Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | * |
| 3 | * Intel Ethernet Controller XL710 Family Linux Driver |
Greg Rose | dc641b7 | 2013-12-18 13:45:51 +0000 | [diff] [blame] | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
Greg Rose | dc641b7 | 2013-12-18 13:45:51 +0000 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program. If not, see <http://www.gnu.org/licenses/>. |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 17 | * |
| 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
| 21 | * Contact Information: |
| 22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 24 | * |
| 25 | ******************************************************************************/ |
| 26 | |
Vasu Dev | 36fac58 | 2013-11-28 06:39:31 +0000 | [diff] [blame] | 27 | #ifndef _I40E_TXRX_H_ |
| 28 | #define _I40E_TXRX_H_ |
| 29 | |
Jesse Brandeburg | aee8087 | 2014-04-09 05:59:02 +0000 | [diff] [blame] | 30 | /* Interrupt Throttling and Rate Limiting Goodies */ |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 31 | |
Shannon Nelson | 3126dcb | 2013-12-21 05:44:47 +0000 | [diff] [blame] | 32 | #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ |
| 33 | #define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */ |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 34 | #define I40E_MAX_IRATE 0x03F |
| 35 | #define I40E_MIN_IRATE 0x001 |
| 36 | #define I40E_IRATE_USEC_RESOLUTION 4 |
| 37 | #define I40E_ITR_100K 0x0005 |
| 38 | #define I40E_ITR_20K 0x0019 |
| 39 | #define I40E_ITR_8K 0x003E |
| 40 | #define I40E_ITR_4K 0x007A |
| 41 | #define I40E_ITR_RX_DEF I40E_ITR_8K |
| 42 | #define I40E_ITR_TX_DEF I40E_ITR_4K |
| 43 | #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ |
| 44 | #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ |
| 45 | #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ |
| 46 | #define I40E_DEFAULT_IRQ_WORK 256 |
| 47 | #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) |
| 48 | #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) |
| 49 | #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) |
| 50 | |
| 51 | #define I40E_QUEUE_END_OF_LIST 0x7FF |
| 52 | |
Jesse Brandeburg | 0319577 | 2013-11-20 10:03:09 +0000 | [diff] [blame] | 53 | /* this enum matches hardware bits and is meant to be used by DYN_CTLN |
| 54 | * registers and QINT registers or more generally anywhere in the manual |
| 55 | * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any |
| 56 | * register but instead is a special value meaning "don't update" ITR0/1/2. |
| 57 | */ |
| 58 | enum i40e_dyn_idx_t { |
| 59 | I40E_IDX_ITR0 = 0, |
| 60 | I40E_IDX_ITR1 = 1, |
| 61 | I40E_IDX_ITR2 = 2, |
| 62 | I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ |
| 63 | }; |
| 64 | |
| 65 | /* these are indexes into ITRN registers */ |
| 66 | #define I40E_RX_ITR I40E_IDX_ITR0 |
| 67 | #define I40E_TX_ITR I40E_IDX_ITR1 |
| 68 | #define I40E_PE_ITR I40E_IDX_ITR2 |
| 69 | |
Mitch Williams | 12dc4fe | 2013-11-28 06:39:32 +0000 | [diff] [blame] | 70 | /* Supported RSS offloads */ |
| 71 | #define I40E_DEFAULT_RSS_HENA ( \ |
Mitch Williams | 12dc4fe | 2013-11-28 06:39:32 +0000 | [diff] [blame] | 72 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ |
| 73 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ |
Mitch Williams | 12dc4fe | 2013-11-28 06:39:32 +0000 | [diff] [blame] | 74 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ |
| 75 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ |
| 76 | ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ |
Mitch Williams | 12dc4fe | 2013-11-28 06:39:32 +0000 | [diff] [blame] | 77 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ |
Mitch Williams | 12dc4fe | 2013-11-28 06:39:32 +0000 | [diff] [blame] | 78 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ |
| 79 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ |
| 80 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ |
| 81 | ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ |
| 82 | ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) |
| 83 | |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 84 | /* Supported Rx Buffer Sizes */ |
| 85 | #define I40E_RXBUFFER_512 512 /* Used for packet split */ |
| 86 | #define I40E_RXBUFFER_2048 2048 |
| 87 | #define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ |
| 88 | #define I40E_RXBUFFER_4096 4096 |
| 89 | #define I40E_RXBUFFER_8192 8192 |
| 90 | #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ |
| 91 | |
| 92 | /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
| 93 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, |
| 94 | * this adds up to 512 bytes of extra data meaning the smallest allocation |
| 95 | * we could have is 1K. |
| 96 | * i.e. RXBUFFER_512 --> size-1024 slab |
| 97 | */ |
| 98 | #define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 |
| 99 | |
| 100 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 101 | #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 102 | #define I40E_RX_NEXT_DESC(r, i, n) \ |
| 103 | do { \ |
| 104 | (i)++; \ |
| 105 | if ((i) == (r)->count) \ |
| 106 | i = 0; \ |
| 107 | (n) = I40E_RX_DESC((r), (i)); \ |
| 108 | } while (0) |
| 109 | |
| 110 | #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ |
| 111 | do { \ |
| 112 | I40E_RX_NEXT_DESC((r), (i), (n)); \ |
| 113 | prefetch((n)); \ |
| 114 | } while (0) |
| 115 | |
| 116 | #define i40e_rx_desc i40e_32byte_rx_desc |
| 117 | |
| 118 | #define I40E_MIN_TX_LEN 17 |
Jesse Brandeburg | 980093e | 2014-05-10 04:49:12 +0000 | [diff] [blame] | 119 | #define I40E_MAX_DATA_PER_TXD 8192 |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 120 | |
| 121 | /* Tx Descriptors needed, worst case */ |
| 122 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) |
Jesse Brandeburg | 980093e | 2014-05-10 04:49:12 +0000 | [diff] [blame] | 123 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 124 | |
| 125 | #define I40E_TX_FLAGS_CSUM (u32)(1) |
| 126 | #define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) |
| 127 | #define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) |
| 128 | #define I40E_TX_FLAGS_TSO (u32)(1 << 3) |
| 129 | #define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) |
| 130 | #define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) |
| 131 | #define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) |
| 132 | #define I40E_TX_FLAGS_FSO (u32)(1 << 7) |
Jacob Keller | beb0dff | 2014-01-11 05:43:19 +0000 | [diff] [blame] | 133 | #define I40E_TX_FLAGS_TSYN (u32)(1 << 8) |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 134 | #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 |
| 135 | #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
| 136 | #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 |
| 137 | #define I40E_TX_FLAGS_VLAN_SHIFT 16 |
| 138 | |
| 139 | struct i40e_tx_buffer { |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 140 | struct i40e_tx_desc *next_to_watch; |
Alexander Duyck | 35a1e2a | 2013-09-28 06:00:17 +0000 | [diff] [blame] | 141 | unsigned long time_stamp; |
| 142 | struct sk_buff *skb; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 143 | unsigned int bytecount; |
Alexander Duyck | 35a1e2a | 2013-09-28 06:00:17 +0000 | [diff] [blame] | 144 | unsigned short gso_segs; |
| 145 | DEFINE_DMA_UNMAP_ADDR(dma); |
| 146 | DEFINE_DMA_UNMAP_LEN(len); |
| 147 | u32 tx_flags; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | struct i40e_rx_buffer { |
| 151 | struct sk_buff *skb; |
| 152 | dma_addr_t dma; |
| 153 | struct page *page; |
| 154 | dma_addr_t page_dma; |
| 155 | unsigned int page_offset; |
| 156 | }; |
| 157 | |
Alexander Duyck | a114d0a | 2013-09-28 06:00:43 +0000 | [diff] [blame] | 158 | struct i40e_queue_stats { |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 159 | u64 packets; |
| 160 | u64 bytes; |
Alexander Duyck | a114d0a | 2013-09-28 06:00:43 +0000 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | struct i40e_tx_queue_stats { |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 164 | u64 restart_queue; |
| 165 | u64 tx_busy; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 166 | u64 tx_done_old; |
| 167 | }; |
| 168 | |
| 169 | struct i40e_rx_queue_stats { |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 170 | u64 non_eop_descs; |
Mitch Williams | 420136c | 2013-12-18 13:45:59 +0000 | [diff] [blame] | 171 | u64 alloc_page_failed; |
| 172 | u64 alloc_buff_failed; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | enum i40e_ring_state_t { |
| 176 | __I40E_TX_FDIR_INIT_DONE, |
| 177 | __I40E_TX_XPS_INIT_DONE, |
| 178 | __I40E_TX_DETECT_HANG, |
| 179 | __I40E_HANG_CHECK_ARMED, |
| 180 | __I40E_RX_PS_ENABLED, |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 181 | __I40E_RX_16BYTE_DESC_ENABLED, |
| 182 | }; |
| 183 | |
| 184 | #define ring_is_ps_enabled(ring) \ |
| 185 | test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) |
| 186 | #define set_ring_ps_enabled(ring) \ |
| 187 | set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) |
| 188 | #define clear_ring_ps_enabled(ring) \ |
| 189 | clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) |
| 190 | #define check_for_tx_hang(ring) \ |
| 191 | test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) |
| 192 | #define set_check_for_tx_hang(ring) \ |
| 193 | set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) |
| 194 | #define clear_check_for_tx_hang(ring) \ |
| 195 | clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 196 | #define ring_is_16byte_desc_enabled(ring) \ |
| 197 | test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) |
| 198 | #define set_ring_16byte_desc_enabled(ring) \ |
| 199 | set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) |
| 200 | #define clear_ring_16byte_desc_enabled(ring) \ |
| 201 | clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) |
| 202 | |
| 203 | /* struct that defines a descriptor ring, associated with a VSI */ |
| 204 | struct i40e_ring { |
Alexander Duyck | cd0b6fa | 2013-09-28 06:00:53 +0000 | [diff] [blame] | 205 | struct i40e_ring *next; /* pointer to next ring in q_vector */ |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 206 | void *desc; /* Descriptor ring memory */ |
| 207 | struct device *dev; /* Used for DMA mapping */ |
| 208 | struct net_device *netdev; /* netdev ring maps to */ |
| 209 | union { |
| 210 | struct i40e_tx_buffer *tx_bi; |
| 211 | struct i40e_rx_buffer *rx_bi; |
| 212 | }; |
| 213 | unsigned long state; |
| 214 | u16 queue_index; /* Queue number of ring */ |
| 215 | u8 dcb_tc; /* Traffic class of ring */ |
| 216 | u8 __iomem *tail; |
| 217 | |
| 218 | u16 count; /* Number of descriptors */ |
| 219 | u16 reg_idx; /* HW register index of the ring */ |
| 220 | u16 rx_hdr_len; |
| 221 | u16 rx_buf_len; |
| 222 | u8 dtype; |
| 223 | #define I40E_RX_DTYPE_NO_SPLIT 0 |
| 224 | #define I40E_RX_DTYPE_SPLIT_ALWAYS 1 |
| 225 | #define I40E_RX_DTYPE_HEADER_SPLIT 2 |
| 226 | u8 hsplit; |
| 227 | #define I40E_RX_SPLIT_L2 0x1 |
| 228 | #define I40E_RX_SPLIT_IP 0x2 |
| 229 | #define I40E_RX_SPLIT_TCP_UDP 0x4 |
| 230 | #define I40E_RX_SPLIT_SCTP 0x8 |
| 231 | |
| 232 | /* used in interrupt processing */ |
| 233 | u16 next_to_use; |
| 234 | u16 next_to_clean; |
| 235 | |
| 236 | u8 atr_sample_rate; |
| 237 | u8 atr_count; |
| 238 | |
Jacob Keller | beb0dff | 2014-01-11 05:43:19 +0000 | [diff] [blame] | 239 | unsigned long last_rx_timestamp; |
| 240 | |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 241 | bool ring_active; /* is ring online or not */ |
| 242 | |
| 243 | /* stats structs */ |
Alexander Duyck | a114d0a | 2013-09-28 06:00:43 +0000 | [diff] [blame] | 244 | struct i40e_queue_stats stats; |
Alexander Duyck | 980e9b1 | 2013-09-28 06:01:03 +0000 | [diff] [blame] | 245 | struct u64_stats_sync syncp; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 246 | union { |
| 247 | struct i40e_tx_queue_stats tx_stats; |
| 248 | struct i40e_rx_queue_stats rx_stats; |
| 249 | }; |
| 250 | |
| 251 | unsigned int size; /* length of descriptor ring in bytes */ |
| 252 | dma_addr_t dma; /* physical address of ring */ |
| 253 | |
| 254 | struct i40e_vsi *vsi; /* Backreference to associated VSI */ |
| 255 | struct i40e_q_vector *q_vector; /* Backreference to associated vector */ |
Alexander Duyck | 9f65e15b | 2013-09-28 06:00:58 +0000 | [diff] [blame] | 256 | |
| 257 | struct rcu_head rcu; /* to avoid race on free */ |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 258 | } ____cacheline_internodealigned_in_smp; |
| 259 | |
| 260 | enum i40e_latency_range { |
| 261 | I40E_LOWEST_LATENCY = 0, |
| 262 | I40E_LOW_LATENCY = 1, |
| 263 | I40E_BULK_LATENCY = 2, |
| 264 | }; |
| 265 | |
| 266 | struct i40e_ring_container { |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 267 | /* array of pointers to rings */ |
Alexander Duyck | cd0b6fa | 2013-09-28 06:00:53 +0000 | [diff] [blame] | 268 | struct i40e_ring *ring; |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 269 | unsigned int total_bytes; /* total bytes processed this int */ |
| 270 | unsigned int total_packets; /* total packets processed this int */ |
| 271 | u16 count; |
| 272 | enum i40e_latency_range latency_range; |
| 273 | u16 itr; |
| 274 | }; |
| 275 | |
Alexander Duyck | cd0b6fa | 2013-09-28 06:00:53 +0000 | [diff] [blame] | 276 | /* iterator for handling rings in ring container */ |
| 277 | #define i40e_for_each_ring(pos, head) \ |
| 278 | for (pos = (head).ring; pos != NULL; pos = pos->next) |
| 279 | |
Jesse Brandeburg | 7daa6bf | 2013-09-11 08:40:01 +0000 | [diff] [blame] | 280 | void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); |
| 281 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
| 282 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring); |
| 283 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring); |
| 284 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); |
| 285 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); |
| 286 | void i40e_free_tx_resources(struct i40e_ring *tx_ring); |
| 287 | void i40e_free_rx_resources(struct i40e_ring *rx_ring); |
| 288 | int i40e_napi_poll(struct napi_struct *napi, int budget); |
Vasu Dev | 36fac58 | 2013-11-28 06:39:31 +0000 | [diff] [blame] | 289 | #endif /* _I40E_TXRX_H_ */ |