Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012,2013 - ARM Ltd |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * Derived from arch/arm/kvm/coproc.c: |
| 6 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University |
| 7 | * Authors: Rusty Russell <rusty@rustcorp.com.au> |
| 8 | * Christoffer Dall <c.dall@virtualopensystems.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License, version 2, as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 23 | #include <linux/kvm_host.h> |
Mark Rutland | c6d01a9 | 2014-11-24 13:59:30 +0000 | [diff] [blame] | 24 | #include <linux/mm.h> |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 25 | #include <linux/uaccess.h> |
Mark Rutland | c6d01a9 | 2014-11-24 13:59:30 +0000 | [diff] [blame] | 26 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 27 | #include <asm/cacheflush.h> |
| 28 | #include <asm/cputype.h> |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 29 | #include <asm/debug-monitors.h> |
Mark Rutland | c6d01a9 | 2014-11-24 13:59:30 +0000 | [diff] [blame] | 30 | #include <asm/esr.h> |
| 31 | #include <asm/kvm_arm.h> |
| 32 | #include <asm/kvm_coproc.h> |
| 33 | #include <asm/kvm_emulate.h> |
| 34 | #include <asm/kvm_host.h> |
| 35 | #include <asm/kvm_mmu.h> |
| 36 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 37 | #include <trace/events/kvm.h> |
| 38 | |
| 39 | #include "sys_regs.h" |
| 40 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 41 | #include "trace.h" |
| 42 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 43 | /* |
| 44 | * All of this file is extremly similar to the ARM coproc.c, but the |
| 45 | * types are different. My gut feeling is that it should be pretty |
| 46 | * easy to merge, but that would be an ABI breakage -- again. VFP |
| 47 | * would also need to be abstracted. |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 48 | * |
| 49 | * For AArch32, we only take care of what is being trapped. Anything |
| 50 | * that has to do with init and userspace access has to go via the |
| 51 | * 64bit interface. |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 52 | */ |
| 53 | |
| 54 | /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ |
| 55 | static u32 cache_levels; |
| 56 | |
| 57 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ |
| 58 | #define CSSELR_MAX 12 |
| 59 | |
| 60 | /* Which cache CCSIDR represents depends on CSSELR value. */ |
| 61 | static u32 get_ccsidr(u32 csselr) |
| 62 | { |
| 63 | u32 ccsidr; |
| 64 | |
| 65 | /* Make sure noone else changes CSSELR during this! */ |
| 66 | local_irq_disable(); |
| 67 | /* Put value into CSSELR */ |
| 68 | asm volatile("msr csselr_el1, %x0" : : "r" (csselr)); |
| 69 | isb(); |
| 70 | /* Read result out of CCSIDR */ |
| 71 | asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr)); |
| 72 | local_irq_enable(); |
| 73 | |
| 74 | return ccsidr; |
| 75 | } |
| 76 | |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 77 | /* |
| 78 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). |
| 79 | */ |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 80 | static bool access_dcsw(struct kvm_vcpu *vcpu, |
| 81 | const struct sys_reg_params *p, |
| 82 | const struct sys_reg_desc *r) |
| 83 | { |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 84 | if (!p->is_write) |
| 85 | return read_from_write_only(vcpu, p); |
| 86 | |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 87 | kvm_set_way_flush(vcpu); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 88 | return true; |
| 89 | } |
| 90 | |
| 91 | /* |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 92 | * Generic accessor for VM registers. Only called as long as HCR_TVM |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 93 | * is set. If the guest enables the MMU, we stop trapping the VM |
| 94 | * sys_regs and leave it in complete control of the caches. |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 95 | */ |
| 96 | static bool access_vm_reg(struct kvm_vcpu *vcpu, |
| 97 | const struct sys_reg_params *p, |
| 98 | const struct sys_reg_desc *r) |
| 99 | { |
| 100 | unsigned long val; |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 101 | bool was_enabled = vcpu_has_cache_enabled(vcpu); |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 102 | |
| 103 | BUG_ON(!p->is_write); |
| 104 | |
| 105 | val = *vcpu_reg(vcpu, p->Rt); |
Marc Zyngier | dedf97e | 2014-08-01 12:00:36 +0100 | [diff] [blame] | 106 | if (!p->is_aarch32) { |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 107 | vcpu_sys_reg(vcpu, r->reg) = val; |
Marc Zyngier | dedf97e | 2014-08-01 12:00:36 +0100 | [diff] [blame] | 108 | } else { |
| 109 | if (!p->is_32bit) |
| 110 | vcpu_cp15_64_high(vcpu, r->reg) = val >> 32; |
Victor Kamensky | f0a3eaf | 2014-07-02 17:19:30 +0100 | [diff] [blame] | 111 | vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL; |
Marc Zyngier | dedf97e | 2014-08-01 12:00:36 +0100 | [diff] [blame] | 112 | } |
Victor Kamensky | f0a3eaf | 2014-07-02 17:19:30 +0100 | [diff] [blame] | 113 | |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 114 | kvm_toggle_cache(vcpu, was_enabled); |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 115 | return true; |
| 116 | } |
| 117 | |
Andre Przywara | 6d52f35 | 2014-06-03 10:13:13 +0200 | [diff] [blame] | 118 | /* |
| 119 | * Trap handler for the GICv3 SGI generation system register. |
| 120 | * Forward the request to the VGIC emulation. |
| 121 | * The cp15_64 code makes sure this automatically works |
| 122 | * for both AArch64 and AArch32 accesses. |
| 123 | */ |
| 124 | static bool access_gic_sgi(struct kvm_vcpu *vcpu, |
| 125 | const struct sys_reg_params *p, |
| 126 | const struct sys_reg_desc *r) |
| 127 | { |
| 128 | u64 val; |
| 129 | |
| 130 | if (!p->is_write) |
| 131 | return read_from_write_only(vcpu, p); |
| 132 | |
| 133 | val = *vcpu_reg(vcpu, p->Rt); |
| 134 | vgic_v3_dispatch_sgi(vcpu, val); |
| 135 | |
| 136 | return true; |
| 137 | } |
| 138 | |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 139 | static bool trap_raz_wi(struct kvm_vcpu *vcpu, |
| 140 | const struct sys_reg_params *p, |
| 141 | const struct sys_reg_desc *r) |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 142 | { |
| 143 | if (p->is_write) |
| 144 | return ignore_write(vcpu, p); |
| 145 | else |
| 146 | return read_zero(vcpu, p); |
| 147 | } |
| 148 | |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 149 | static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, |
| 150 | const struct sys_reg_params *p, |
| 151 | const struct sys_reg_desc *r) |
| 152 | { |
| 153 | if (p->is_write) { |
| 154 | return ignore_write(vcpu, p); |
| 155 | } else { |
| 156 | *vcpu_reg(vcpu, p->Rt) = (1 << 3); |
| 157 | return true; |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, |
| 162 | const struct sys_reg_params *p, |
| 163 | const struct sys_reg_desc *r) |
| 164 | { |
| 165 | if (p->is_write) { |
| 166 | return ignore_write(vcpu, p); |
| 167 | } else { |
| 168 | u32 val; |
| 169 | asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val)); |
| 170 | *vcpu_reg(vcpu, p->Rt) = val; |
| 171 | return true; |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * We want to avoid world-switching all the DBG registers all the |
| 177 | * time: |
| 178 | * |
| 179 | * - If we've touched any debug register, it is likely that we're |
| 180 | * going to touch more of them. It then makes sense to disable the |
| 181 | * traps and start doing the save/restore dance |
| 182 | * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is |
| 183 | * then mandatory to save/restore the registers, as the guest |
| 184 | * depends on them. |
| 185 | * |
| 186 | * For this, we use a DIRTY bit, indicating the guest has modified the |
| 187 | * debug registers, used as follow: |
| 188 | * |
| 189 | * On guest entry: |
| 190 | * - If the dirty bit is set (because we're coming back from trapping), |
| 191 | * disable the traps, save host registers, restore guest registers. |
| 192 | * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), |
| 193 | * set the dirty bit, disable the traps, save host registers, |
| 194 | * restore guest registers. |
| 195 | * - Otherwise, enable the traps |
| 196 | * |
| 197 | * On guest exit: |
| 198 | * - If the dirty bit is set, save guest registers, restore host |
| 199 | * registers and clear the dirty bit. This ensure that the host can |
| 200 | * now use the debug registers. |
| 201 | */ |
| 202 | static bool trap_debug_regs(struct kvm_vcpu *vcpu, |
| 203 | const struct sys_reg_params *p, |
| 204 | const struct sys_reg_desc *r) |
| 205 | { |
| 206 | if (p->is_write) { |
| 207 | vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt); |
| 208 | vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; |
| 209 | } else { |
| 210 | *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); |
| 211 | } |
| 212 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 213 | trace_trap_reg(__func__, r->reg, p->is_write, *vcpu_reg(vcpu, p->Rt)); |
| 214 | |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 215 | return true; |
| 216 | } |
| 217 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 218 | /* |
| 219 | * reg_to_dbg/dbg_to_reg |
| 220 | * |
| 221 | * A 32 bit write to a debug register leave top bits alone |
| 222 | * A 32 bit read from a debug register only returns the bottom bits |
| 223 | * |
| 224 | * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the |
| 225 | * hyp.S code switches between host and guest values in future. |
| 226 | */ |
| 227 | static inline void reg_to_dbg(struct kvm_vcpu *vcpu, |
| 228 | const struct sys_reg_params *p, |
| 229 | u64 *dbg_reg) |
| 230 | { |
| 231 | u64 val = *vcpu_reg(vcpu, p->Rt); |
| 232 | |
| 233 | if (p->is_32bit) { |
| 234 | val &= 0xffffffffUL; |
| 235 | val |= ((*dbg_reg >> 32) << 32); |
| 236 | } |
| 237 | |
| 238 | *dbg_reg = val; |
| 239 | vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; |
| 240 | } |
| 241 | |
| 242 | static inline void dbg_to_reg(struct kvm_vcpu *vcpu, |
| 243 | const struct sys_reg_params *p, |
| 244 | u64 *dbg_reg) |
| 245 | { |
| 246 | u64 val = *dbg_reg; |
| 247 | |
| 248 | if (p->is_32bit) |
| 249 | val &= 0xffffffffUL; |
| 250 | |
| 251 | *vcpu_reg(vcpu, p->Rt) = val; |
| 252 | } |
| 253 | |
| 254 | static inline bool trap_bvr(struct kvm_vcpu *vcpu, |
| 255 | const struct sys_reg_params *p, |
| 256 | const struct sys_reg_desc *rd) |
| 257 | { |
| 258 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; |
| 259 | |
| 260 | if (p->is_write) |
| 261 | reg_to_dbg(vcpu, p, dbg_reg); |
| 262 | else |
| 263 | dbg_to_reg(vcpu, p, dbg_reg); |
| 264 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 265 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
| 266 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 267 | return true; |
| 268 | } |
| 269 | |
| 270 | static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 271 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 272 | { |
| 273 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; |
| 274 | |
| 275 | if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 276 | return -EFAULT; |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 281 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 282 | { |
| 283 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; |
| 284 | |
| 285 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 286 | return -EFAULT; |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static inline void reset_bvr(struct kvm_vcpu *vcpu, |
| 291 | const struct sys_reg_desc *rd) |
| 292 | { |
| 293 | vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; |
| 294 | } |
| 295 | |
| 296 | static inline bool trap_bcr(struct kvm_vcpu *vcpu, |
| 297 | const struct sys_reg_params *p, |
| 298 | const struct sys_reg_desc *rd) |
| 299 | { |
| 300 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; |
| 301 | |
| 302 | if (p->is_write) |
| 303 | reg_to_dbg(vcpu, p, dbg_reg); |
| 304 | else |
| 305 | dbg_to_reg(vcpu, p, dbg_reg); |
| 306 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 307 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
| 308 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 309 | return true; |
| 310 | } |
| 311 | |
| 312 | static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 313 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 314 | { |
| 315 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; |
| 316 | |
| 317 | if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 318 | return -EFAULT; |
| 319 | |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 324 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 325 | { |
| 326 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; |
| 327 | |
| 328 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 329 | return -EFAULT; |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | static inline void reset_bcr(struct kvm_vcpu *vcpu, |
| 334 | const struct sys_reg_desc *rd) |
| 335 | { |
| 336 | vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; |
| 337 | } |
| 338 | |
| 339 | static inline bool trap_wvr(struct kvm_vcpu *vcpu, |
| 340 | const struct sys_reg_params *p, |
| 341 | const struct sys_reg_desc *rd) |
| 342 | { |
| 343 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; |
| 344 | |
| 345 | if (p->is_write) |
| 346 | reg_to_dbg(vcpu, p, dbg_reg); |
| 347 | else |
| 348 | dbg_to_reg(vcpu, p, dbg_reg); |
| 349 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 350 | trace_trap_reg(__func__, rd->reg, p->is_write, |
| 351 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); |
| 352 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 353 | return true; |
| 354 | } |
| 355 | |
| 356 | static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 357 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 358 | { |
| 359 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; |
| 360 | |
| 361 | if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 362 | return -EFAULT; |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 367 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 368 | { |
| 369 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; |
| 370 | |
| 371 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 372 | return -EFAULT; |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static inline void reset_wvr(struct kvm_vcpu *vcpu, |
| 377 | const struct sys_reg_desc *rd) |
| 378 | { |
| 379 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; |
| 380 | } |
| 381 | |
| 382 | static inline bool trap_wcr(struct kvm_vcpu *vcpu, |
| 383 | const struct sys_reg_params *p, |
| 384 | const struct sys_reg_desc *rd) |
| 385 | { |
| 386 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; |
| 387 | |
| 388 | if (p->is_write) |
| 389 | reg_to_dbg(vcpu, p, dbg_reg); |
| 390 | else |
| 391 | dbg_to_reg(vcpu, p, dbg_reg); |
| 392 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 393 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
| 394 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 395 | return true; |
| 396 | } |
| 397 | |
| 398 | static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 399 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 400 | { |
| 401 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; |
| 402 | |
| 403 | if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 404 | return -EFAULT; |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
| 409 | const struct kvm_one_reg *reg, void __user *uaddr) |
| 410 | { |
| 411 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; |
| 412 | |
| 413 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) |
| 414 | return -EFAULT; |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | static inline void reset_wcr(struct kvm_vcpu *vcpu, |
| 419 | const struct sys_reg_desc *rd) |
| 420 | { |
| 421 | vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; |
| 422 | } |
| 423 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 424 | static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
| 425 | { |
| 426 | u64 amair; |
| 427 | |
| 428 | asm volatile("mrs %0, amair_el1\n" : "=r" (amair)); |
| 429 | vcpu_sys_reg(vcpu, AMAIR_EL1) = amair; |
| 430 | } |
| 431 | |
| 432 | static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
| 433 | { |
Andre Przywara | 4429fc6 | 2014-06-02 15:37:13 +0200 | [diff] [blame] | 434 | u64 mpidr; |
| 435 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 436 | /* |
Andre Przywara | 4429fc6 | 2014-06-02 15:37:13 +0200 | [diff] [blame] | 437 | * Map the vcpu_id into the first three affinity level fields of |
| 438 | * the MPIDR. We limit the number of VCPUs in level 0 due to a |
| 439 | * limitation to 16 CPUs in that level in the ICC_SGIxR registers |
| 440 | * of the GICv3 to be able to address each CPU directly when |
| 441 | * sending IPIs. |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 442 | */ |
Andre Przywara | 4429fc6 | 2014-06-02 15:37:13 +0200 | [diff] [blame] | 443 | mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); |
| 444 | mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); |
| 445 | mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); |
| 446 | vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 447 | } |
| 448 | |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 449 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ |
| 450 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ |
| 451 | /* DBGBVRn_EL1 */ \ |
| 452 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \ |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 453 | trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \ |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 454 | /* DBGBCRn_EL1 */ \ |
| 455 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \ |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 456 | trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \ |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 457 | /* DBGWVRn_EL1 */ \ |
| 458 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \ |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 459 | trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \ |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 460 | /* DBGWCRn_EL1 */ \ |
| 461 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \ |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 462 | trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr } |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 463 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 464 | /* |
| 465 | * Architected system registers. |
| 466 | * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 467 | * |
| 468 | * We could trap ID_DFR0 and tell the guest we don't support performance |
| 469 | * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was |
| 470 | * NAKed, so it will read the PMCR anyway. |
| 471 | * |
| 472 | * Therefore we tell the guest we have 0 counters. Unfortunately, we |
| 473 | * must always support PMCCNTR (the cycle counter): we just RAZ/WI for |
| 474 | * all PM registers, which doesn't crash the guest kernel at least. |
| 475 | * |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 476 | * Debug handling: We do trap most, if not all debug related system |
| 477 | * registers. The implementation is good enough to ensure that a guest |
| 478 | * can use these with minimal performance degradation. The drawback is |
| 479 | * that we don't implement any of the external debug, none of the |
| 480 | * OSlock protocol. This should be revisited if we ever encounter a |
| 481 | * more demanding guest... |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 482 | */ |
| 483 | static const struct sys_reg_desc sys_reg_descs[] = { |
| 484 | /* DC ISW */ |
| 485 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010), |
| 486 | access_dcsw }, |
| 487 | /* DC CSW */ |
| 488 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010), |
| 489 | access_dcsw }, |
| 490 | /* DC CISW */ |
| 491 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010), |
| 492 | access_dcsw }, |
| 493 | |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 494 | DBG_BCR_BVR_WCR_WVR_EL1(0), |
| 495 | DBG_BCR_BVR_WCR_WVR_EL1(1), |
| 496 | /* MDCCINT_EL1 */ |
| 497 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000), |
| 498 | trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, |
| 499 | /* MDSCR_EL1 */ |
| 500 | { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010), |
| 501 | trap_debug_regs, reset_val, MDSCR_EL1, 0 }, |
| 502 | DBG_BCR_BVR_WCR_WVR_EL1(2), |
| 503 | DBG_BCR_BVR_WCR_WVR_EL1(3), |
| 504 | DBG_BCR_BVR_WCR_WVR_EL1(4), |
| 505 | DBG_BCR_BVR_WCR_WVR_EL1(5), |
| 506 | DBG_BCR_BVR_WCR_WVR_EL1(6), |
| 507 | DBG_BCR_BVR_WCR_WVR_EL1(7), |
| 508 | DBG_BCR_BVR_WCR_WVR_EL1(8), |
| 509 | DBG_BCR_BVR_WCR_WVR_EL1(9), |
| 510 | DBG_BCR_BVR_WCR_WVR_EL1(10), |
| 511 | DBG_BCR_BVR_WCR_WVR_EL1(11), |
| 512 | DBG_BCR_BVR_WCR_WVR_EL1(12), |
| 513 | DBG_BCR_BVR_WCR_WVR_EL1(13), |
| 514 | DBG_BCR_BVR_WCR_WVR_EL1(14), |
| 515 | DBG_BCR_BVR_WCR_WVR_EL1(15), |
| 516 | |
| 517 | /* MDRAR_EL1 */ |
| 518 | { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000), |
| 519 | trap_raz_wi }, |
| 520 | /* OSLAR_EL1 */ |
| 521 | { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100), |
| 522 | trap_raz_wi }, |
| 523 | /* OSLSR_EL1 */ |
| 524 | { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100), |
| 525 | trap_oslsr_el1 }, |
| 526 | /* OSDLR_EL1 */ |
| 527 | { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100), |
| 528 | trap_raz_wi }, |
| 529 | /* DBGPRCR_EL1 */ |
| 530 | { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100), |
| 531 | trap_raz_wi }, |
| 532 | /* DBGCLAIMSET_EL1 */ |
| 533 | { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110), |
| 534 | trap_raz_wi }, |
| 535 | /* DBGCLAIMCLR_EL1 */ |
| 536 | { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110), |
| 537 | trap_raz_wi }, |
| 538 | /* DBGAUTHSTATUS_EL1 */ |
| 539 | { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110), |
| 540 | trap_dbgauthstatus_el1 }, |
| 541 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 542 | /* TEECR32_EL1 */ |
| 543 | { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000), |
| 544 | NULL, reset_val, TEECR32_EL1, 0 }, |
| 545 | /* TEEHBR32_EL1 */ |
| 546 | { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000), |
| 547 | NULL, reset_val, TEEHBR32_EL1, 0 }, |
Marc Zyngier | 0c557ed | 2014-04-24 10:24:46 +0100 | [diff] [blame] | 548 | |
| 549 | /* MDCCSR_EL1 */ |
| 550 | { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000), |
| 551 | trap_raz_wi }, |
| 552 | /* DBGDTR_EL0 */ |
| 553 | { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000), |
| 554 | trap_raz_wi }, |
| 555 | /* DBGDTR[TR]X_EL0 */ |
| 556 | { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000), |
| 557 | trap_raz_wi }, |
| 558 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 559 | /* DBGVCR32_EL2 */ |
| 560 | { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000), |
| 561 | NULL, reset_val, DBGVCR32_EL2, 0 }, |
| 562 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 563 | /* MPIDR_EL1 */ |
| 564 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101), |
| 565 | NULL, reset_mpidr, MPIDR_EL1 }, |
| 566 | /* SCTLR_EL1 */ |
| 567 | { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000), |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 568 | access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 569 | /* CPACR_EL1 */ |
| 570 | { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010), |
| 571 | NULL, reset_val, CPACR_EL1, 0 }, |
| 572 | /* TTBR0_EL1 */ |
| 573 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 574 | access_vm_reg, reset_unknown, TTBR0_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 575 | /* TTBR1_EL1 */ |
| 576 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 577 | access_vm_reg, reset_unknown, TTBR1_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 578 | /* TCR_EL1 */ |
| 579 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 580 | access_vm_reg, reset_val, TCR_EL1, 0 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 581 | |
| 582 | /* AFSR0_EL1 */ |
| 583 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 584 | access_vm_reg, reset_unknown, AFSR0_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 585 | /* AFSR1_EL1 */ |
| 586 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 587 | access_vm_reg, reset_unknown, AFSR1_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 588 | /* ESR_EL1 */ |
| 589 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 590 | access_vm_reg, reset_unknown, ESR_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 591 | /* FAR_EL1 */ |
| 592 | { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 593 | access_vm_reg, reset_unknown, FAR_EL1 }, |
Marc Zyngier | 1bbd805 | 2013-06-07 11:02:34 +0100 | [diff] [blame] | 594 | /* PAR_EL1 */ |
| 595 | { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000), |
| 596 | NULL, reset_unknown, PAR_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 597 | |
| 598 | /* PMINTENSET_EL1 */ |
| 599 | { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 600 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 601 | /* PMINTENCLR_EL1 */ |
| 602 | { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 603 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 604 | |
| 605 | /* MAIR_EL1 */ |
| 606 | { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 607 | access_vm_reg, reset_unknown, MAIR_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 608 | /* AMAIR_EL1 */ |
| 609 | { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 610 | access_vm_reg, reset_amair_el1, AMAIR_EL1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 611 | |
| 612 | /* VBAR_EL1 */ |
| 613 | { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000), |
| 614 | NULL, reset_val, VBAR_EL1, 0 }, |
Christoffer Dall | db7dedd | 2014-11-19 11:23:54 +0000 | [diff] [blame] | 615 | |
Andre Przywara | 6d52f35 | 2014-06-03 10:13:13 +0200 | [diff] [blame] | 616 | /* ICC_SGI1R_EL1 */ |
| 617 | { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101), |
| 618 | access_gic_sgi }, |
Christoffer Dall | db7dedd | 2014-11-19 11:23:54 +0000 | [diff] [blame] | 619 | /* ICC_SRE_EL1 */ |
| 620 | { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101), |
| 621 | trap_raz_wi }, |
| 622 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 623 | /* CONTEXTIDR_EL1 */ |
| 624 | { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001), |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 625 | access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 626 | /* TPIDR_EL1 */ |
| 627 | { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100), |
| 628 | NULL, reset_unknown, TPIDR_EL1 }, |
| 629 | |
| 630 | /* CNTKCTL_EL1 */ |
| 631 | { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000), |
| 632 | NULL, reset_val, CNTKCTL_EL1, 0}, |
| 633 | |
| 634 | /* CSSELR_EL1 */ |
| 635 | { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000), |
| 636 | NULL, reset_unknown, CSSELR_EL1 }, |
| 637 | |
| 638 | /* PMCR_EL0 */ |
| 639 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 640 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 641 | /* PMCNTENSET_EL0 */ |
| 642 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 643 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 644 | /* PMCNTENCLR_EL0 */ |
| 645 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 646 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 647 | /* PMOVSCLR_EL0 */ |
| 648 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 649 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 650 | /* PMSWINC_EL0 */ |
| 651 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 652 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 653 | /* PMSELR_EL0 */ |
| 654 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 655 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 656 | /* PMCEID0_EL0 */ |
| 657 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 658 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 659 | /* PMCEID1_EL0 */ |
| 660 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 661 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 662 | /* PMCCNTR_EL0 */ |
| 663 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 664 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 665 | /* PMXEVTYPER_EL0 */ |
| 666 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 667 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 668 | /* PMXEVCNTR_EL0 */ |
| 669 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 670 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 671 | /* PMUSERENR_EL0 */ |
| 672 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 673 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 674 | /* PMOVSSET_EL0 */ |
| 675 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 676 | trap_raz_wi }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 677 | |
| 678 | /* TPIDR_EL0 */ |
| 679 | { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010), |
| 680 | NULL, reset_unknown, TPIDR_EL0 }, |
| 681 | /* TPIDRRO_EL0 */ |
| 682 | { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011), |
| 683 | NULL, reset_unknown, TPIDRRO_EL0 }, |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 684 | |
| 685 | /* DACR32_EL2 */ |
| 686 | { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000), |
| 687 | NULL, reset_unknown, DACR32_EL2 }, |
| 688 | /* IFSR32_EL2 */ |
| 689 | { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001), |
| 690 | NULL, reset_unknown, IFSR32_EL2 }, |
| 691 | /* FPEXC32_EL2 */ |
| 692 | { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000), |
| 693 | NULL, reset_val, FPEXC32_EL2, 0x70 }, |
| 694 | }; |
| 695 | |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 696 | static bool trap_dbgidr(struct kvm_vcpu *vcpu, |
| 697 | const struct sys_reg_params *p, |
| 698 | const struct sys_reg_desc *r) |
| 699 | { |
| 700 | if (p->is_write) { |
| 701 | return ignore_write(vcpu, p); |
| 702 | } else { |
| 703 | u64 dfr = read_cpuid(ID_AA64DFR0_EL1); |
| 704 | u64 pfr = read_cpuid(ID_AA64PFR0_EL1); |
| 705 | u32 el3 = !!((pfr >> 12) & 0xf); |
| 706 | |
| 707 | *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) | |
| 708 | (((dfr >> 12) & 0xf) << 24) | |
| 709 | (((dfr >> 28) & 0xf) << 20) | |
| 710 | (6 << 16) | (el3 << 14) | (el3 << 12)); |
| 711 | return true; |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | static bool trap_debug32(struct kvm_vcpu *vcpu, |
| 716 | const struct sys_reg_params *p, |
| 717 | const struct sys_reg_desc *r) |
| 718 | { |
| 719 | if (p->is_write) { |
| 720 | vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt); |
| 721 | vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; |
| 722 | } else { |
| 723 | *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg); |
| 724 | } |
| 725 | |
| 726 | return true; |
| 727 | } |
| 728 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 729 | /* AArch32 debug register mappings |
| 730 | * |
| 731 | * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] |
| 732 | * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] |
| 733 | * |
| 734 | * All control registers and watchpoint value registers are mapped to |
| 735 | * the lower 32 bits of their AArch64 equivalents. We share the trap |
| 736 | * handlers with the above AArch64 code which checks what mode the |
| 737 | * system is in. |
| 738 | */ |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 739 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 740 | static inline bool trap_xvr(struct kvm_vcpu *vcpu, |
| 741 | const struct sys_reg_params *p, |
| 742 | const struct sys_reg_desc *rd) |
| 743 | { |
| 744 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; |
| 745 | |
| 746 | if (p->is_write) { |
| 747 | u64 val = *dbg_reg; |
| 748 | |
| 749 | val &= 0xffffffffUL; |
| 750 | val |= *vcpu_reg(vcpu, p->Rt) << 32; |
| 751 | *dbg_reg = val; |
| 752 | |
| 753 | vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; |
| 754 | } else { |
| 755 | *vcpu_reg(vcpu, p->Rt) = *dbg_reg >> 32; |
| 756 | } |
| 757 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 758 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
| 759 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 760 | return true; |
| 761 | } |
| 762 | |
| 763 | #define DBG_BCR_BVR_WCR_WVR(n) \ |
| 764 | /* DBGBVRn */ \ |
| 765 | { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ |
| 766 | /* DBGBCRn */ \ |
| 767 | { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ |
| 768 | /* DBGWVRn */ \ |
| 769 | { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ |
| 770 | /* DBGWCRn */ \ |
| 771 | { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } |
| 772 | |
| 773 | #define DBGBXVR(n) \ |
| 774 | { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 775 | |
| 776 | /* |
| 777 | * Trapped cp14 registers. We generally ignore most of the external |
| 778 | * debug, on the principle that they don't really make sense to a |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 779 | * guest. Revisit this one day, would this principle change. |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 780 | */ |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 781 | static const struct sys_reg_desc cp14_regs[] = { |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 782 | /* DBGIDR */ |
| 783 | { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, |
| 784 | /* DBGDTRRXext */ |
| 785 | { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, |
| 786 | |
| 787 | DBG_BCR_BVR_WCR_WVR(0), |
| 788 | /* DBGDSCRint */ |
| 789 | { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, |
| 790 | DBG_BCR_BVR_WCR_WVR(1), |
| 791 | /* DBGDCCINT */ |
| 792 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, |
| 793 | /* DBGDSCRext */ |
| 794 | { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, |
| 795 | DBG_BCR_BVR_WCR_WVR(2), |
| 796 | /* DBGDTR[RT]Xint */ |
| 797 | { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, |
| 798 | /* DBGDTR[RT]Xext */ |
| 799 | { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, |
| 800 | DBG_BCR_BVR_WCR_WVR(3), |
| 801 | DBG_BCR_BVR_WCR_WVR(4), |
| 802 | DBG_BCR_BVR_WCR_WVR(5), |
| 803 | /* DBGWFAR */ |
| 804 | { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, |
| 805 | /* DBGOSECCR */ |
| 806 | { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, |
| 807 | DBG_BCR_BVR_WCR_WVR(6), |
| 808 | /* DBGVCR */ |
| 809 | { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, |
| 810 | DBG_BCR_BVR_WCR_WVR(7), |
| 811 | DBG_BCR_BVR_WCR_WVR(8), |
| 812 | DBG_BCR_BVR_WCR_WVR(9), |
| 813 | DBG_BCR_BVR_WCR_WVR(10), |
| 814 | DBG_BCR_BVR_WCR_WVR(11), |
| 815 | DBG_BCR_BVR_WCR_WVR(12), |
| 816 | DBG_BCR_BVR_WCR_WVR(13), |
| 817 | DBG_BCR_BVR_WCR_WVR(14), |
| 818 | DBG_BCR_BVR_WCR_WVR(15), |
| 819 | |
| 820 | /* DBGDRAR (32bit) */ |
| 821 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, |
| 822 | |
| 823 | DBGBXVR(0), |
| 824 | /* DBGOSLAR */ |
| 825 | { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, |
| 826 | DBGBXVR(1), |
| 827 | /* DBGOSLSR */ |
| 828 | { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, |
| 829 | DBGBXVR(2), |
| 830 | DBGBXVR(3), |
| 831 | /* DBGOSDLR */ |
| 832 | { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, |
| 833 | DBGBXVR(4), |
| 834 | /* DBGPRCR */ |
| 835 | { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, |
| 836 | DBGBXVR(5), |
| 837 | DBGBXVR(6), |
| 838 | DBGBXVR(7), |
| 839 | DBGBXVR(8), |
| 840 | DBGBXVR(9), |
| 841 | DBGBXVR(10), |
| 842 | DBGBXVR(11), |
| 843 | DBGBXVR(12), |
| 844 | DBGBXVR(13), |
| 845 | DBGBXVR(14), |
| 846 | DBGBXVR(15), |
| 847 | |
| 848 | /* DBGDSAR (32bit) */ |
| 849 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, |
| 850 | |
| 851 | /* DBGDEVID2 */ |
| 852 | { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, |
| 853 | /* DBGDEVID1 */ |
| 854 | { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, |
| 855 | /* DBGDEVID */ |
| 856 | { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, |
| 857 | /* DBGCLAIMSET */ |
| 858 | { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, |
| 859 | /* DBGCLAIMCLR */ |
| 860 | { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, |
| 861 | /* DBGAUTHSTATUS */ |
| 862 | { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 863 | }; |
| 864 | |
Marc Zyngier | a9866ba0 | 2014-04-24 14:11:48 +0100 | [diff] [blame] | 865 | /* Trapped cp14 64bit registers */ |
| 866 | static const struct sys_reg_desc cp14_64_regs[] = { |
Marc Zyngier | bdfb4b3 | 2014-04-24 10:31:37 +0100 | [diff] [blame] | 867 | /* DBGDRAR (64bit) */ |
| 868 | { Op1( 0), CRm( 1), .access = trap_raz_wi }, |
| 869 | |
| 870 | /* DBGDSAR (64bit) */ |
| 871 | { Op1( 0), CRm( 2), .access = trap_raz_wi }, |
Marc Zyngier | a9866ba0 | 2014-04-24 14:11:48 +0100 | [diff] [blame] | 872 | }; |
| 873 | |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 874 | /* |
| 875 | * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, |
| 876 | * depending on the way they are accessed (as a 32bit or a 64bit |
| 877 | * register). |
| 878 | */ |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 879 | static const struct sys_reg_desc cp15_regs[] = { |
Andre Przywara | 6d52f35 | 2014-06-03 10:13:13 +0200 | [diff] [blame] | 880 | { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, |
| 881 | |
Marc Zyngier | 3c1e716 | 2014-12-19 16:05:31 +0000 | [diff] [blame] | 882 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 883 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, |
| 884 | { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, |
| 885 | { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, |
| 886 | { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, |
| 887 | { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, |
| 888 | { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, |
| 889 | { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, |
| 890 | { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, |
| 891 | { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, |
| 892 | { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, |
| 893 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 894 | /* |
| 895 | * DC{C,I,CI}SW operations: |
| 896 | */ |
| 897 | { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, |
| 898 | { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, |
| 899 | { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 900 | |
Marc Zyngier | 7609c12 | 2014-04-24 10:21:16 +0100 | [diff] [blame] | 901 | /* PMU */ |
| 902 | { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi }, |
| 903 | { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, |
| 904 | { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, |
| 905 | { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, |
| 906 | { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi }, |
| 907 | { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi }, |
| 908 | { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi }, |
| 909 | { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, |
| 910 | { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi }, |
| 911 | { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, |
| 912 | { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, |
| 913 | { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, |
| 914 | { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi }, |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 915 | |
| 916 | { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, |
| 917 | { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, |
| 918 | { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, |
| 919 | { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, |
Christoffer Dall | db7dedd | 2014-11-19 11:23:54 +0000 | [diff] [blame] | 920 | |
| 921 | /* ICC_SRE */ |
| 922 | { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi }, |
| 923 | |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 924 | { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, |
Marc Zyngier | a9866ba0 | 2014-04-24 14:11:48 +0100 | [diff] [blame] | 925 | }; |
| 926 | |
| 927 | static const struct sys_reg_desc cp15_64_regs[] = { |
| 928 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, |
Andre Przywara | 6d52f35 | 2014-06-03 10:13:13 +0200 | [diff] [blame] | 929 | { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, |
Marc Zyngier | 4d44923 | 2014-01-14 18:00:55 +0000 | [diff] [blame] | 930 | { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 931 | }; |
| 932 | |
| 933 | /* Target specific emulation tables */ |
| 934 | static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS]; |
| 935 | |
| 936 | void kvm_register_target_sys_reg_table(unsigned int target, |
| 937 | struct kvm_sys_reg_target_table *table) |
| 938 | { |
| 939 | target_tables[target] = table; |
| 940 | } |
| 941 | |
| 942 | /* Get specific register table for this target. */ |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 943 | static const struct sys_reg_desc *get_target_table(unsigned target, |
| 944 | bool mode_is_64, |
| 945 | size_t *num) |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 946 | { |
| 947 | struct kvm_sys_reg_target_table *table; |
| 948 | |
| 949 | table = target_tables[target]; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 950 | if (mode_is_64) { |
| 951 | *num = table->table64.num; |
| 952 | return table->table64.table; |
| 953 | } else { |
| 954 | *num = table->table32.num; |
| 955 | return table->table32.table; |
| 956 | } |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 957 | } |
| 958 | |
| 959 | static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, |
| 960 | const struct sys_reg_desc table[], |
| 961 | unsigned int num) |
| 962 | { |
| 963 | unsigned int i; |
| 964 | |
| 965 | for (i = 0; i < num; i++) { |
| 966 | const struct sys_reg_desc *r = &table[i]; |
| 967 | |
| 968 | if (params->Op0 != r->Op0) |
| 969 | continue; |
| 970 | if (params->Op1 != r->Op1) |
| 971 | continue; |
| 972 | if (params->CRn != r->CRn) |
| 973 | continue; |
| 974 | if (params->CRm != r->CRm) |
| 975 | continue; |
| 976 | if (params->Op2 != r->Op2) |
| 977 | continue; |
| 978 | |
| 979 | return r; |
| 980 | } |
| 981 | return NULL; |
| 982 | } |
| 983 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 984 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 985 | { |
| 986 | kvm_inject_undefined(vcpu); |
| 987 | return 1; |
| 988 | } |
| 989 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 990 | /* |
| 991 | * emulate_cp -- tries to match a sys_reg access in a handling table, and |
| 992 | * call the corresponding trap handler. |
| 993 | * |
| 994 | * @params: pointer to the descriptor of the access |
| 995 | * @table: array of trap descriptors |
| 996 | * @num: size of the trap descriptor array |
| 997 | * |
| 998 | * Return 0 if the access has been handled, and -1 if not. |
| 999 | */ |
| 1000 | static int emulate_cp(struct kvm_vcpu *vcpu, |
| 1001 | const struct sys_reg_params *params, |
| 1002 | const struct sys_reg_desc *table, |
| 1003 | size_t num) |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1004 | { |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1005 | const struct sys_reg_desc *r; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1006 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1007 | if (!table) |
| 1008 | return -1; /* Not handled */ |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1009 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1010 | r = find_reg(params, table, num); |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1011 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1012 | if (r) { |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1013 | /* |
| 1014 | * Not having an accessor means that we have |
| 1015 | * configured a trap that we don't know how to |
| 1016 | * handle. This certainly qualifies as a gross bug |
| 1017 | * that should be fixed right away. |
| 1018 | */ |
| 1019 | BUG_ON(!r->access); |
| 1020 | |
| 1021 | if (likely(r->access(vcpu, params, r))) { |
| 1022 | /* Skip instruction, since it was emulated */ |
| 1023 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1024 | } |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1025 | |
| 1026 | /* Handled */ |
| 1027 | return 0; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1030 | /* Not handled */ |
| 1031 | return -1; |
| 1032 | } |
| 1033 | |
| 1034 | static void unhandled_cp_access(struct kvm_vcpu *vcpu, |
| 1035 | struct sys_reg_params *params) |
| 1036 | { |
| 1037 | u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu); |
| 1038 | int cp; |
| 1039 | |
| 1040 | switch(hsr_ec) { |
Mark Rutland | c6d01a9 | 2014-11-24 13:59:30 +0000 | [diff] [blame] | 1041 | case ESR_ELx_EC_CP15_32: |
| 1042 | case ESR_ELx_EC_CP15_64: |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1043 | cp = 15; |
| 1044 | break; |
Mark Rutland | c6d01a9 | 2014-11-24 13:59:30 +0000 | [diff] [blame] | 1045 | case ESR_ELx_EC_CP14_MR: |
| 1046 | case ESR_ELx_EC_CP14_64: |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1047 | cp = 14; |
| 1048 | break; |
| 1049 | default: |
| 1050 | WARN_ON((cp = -1)); |
| 1051 | } |
| 1052 | |
| 1053 | kvm_err("Unsupported guest CP%d access at: %08lx\n", |
| 1054 | cp, *vcpu_pc(vcpu)); |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1055 | print_sys_reg_instr(params); |
| 1056 | kvm_inject_undefined(vcpu); |
| 1057 | } |
| 1058 | |
| 1059 | /** |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1060 | * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1061 | * @vcpu: The VCPU pointer |
| 1062 | * @run: The kvm_run struct |
| 1063 | */ |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1064 | static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, |
| 1065 | const struct sys_reg_desc *global, |
| 1066 | size_t nr_global, |
| 1067 | const struct sys_reg_desc *target_specific, |
| 1068 | size_t nr_specific) |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1069 | { |
| 1070 | struct sys_reg_params params; |
| 1071 | u32 hsr = kvm_vcpu_get_hsr(vcpu); |
| 1072 | int Rt2 = (hsr >> 10) & 0xf; |
| 1073 | |
Marc Zyngier | 2072d29 | 2014-01-21 10:55:17 +0000 | [diff] [blame] | 1074 | params.is_aarch32 = true; |
| 1075 | params.is_32bit = false; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1076 | params.CRm = (hsr >> 1) & 0xf; |
| 1077 | params.Rt = (hsr >> 5) & 0xf; |
| 1078 | params.is_write = ((hsr & 1) == 0); |
| 1079 | |
| 1080 | params.Op0 = 0; |
| 1081 | params.Op1 = (hsr >> 16) & 0xf; |
| 1082 | params.Op2 = 0; |
| 1083 | params.CRn = 0; |
| 1084 | |
| 1085 | /* |
| 1086 | * Massive hack here. Store Rt2 in the top 32bits so we only |
| 1087 | * have one register to deal with. As we use the same trap |
| 1088 | * backends between AArch32 and AArch64, we get away with it. |
| 1089 | */ |
| 1090 | if (params.is_write) { |
| 1091 | u64 val = *vcpu_reg(vcpu, params.Rt); |
| 1092 | val &= 0xffffffff; |
| 1093 | val |= *vcpu_reg(vcpu, Rt2) << 32; |
| 1094 | *vcpu_reg(vcpu, params.Rt) = val; |
| 1095 | } |
| 1096 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1097 | if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific)) |
| 1098 | goto out; |
| 1099 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) |
| 1100 | goto out; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1101 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1102 | unhandled_cp_access(vcpu, ¶ms); |
| 1103 | |
| 1104 | out: |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1105 | /* Do the opposite hack for the read side */ |
| 1106 | if (!params.is_write) { |
| 1107 | u64 val = *vcpu_reg(vcpu, params.Rt); |
| 1108 | val >>= 32; |
| 1109 | *vcpu_reg(vcpu, Rt2) = val; |
| 1110 | } |
| 1111 | |
| 1112 | return 1; |
| 1113 | } |
| 1114 | |
| 1115 | /** |
| 1116 | * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access |
| 1117 | * @vcpu: The VCPU pointer |
| 1118 | * @run: The kvm_run struct |
| 1119 | */ |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1120 | static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, |
| 1121 | const struct sys_reg_desc *global, |
| 1122 | size_t nr_global, |
| 1123 | const struct sys_reg_desc *target_specific, |
| 1124 | size_t nr_specific) |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1125 | { |
| 1126 | struct sys_reg_params params; |
| 1127 | u32 hsr = kvm_vcpu_get_hsr(vcpu); |
| 1128 | |
Marc Zyngier | 2072d29 | 2014-01-21 10:55:17 +0000 | [diff] [blame] | 1129 | params.is_aarch32 = true; |
| 1130 | params.is_32bit = true; |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1131 | params.CRm = (hsr >> 1) & 0xf; |
| 1132 | params.Rt = (hsr >> 5) & 0xf; |
| 1133 | params.is_write = ((hsr & 1) == 0); |
| 1134 | params.CRn = (hsr >> 10) & 0xf; |
| 1135 | params.Op0 = 0; |
| 1136 | params.Op1 = (hsr >> 14) & 0x7; |
| 1137 | params.Op2 = (hsr >> 17) & 0x7; |
| 1138 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1139 | if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific)) |
| 1140 | return 1; |
| 1141 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) |
| 1142 | return 1; |
| 1143 | |
| 1144 | unhandled_cp_access(vcpu, ¶ms); |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1145 | return 1; |
| 1146 | } |
| 1147 | |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1148 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 1149 | { |
| 1150 | const struct sys_reg_desc *target_specific; |
| 1151 | size_t num; |
| 1152 | |
| 1153 | target_specific = get_target_table(vcpu->arch.target, false, &num); |
| 1154 | return kvm_handle_cp_64(vcpu, |
Marc Zyngier | a9866ba0 | 2014-04-24 14:11:48 +0100 | [diff] [blame] | 1155 | cp15_64_regs, ARRAY_SIZE(cp15_64_regs), |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1156 | target_specific, num); |
| 1157 | } |
| 1158 | |
| 1159 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 1160 | { |
| 1161 | const struct sys_reg_desc *target_specific; |
| 1162 | size_t num; |
| 1163 | |
| 1164 | target_specific = get_target_table(vcpu->arch.target, false, &num); |
| 1165 | return kvm_handle_cp_32(vcpu, |
| 1166 | cp15_regs, ARRAY_SIZE(cp15_regs), |
| 1167 | target_specific, num); |
| 1168 | } |
| 1169 | |
| 1170 | int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 1171 | { |
| 1172 | return kvm_handle_cp_64(vcpu, |
Marc Zyngier | a9866ba0 | 2014-04-24 14:11:48 +0100 | [diff] [blame] | 1173 | cp14_64_regs, ARRAY_SIZE(cp14_64_regs), |
Marc Zyngier | 7256401 | 2014-04-24 10:27:13 +0100 | [diff] [blame] | 1174 | NULL, 0); |
| 1175 | } |
| 1176 | |
| 1177 | int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 1178 | { |
| 1179 | return kvm_handle_cp_32(vcpu, |
| 1180 | cp14_regs, ARRAY_SIZE(cp14_regs), |
| 1181 | NULL, 0); |
| 1182 | } |
| 1183 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1184 | static int emulate_sys_reg(struct kvm_vcpu *vcpu, |
| 1185 | const struct sys_reg_params *params) |
| 1186 | { |
| 1187 | size_t num; |
| 1188 | const struct sys_reg_desc *table, *r; |
| 1189 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1190 | table = get_target_table(vcpu->arch.target, true, &num); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1191 | |
| 1192 | /* Search target-specific then generic table. */ |
| 1193 | r = find_reg(params, table, num); |
| 1194 | if (!r) |
| 1195 | r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
| 1196 | |
| 1197 | if (likely(r)) { |
| 1198 | /* |
| 1199 | * Not having an accessor means that we have |
| 1200 | * configured a trap that we don't know how to |
| 1201 | * handle. This certainly qualifies as a gross bug |
| 1202 | * that should be fixed right away. |
| 1203 | */ |
| 1204 | BUG_ON(!r->access); |
| 1205 | |
| 1206 | if (likely(r->access(vcpu, params, r))) { |
| 1207 | /* Skip instruction, since it was emulated */ |
| 1208 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); |
| 1209 | return 1; |
| 1210 | } |
| 1211 | /* If access function fails, it should complain. */ |
| 1212 | } else { |
| 1213 | kvm_err("Unsupported guest sys_reg access at: %lx\n", |
| 1214 | *vcpu_pc(vcpu)); |
| 1215 | print_sys_reg_instr(params); |
| 1216 | } |
| 1217 | kvm_inject_undefined(vcpu); |
| 1218 | return 1; |
| 1219 | } |
| 1220 | |
| 1221 | static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, |
| 1222 | const struct sys_reg_desc *table, size_t num) |
| 1223 | { |
| 1224 | unsigned long i; |
| 1225 | |
| 1226 | for (i = 0; i < num; i++) |
| 1227 | if (table[i].reset) |
| 1228 | table[i].reset(vcpu, &table[i]); |
| 1229 | } |
| 1230 | |
| 1231 | /** |
| 1232 | * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access |
| 1233 | * @vcpu: The VCPU pointer |
| 1234 | * @run: The kvm_run struct |
| 1235 | */ |
| 1236 | int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) |
| 1237 | { |
| 1238 | struct sys_reg_params params; |
| 1239 | unsigned long esr = kvm_vcpu_get_hsr(vcpu); |
| 1240 | |
Alex Bennée | eef8c85 | 2015-07-07 17:30:03 +0100 | [diff] [blame] | 1241 | trace_kvm_handle_sys_reg(esr); |
| 1242 | |
Marc Zyngier | 2072d29 | 2014-01-21 10:55:17 +0000 | [diff] [blame] | 1243 | params.is_aarch32 = false; |
| 1244 | params.is_32bit = false; |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1245 | params.Op0 = (esr >> 20) & 3; |
| 1246 | params.Op1 = (esr >> 14) & 0x7; |
| 1247 | params.CRn = (esr >> 10) & 0xf; |
| 1248 | params.CRm = (esr >> 1) & 0xf; |
| 1249 | params.Op2 = (esr >> 17) & 0x7; |
| 1250 | params.Rt = (esr >> 5) & 0x1f; |
| 1251 | params.is_write = !(esr & 1); |
| 1252 | |
| 1253 | return emulate_sys_reg(vcpu, ¶ms); |
| 1254 | } |
| 1255 | |
| 1256 | /****************************************************************************** |
| 1257 | * Userspace API |
| 1258 | *****************************************************************************/ |
| 1259 | |
| 1260 | static bool index_to_params(u64 id, struct sys_reg_params *params) |
| 1261 | { |
| 1262 | switch (id & KVM_REG_SIZE_MASK) { |
| 1263 | case KVM_REG_SIZE_U64: |
| 1264 | /* Any unused index bits means it's not valid. */ |
| 1265 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK |
| 1266 | | KVM_REG_ARM_COPROC_MASK |
| 1267 | | KVM_REG_ARM64_SYSREG_OP0_MASK |
| 1268 | | KVM_REG_ARM64_SYSREG_OP1_MASK |
| 1269 | | KVM_REG_ARM64_SYSREG_CRN_MASK |
| 1270 | | KVM_REG_ARM64_SYSREG_CRM_MASK |
| 1271 | | KVM_REG_ARM64_SYSREG_OP2_MASK)) |
| 1272 | return false; |
| 1273 | params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) |
| 1274 | >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); |
| 1275 | params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) |
| 1276 | >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); |
| 1277 | params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) |
| 1278 | >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); |
| 1279 | params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) |
| 1280 | >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); |
| 1281 | params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) |
| 1282 | >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); |
| 1283 | return true; |
| 1284 | default: |
| 1285 | return false; |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | /* Decode an index value, and find the sys_reg_desc entry. */ |
| 1290 | static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, |
| 1291 | u64 id) |
| 1292 | { |
| 1293 | size_t num; |
| 1294 | const struct sys_reg_desc *table, *r; |
| 1295 | struct sys_reg_params params; |
| 1296 | |
| 1297 | /* We only do sys_reg for now. */ |
| 1298 | if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) |
| 1299 | return NULL; |
| 1300 | |
| 1301 | if (!index_to_params(id, ¶ms)) |
| 1302 | return NULL; |
| 1303 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1304 | table = get_target_table(vcpu->arch.target, true, &num); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1305 | r = find_reg(¶ms, table, num); |
| 1306 | if (!r) |
| 1307 | r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
| 1308 | |
| 1309 | /* Not saved in the sys_reg array? */ |
| 1310 | if (r && !r->reg) |
| 1311 | r = NULL; |
| 1312 | |
| 1313 | return r; |
| 1314 | } |
| 1315 | |
| 1316 | /* |
| 1317 | * These are the invariant sys_reg registers: we let the guest see the |
| 1318 | * host versions of these, so they're part of the guest state. |
| 1319 | * |
| 1320 | * A future CPU may provide a mechanism to present different values to |
| 1321 | * the guest, or a future kvm may trap them. |
| 1322 | */ |
| 1323 | |
| 1324 | #define FUNCTION_INVARIANT(reg) \ |
| 1325 | static void get_##reg(struct kvm_vcpu *v, \ |
| 1326 | const struct sys_reg_desc *r) \ |
| 1327 | { \ |
| 1328 | u64 val; \ |
| 1329 | \ |
| 1330 | asm volatile("mrs %0, " __stringify(reg) "\n" \ |
| 1331 | : "=r" (val)); \ |
| 1332 | ((struct sys_reg_desc *)r)->val = val; \ |
| 1333 | } |
| 1334 | |
| 1335 | FUNCTION_INVARIANT(midr_el1) |
| 1336 | FUNCTION_INVARIANT(ctr_el0) |
| 1337 | FUNCTION_INVARIANT(revidr_el1) |
| 1338 | FUNCTION_INVARIANT(id_pfr0_el1) |
| 1339 | FUNCTION_INVARIANT(id_pfr1_el1) |
| 1340 | FUNCTION_INVARIANT(id_dfr0_el1) |
| 1341 | FUNCTION_INVARIANT(id_afr0_el1) |
| 1342 | FUNCTION_INVARIANT(id_mmfr0_el1) |
| 1343 | FUNCTION_INVARIANT(id_mmfr1_el1) |
| 1344 | FUNCTION_INVARIANT(id_mmfr2_el1) |
| 1345 | FUNCTION_INVARIANT(id_mmfr3_el1) |
| 1346 | FUNCTION_INVARIANT(id_isar0_el1) |
| 1347 | FUNCTION_INVARIANT(id_isar1_el1) |
| 1348 | FUNCTION_INVARIANT(id_isar2_el1) |
| 1349 | FUNCTION_INVARIANT(id_isar3_el1) |
| 1350 | FUNCTION_INVARIANT(id_isar4_el1) |
| 1351 | FUNCTION_INVARIANT(id_isar5_el1) |
| 1352 | FUNCTION_INVARIANT(clidr_el1) |
| 1353 | FUNCTION_INVARIANT(aidr_el1) |
| 1354 | |
| 1355 | /* ->val is filled in by kvm_sys_reg_table_init() */ |
| 1356 | static struct sys_reg_desc invariant_sys_regs[] = { |
| 1357 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000), |
| 1358 | NULL, get_midr_el1 }, |
| 1359 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110), |
| 1360 | NULL, get_revidr_el1 }, |
| 1361 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000), |
| 1362 | NULL, get_id_pfr0_el1 }, |
| 1363 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001), |
| 1364 | NULL, get_id_pfr1_el1 }, |
| 1365 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010), |
| 1366 | NULL, get_id_dfr0_el1 }, |
| 1367 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011), |
| 1368 | NULL, get_id_afr0_el1 }, |
| 1369 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100), |
| 1370 | NULL, get_id_mmfr0_el1 }, |
| 1371 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101), |
| 1372 | NULL, get_id_mmfr1_el1 }, |
| 1373 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110), |
| 1374 | NULL, get_id_mmfr2_el1 }, |
| 1375 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111), |
| 1376 | NULL, get_id_mmfr3_el1 }, |
| 1377 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000), |
| 1378 | NULL, get_id_isar0_el1 }, |
| 1379 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001), |
| 1380 | NULL, get_id_isar1_el1 }, |
| 1381 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010), |
| 1382 | NULL, get_id_isar2_el1 }, |
| 1383 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011), |
| 1384 | NULL, get_id_isar3_el1 }, |
| 1385 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100), |
| 1386 | NULL, get_id_isar4_el1 }, |
| 1387 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101), |
| 1388 | NULL, get_id_isar5_el1 }, |
| 1389 | { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001), |
| 1390 | NULL, get_clidr_el1 }, |
| 1391 | { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111), |
| 1392 | NULL, get_aidr_el1 }, |
| 1393 | { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001), |
| 1394 | NULL, get_ctr_el0 }, |
| 1395 | }; |
| 1396 | |
Victor Kamensky | 26c99af | 2014-06-12 09:30:12 -0700 | [diff] [blame] | 1397 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1398 | { |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1399 | if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) |
| 1400 | return -EFAULT; |
| 1401 | return 0; |
| 1402 | } |
| 1403 | |
Victor Kamensky | 26c99af | 2014-06-12 09:30:12 -0700 | [diff] [blame] | 1404 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1405 | { |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1406 | if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) |
| 1407 | return -EFAULT; |
| 1408 | return 0; |
| 1409 | } |
| 1410 | |
| 1411 | static int get_invariant_sys_reg(u64 id, void __user *uaddr) |
| 1412 | { |
| 1413 | struct sys_reg_params params; |
| 1414 | const struct sys_reg_desc *r; |
| 1415 | |
| 1416 | if (!index_to_params(id, ¶ms)) |
| 1417 | return -ENOENT; |
| 1418 | |
| 1419 | r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)); |
| 1420 | if (!r) |
| 1421 | return -ENOENT; |
| 1422 | |
| 1423 | return reg_to_user(uaddr, &r->val, id); |
| 1424 | } |
| 1425 | |
| 1426 | static int set_invariant_sys_reg(u64 id, void __user *uaddr) |
| 1427 | { |
| 1428 | struct sys_reg_params params; |
| 1429 | const struct sys_reg_desc *r; |
| 1430 | int err; |
| 1431 | u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ |
| 1432 | |
| 1433 | if (!index_to_params(id, ¶ms)) |
| 1434 | return -ENOENT; |
| 1435 | r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)); |
| 1436 | if (!r) |
| 1437 | return -ENOENT; |
| 1438 | |
| 1439 | err = reg_from_user(&val, uaddr, id); |
| 1440 | if (err) |
| 1441 | return err; |
| 1442 | |
| 1443 | /* This is what we mean by invariant: you can't change it. */ |
| 1444 | if (r->val != val) |
| 1445 | return -EINVAL; |
| 1446 | |
| 1447 | return 0; |
| 1448 | } |
| 1449 | |
| 1450 | static bool is_valid_cache(u32 val) |
| 1451 | { |
| 1452 | u32 level, ctype; |
| 1453 | |
| 1454 | if (val >= CSSELR_MAX) |
Will Deacon | 18d4576 | 2014-08-26 15:13:22 +0100 | [diff] [blame] | 1455 | return false; |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1456 | |
| 1457 | /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ |
| 1458 | level = (val >> 1); |
| 1459 | ctype = (cache_levels >> (level * 3)) & 7; |
| 1460 | |
| 1461 | switch (ctype) { |
| 1462 | case 0: /* No cache */ |
| 1463 | return false; |
| 1464 | case 1: /* Instruction cache only */ |
| 1465 | return (val & 1); |
| 1466 | case 2: /* Data cache only */ |
| 1467 | case 4: /* Unified cache */ |
| 1468 | return !(val & 1); |
| 1469 | case 3: /* Separate instruction and data caches */ |
| 1470 | return true; |
| 1471 | default: /* Reserved: we can't know instruction or data. */ |
| 1472 | return false; |
| 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | static int demux_c15_get(u64 id, void __user *uaddr) |
| 1477 | { |
| 1478 | u32 val; |
| 1479 | u32 __user *uval = uaddr; |
| 1480 | |
| 1481 | /* Fail if we have unknown bits set. */ |
| 1482 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK |
| 1483 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) |
| 1484 | return -ENOENT; |
| 1485 | |
| 1486 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { |
| 1487 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: |
| 1488 | if (KVM_REG_SIZE(id) != 4) |
| 1489 | return -ENOENT; |
| 1490 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) |
| 1491 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; |
| 1492 | if (!is_valid_cache(val)) |
| 1493 | return -ENOENT; |
| 1494 | |
| 1495 | return put_user(get_ccsidr(val), uval); |
| 1496 | default: |
| 1497 | return -ENOENT; |
| 1498 | } |
| 1499 | } |
| 1500 | |
| 1501 | static int demux_c15_set(u64 id, void __user *uaddr) |
| 1502 | { |
| 1503 | u32 val, newval; |
| 1504 | u32 __user *uval = uaddr; |
| 1505 | |
| 1506 | /* Fail if we have unknown bits set. */ |
| 1507 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK |
| 1508 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) |
| 1509 | return -ENOENT; |
| 1510 | |
| 1511 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { |
| 1512 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: |
| 1513 | if (KVM_REG_SIZE(id) != 4) |
| 1514 | return -ENOENT; |
| 1515 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) |
| 1516 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; |
| 1517 | if (!is_valid_cache(val)) |
| 1518 | return -ENOENT; |
| 1519 | |
| 1520 | if (get_user(newval, uval)) |
| 1521 | return -EFAULT; |
| 1522 | |
| 1523 | /* This is also invariant: you can't change it. */ |
| 1524 | if (newval != get_ccsidr(val)) |
| 1525 | return -EINVAL; |
| 1526 | return 0; |
| 1527 | default: |
| 1528 | return -ENOENT; |
| 1529 | } |
| 1530 | } |
| 1531 | |
| 1532 | int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) |
| 1533 | { |
| 1534 | const struct sys_reg_desc *r; |
| 1535 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; |
| 1536 | |
| 1537 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) |
| 1538 | return demux_c15_get(reg->id, uaddr); |
| 1539 | |
| 1540 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) |
| 1541 | return -ENOENT; |
| 1542 | |
| 1543 | r = index_to_sys_reg_desc(vcpu, reg->id); |
| 1544 | if (!r) |
| 1545 | return get_invariant_sys_reg(reg->id, uaddr); |
| 1546 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 1547 | if (r->get_user) |
| 1548 | return (r->get_user)(vcpu, r, reg, uaddr); |
| 1549 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1550 | return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id); |
| 1551 | } |
| 1552 | |
| 1553 | int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) |
| 1554 | { |
| 1555 | const struct sys_reg_desc *r; |
| 1556 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; |
| 1557 | |
| 1558 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) |
| 1559 | return demux_c15_set(reg->id, uaddr); |
| 1560 | |
| 1561 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) |
| 1562 | return -ENOENT; |
| 1563 | |
| 1564 | r = index_to_sys_reg_desc(vcpu, reg->id); |
| 1565 | if (!r) |
| 1566 | return set_invariant_sys_reg(reg->id, uaddr); |
| 1567 | |
Alex Bennée | 84e690b | 2015-07-07 17:30:00 +0100 | [diff] [blame] | 1568 | if (r->set_user) |
| 1569 | return (r->set_user)(vcpu, r, reg, uaddr); |
| 1570 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1571 | return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); |
| 1572 | } |
| 1573 | |
| 1574 | static unsigned int num_demux_regs(void) |
| 1575 | { |
| 1576 | unsigned int i, count = 0; |
| 1577 | |
| 1578 | for (i = 0; i < CSSELR_MAX; i++) |
| 1579 | if (is_valid_cache(i)) |
| 1580 | count++; |
| 1581 | |
| 1582 | return count; |
| 1583 | } |
| 1584 | |
| 1585 | static int write_demux_regids(u64 __user *uindices) |
| 1586 | { |
Alex Bennée | efd48ce | 2014-07-01 16:53:13 +0100 | [diff] [blame] | 1587 | u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1588 | unsigned int i; |
| 1589 | |
| 1590 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; |
| 1591 | for (i = 0; i < CSSELR_MAX; i++) { |
| 1592 | if (!is_valid_cache(i)) |
| 1593 | continue; |
| 1594 | if (put_user(val | i, uindices)) |
| 1595 | return -EFAULT; |
| 1596 | uindices++; |
| 1597 | } |
| 1598 | return 0; |
| 1599 | } |
| 1600 | |
| 1601 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg) |
| 1602 | { |
| 1603 | return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | |
| 1604 | KVM_REG_ARM64_SYSREG | |
| 1605 | (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | |
| 1606 | (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | |
| 1607 | (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | |
| 1608 | (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | |
| 1609 | (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); |
| 1610 | } |
| 1611 | |
| 1612 | static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) |
| 1613 | { |
| 1614 | if (!*uind) |
| 1615 | return true; |
| 1616 | |
| 1617 | if (put_user(sys_reg_to_index(reg), *uind)) |
| 1618 | return false; |
| 1619 | |
| 1620 | (*uind)++; |
| 1621 | return true; |
| 1622 | } |
| 1623 | |
| 1624 | /* Assumed ordered tables, see kvm_sys_reg_table_init. */ |
| 1625 | static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) |
| 1626 | { |
| 1627 | const struct sys_reg_desc *i1, *i2, *end1, *end2; |
| 1628 | unsigned int total = 0; |
| 1629 | size_t num; |
| 1630 | |
| 1631 | /* We check for duplicates here, to allow arch-specific overrides. */ |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1632 | i1 = get_target_table(vcpu->arch.target, true, &num); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1633 | end1 = i1 + num; |
| 1634 | i2 = sys_reg_descs; |
| 1635 | end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); |
| 1636 | |
| 1637 | BUG_ON(i1 == end1 || i2 == end2); |
| 1638 | |
| 1639 | /* Walk carefully, as both tables may refer to the same register. */ |
| 1640 | while (i1 || i2) { |
| 1641 | int cmp = cmp_sys_reg(i1, i2); |
| 1642 | /* target-specific overrides generic entry. */ |
| 1643 | if (cmp <= 0) { |
| 1644 | /* Ignore registers we trap but don't save. */ |
| 1645 | if (i1->reg) { |
| 1646 | if (!copy_reg_to_user(i1, &uind)) |
| 1647 | return -EFAULT; |
| 1648 | total++; |
| 1649 | } |
| 1650 | } else { |
| 1651 | /* Ignore registers we trap but don't save. */ |
| 1652 | if (i2->reg) { |
| 1653 | if (!copy_reg_to_user(i2, &uind)) |
| 1654 | return -EFAULT; |
| 1655 | total++; |
| 1656 | } |
| 1657 | } |
| 1658 | |
| 1659 | if (cmp <= 0 && ++i1 == end1) |
| 1660 | i1 = NULL; |
| 1661 | if (cmp >= 0 && ++i2 == end2) |
| 1662 | i2 = NULL; |
| 1663 | } |
| 1664 | return total; |
| 1665 | } |
| 1666 | |
| 1667 | unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) |
| 1668 | { |
| 1669 | return ARRAY_SIZE(invariant_sys_regs) |
| 1670 | + num_demux_regs() |
| 1671 | + walk_sys_regs(vcpu, (u64 __user *)NULL); |
| 1672 | } |
| 1673 | |
| 1674 | int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) |
| 1675 | { |
| 1676 | unsigned int i; |
| 1677 | int err; |
| 1678 | |
| 1679 | /* Then give them all the invariant registers' indices. */ |
| 1680 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { |
| 1681 | if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) |
| 1682 | return -EFAULT; |
| 1683 | uindices++; |
| 1684 | } |
| 1685 | |
| 1686 | err = walk_sys_regs(vcpu, uindices); |
| 1687 | if (err < 0) |
| 1688 | return err; |
| 1689 | uindices += err; |
| 1690 | |
| 1691 | return write_demux_regids(uindices); |
| 1692 | } |
| 1693 | |
Marc Zyngier | e6a9551 | 2014-05-07 13:43:39 +0100 | [diff] [blame] | 1694 | static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n) |
| 1695 | { |
| 1696 | unsigned int i; |
| 1697 | |
| 1698 | for (i = 1; i < n; i++) { |
| 1699 | if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) { |
| 1700 | kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); |
| 1701 | return 1; |
| 1702 | } |
| 1703 | } |
| 1704 | |
| 1705 | return 0; |
| 1706 | } |
| 1707 | |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1708 | void kvm_sys_reg_table_init(void) |
| 1709 | { |
| 1710 | unsigned int i; |
| 1711 | struct sys_reg_desc clidr; |
| 1712 | |
| 1713 | /* Make sure tables are unique and in order. */ |
Marc Zyngier | e6a9551 | 2014-05-07 13:43:39 +0100 | [diff] [blame] | 1714 | BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs))); |
| 1715 | BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs))); |
| 1716 | BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs))); |
| 1717 | BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs))); |
| 1718 | BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs))); |
| 1719 | BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs))); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1720 | |
| 1721 | /* We abuse the reset function to overwrite the table itself. */ |
| 1722 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) |
| 1723 | invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); |
| 1724 | |
| 1725 | /* |
| 1726 | * CLIDR format is awkward, so clean it up. See ARM B4.1.20: |
| 1727 | * |
| 1728 | * If software reads the Cache Type fields from Ctype1 |
| 1729 | * upwards, once it has seen a value of 0b000, no caches |
| 1730 | * exist at further-out levels of the hierarchy. So, for |
| 1731 | * example, if Ctype3 is the first Cache Type field with a |
| 1732 | * value of 0b000, the values of Ctype4 to Ctype7 must be |
| 1733 | * ignored. |
| 1734 | */ |
| 1735 | get_clidr_el1(NULL, &clidr); /* Ugly... */ |
| 1736 | cache_levels = clidr.val; |
| 1737 | for (i = 0; i < 7; i++) |
| 1738 | if (((cache_levels >> (i*3)) & 7) == 0) |
| 1739 | break; |
| 1740 | /* Clear all higher bits. */ |
| 1741 | cache_levels &= (1 << (i*3))-1; |
| 1742 | } |
| 1743 | |
| 1744 | /** |
| 1745 | * kvm_reset_sys_regs - sets system registers to reset value |
| 1746 | * @vcpu: The VCPU pointer |
| 1747 | * |
| 1748 | * This function finds the right table above and sets the registers on the |
| 1749 | * virtual CPU struct to their architecturally defined reset values. |
| 1750 | */ |
| 1751 | void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) |
| 1752 | { |
| 1753 | size_t num; |
| 1754 | const struct sys_reg_desc *table; |
| 1755 | |
| 1756 | /* Catch someone adding a register without putting in reset entry. */ |
| 1757 | memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs)); |
| 1758 | |
| 1759 | /* Generic chip reset first (so target could override). */ |
| 1760 | reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
| 1761 | |
Marc Zyngier | 62a89c4 | 2013-02-07 10:32:33 +0000 | [diff] [blame] | 1762 | table = get_target_table(vcpu->arch.target, true, &num); |
Marc Zyngier | 7c8c5e6a | 2012-12-10 16:15:34 +0000 | [diff] [blame] | 1763 | reset_sys_reg_descs(vcpu, table, num); |
| 1764 | |
| 1765 | for (num = 1; num < NR_SYS_REGS; num++) |
| 1766 | if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242) |
| 1767 | panic("Didn't reset vcpu_sys_reg(%zi)", num); |
| 1768 | } |