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Max Filippovc622b292012-11-19 07:00:41 +04001We Have Atomic Operation Control (ATOMCTL) Register.
2This register determines the effect of using a S32C1I instruction
3with various combinations of:
4
5 1. With and without an Coherent Cache Controller which
6 can do Atomic Transactions to the memory internally.
7
8 2. With and without An Intelligent Memory Controller which
9 can do Atomic Transactions itself.
10
11The Core comes up with a default value of for the three types of cache ops:
12
13 0x28: (WB: Internal, WT: Internal, BY:Exception)
14
15On the FPGA Cards we typically simulate an Intelligent Memory controller
16which can implement RCW transactions. For FPGA cards with an External
17Memory controller we let it to the atomic operations internally while
18doing a Cached (WB) transaction and use the Memory RCW for un-cached
19operations.
20
21For systems without an coherent cache controller, non-MX, we always
22use the memory controllers RCW, thought non-MX controlers likely
23support the Internal Operation.
24
25CUSTOMER-WARNING:
26 Virtually all customers buy their memory controllers from vendors that
27 don't support atomic RCW memory transactions and will likely want to
28 configure this register to not use RCW.
29
30Developers might find using RCW in Bypass mode convenient when testing
31with the cache being bypassed; for example studying cache alias problems.
32
33See Section 4.3.12.4 of ISA; Bits:
34
35 WB WT BY
36 5 4 | 3 2 | 1 0
37 2 Bit
38 Field
39 Values WB - Write Back WT - Write Thru BY - Bypass
40--------- --------------- ----------------- ----------------
41 0 Exception Exception Exception
42 1 RCW Transaction RCW Transaction RCW Transaction
43 2 Internal Operation Exception Reserved
44 3 Reserved Reserved Reserved