blob: 92dedde761d183a0109dfd7173c37ec1f3a1d43b [file] [log] [blame]
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -05001#ifndef _ASM_POWERPC_TIMEX_H
2#define _ASM_POWERPC_TIMEX_H
3
4#ifdef __KERNEL__
5
6/*
7 * PowerPC architecture timex specifications
8 */
9
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050010#include <asm/cputable.h>
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100011#include <asm/reg.h>
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050012
Benjamin Herrenschmidtcbd27b82005-10-12 11:39:33 +100013#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050014
15typedef unsigned long cycles_t;
16
17static inline cycles_t get_cycles(void)
18{
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100019#ifdef __powerpc64__
20 return mftb();
21#else
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050022 cycles_t ret;
23
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050024 /*
25 * For the "cycle" counter we use the timebase lower half.
26 * Currently only used on SMP.
27 */
28
29 ret = 0;
30
31 __asm__ __volatile__(
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +100032 "97: mftb %0\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050033 "99:\n"
34 ".section __ftr_fixup,\"a\"\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +100035 ".align 2\n"
36 "98:\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050037 " .long %1\n"
38 " .long 0\n"
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +100039 " .long 97b-98b\n"
40 " .long 99b-98b\n"
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050041 ".previous"
42 : "=r" (ret) : "i" (CPU_FTR_601));
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050043 return ret;
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +100044#endif
jdl@freescale.comdd56fdf2005-09-07 15:59:48 -050045}
46
47#endif /* __KERNEL__ */
48#endif /* _ASM_POWERPC_TIMEX_H */