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gerrit-public.fairphone.software / kernel / msm-4.9 / c6b9ef5779c3e1edfa9de949d2a51252bc347663 / . / drivers / scsi / pm8001 / pm80xx_hwi.c
blob: f0dbe79b049cc5c9ecc46b2e0ed955832faf87de [file] [log] [blame]
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48/**
49 * read_main_config_table - read the configure table and save it.
50 * @pm8001_ha: our hba card information
51 */
52static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53{
54 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
55
56 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
57 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
58 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
59 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
60 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
61 pm8001_mr32(address, MAIN_FW_REVISION);
62 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
63 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
64 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
65 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
67 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
68 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
69 pm8001_mr32(address, MAIN_GST_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
71 pm8001_mr32(address, MAIN_IBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
73 pm8001_mr32(address, MAIN_OBQ_OFFSET);
74
75 /* read Error Dump Offset and Length */
76 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
78 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
80 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
84
85 /* read GPIO LED settings from the configuration table */
86 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
87 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
88
89 /* read analog Setting offset from the configuration table */
90 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
91 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
92
93 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
94 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
95 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
96 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
97}
98
99/**
100 * read_general_status_table - read the general status table and save it.
101 * @pm8001_ha: our hba card information
102 */
103static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
104{
105 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
106 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
107 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
108 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
109 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
110 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
111 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
112 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
113 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
114 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
115 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
116 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
117 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
118 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
119 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
120 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
121 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
122 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
123 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
124 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
125 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
126 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
127 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
128 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
129 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
130 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
131 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
132 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
133 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
134}
135/**
136 * read_phy_attr_table - read the phy attribute table and save it.
137 * @pm8001_ha: our hba card information
138 */
139static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
140{
141 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
142 pm8001_ha->phy_attr_table.phystart1_16[0] =
143 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
144 pm8001_ha->phy_attr_table.phystart1_16[1] =
145 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
146 pm8001_ha->phy_attr_table.phystart1_16[2] =
147 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
148 pm8001_ha->phy_attr_table.phystart1_16[3] =
149 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
150 pm8001_ha->phy_attr_table.phystart1_16[4] =
151 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
152 pm8001_ha->phy_attr_table.phystart1_16[5] =
153 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
154 pm8001_ha->phy_attr_table.phystart1_16[6] =
155 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
156 pm8001_ha->phy_attr_table.phystart1_16[7] =
157 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
158 pm8001_ha->phy_attr_table.phystart1_16[8] =
159 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
160 pm8001_ha->phy_attr_table.phystart1_16[9] =
161 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
162 pm8001_ha->phy_attr_table.phystart1_16[10] =
163 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
164 pm8001_ha->phy_attr_table.phystart1_16[11] =
165 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
166 pm8001_ha->phy_attr_table.phystart1_16[12] =
167 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
168 pm8001_ha->phy_attr_table.phystart1_16[13] =
169 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
170 pm8001_ha->phy_attr_table.phystart1_16[14] =
171 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
172 pm8001_ha->phy_attr_table.phystart1_16[15] =
173 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
174
175 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
176 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
177 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
178 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
179 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
180 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
181 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
182 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
183 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
184 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
185 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
186 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
187 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
188 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
189 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
190 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
191 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
192 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
193 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
194 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
195 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
196 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
197 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
198 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
199 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
200 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
201 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
202 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
203 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
204 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
205 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
206 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
207
208}
209
210/**
211 * read_inbnd_queue_table - read the inbound queue table and save it.
212 * @pm8001_ha: our hba card information
213 */
214static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
215{
216 int i;
217 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
218 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
219 u32 offset = i * 0x20;
220 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
221 get_pci_bar_index(pm8001_mr32(address,
222 (offset + IB_PIPCI_BAR)));
223 pm8001_ha->inbnd_q_tbl[i].pi_offset =
224 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
225 }
226}
227
228/**
229 * read_outbnd_queue_table - read the outbound queue table and save it.
230 * @pm8001_ha: our hba card information
231 */
232static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
233{
234 int i;
235 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
236 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
237 u32 offset = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(address,
240 (offset + OB_CIPCI_BAR)));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
243 }
244}
245
246/**
247 * init_default_table_values - init the default table.
248 * @pm8001_ha: our hba card information
249 */
250static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
251{
252 int i;
253 u32 offsetib, offsetob;
254 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
255 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
256
257 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
258 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
259 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
260 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
261 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
262 PM8001_EVENT_LOG_SIZE;
263 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
264 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
265 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
266 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
267 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
268 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
269 PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
272
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]273 /* Disable end to end CRC checking */
274 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
275
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]276 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
277 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
278 PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
279 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
280 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
281 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
282 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
283 pm8001_ha->inbnd_q_tbl[i].base_virt =
284 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
285 pm8001_ha->inbnd_q_tbl[i].total_length =
286 pm8001_ha->memoryMap.region[IB + i].total_len;
287 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
288 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
289 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
290 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
291 pm8001_ha->inbnd_q_tbl[i].ci_virt =
292 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
293 offsetib = i * 0x20;
294 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
295 get_pci_bar_index(pm8001_mr32(addressib,
296 (offsetib + 0x14)));
297 pm8001_ha->inbnd_q_tbl[i].pi_offset =
298 pm8001_mr32(addressib, (offsetib + 0x18));
299 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
300 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
301 }
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
304 PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
305 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
306 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
307 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
308 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
309 pm8001_ha->outbnd_q_tbl[i].base_virt =
310 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
311 pm8001_ha->outbnd_q_tbl[i].total_length =
312 pm8001_ha->memoryMap.region[OB + i].total_len;
313 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
314 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
315 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
316 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
317 /* interrupt vector based on oq */
318 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
319 pm8001_ha->outbnd_q_tbl[i].pi_virt =
320 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
321 offsetob = i * 0x24;
322 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
323 get_pci_bar_index(pm8001_mr32(addressob,
324 offsetob + 0x14));
325 pm8001_ha->outbnd_q_tbl[i].ci_offset =
326 pm8001_mr32(addressob, (offsetob + 0x18));
327 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
328 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
329 }
330}
331
332/**
333 * update_main_config_table - update the main default table to the HBA.
334 * @pm8001_ha: our hba card information
335 */
336static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
337{
338 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
339 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
340 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
341 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
342 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
343 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
344 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
345 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
346 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
347 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
348 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
349 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
350 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
351 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
352 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
353 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
354 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
355 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
356 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
357 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
358 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]359 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
360 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]361
362 /* SPCv specific */
363 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
364 /* Set GPIOLED to 0x2 for LED indicator */
365 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
366 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
367 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
368
369 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
370 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
371 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
372 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
373}
374
375/**
376 * update_inbnd_queue_table - update the inbound queue table to the HBA.
377 * @pm8001_ha: our hba card information
378 */
379static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
380 int number)
381{
382 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
383 u16 offset = number * 0x20;
384 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
385 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
386 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
387 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
388 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
389 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
390 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
391 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
392 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
393 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
394}
395
396/**
397 * update_outbnd_queue_table - update the outbound queue table to the HBA.
398 * @pm8001_ha: our hba card information
399 */
400static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
401 int number)
402{
403 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
404 u16 offset = number * 0x24;
405 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
406 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
407 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
408 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
409 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
410 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
411 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
412 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
413 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
414 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
415 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
416 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
417}
418
419/**
420 * mpi_init_check - check firmware initialization status.
421 * @pm8001_ha: our hba card information
422 */
423static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
424{
425 u32 max_wait_count;
426 u32 value;
427 u32 gst_len_mpistate;
428
429 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
430 table is updated */
431 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
432 /* wait until Inbound DoorBell Clear Register toggled */
433 max_wait_count = 2 * 1000 * 1000;/* 2 sec for spcv/ve */
434 do {
435 udelay(1);
436 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
437 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
438 } while ((value != 0) && (--max_wait_count));
439
440 if (!max_wait_count)
441 return -1;
442 /* check the MPI-State for initialization upto 100ms*/
443 max_wait_count = 100 * 1000;/* 100 msec */
444 do {
445 udelay(1);
446 gst_len_mpistate =
447 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
448 GST_GSTLEN_MPIS_OFFSET);
449 } while ((GST_MPI_STATE_INIT !=
450 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
451 if (!max_wait_count)
452 return -1;
453
454 /* check MPI Initialization error */
455 gst_len_mpistate = gst_len_mpistate >> 16;
456 if (0x0000 != gst_len_mpistate)
457 return -1;
458
459 return 0;
460}
461
462/**
463 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
464 * @pm8001_ha: our hba card information
465 */
466static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
467{
468 u32 value;
469 u32 max_wait_count;
470 u32 max_wait_time;
471 int ret = 0;
472
473 /* reset / PCIe ready */
474 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
475 do {
476 udelay(1);
477 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
478 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
479
480 /* check ila status */
481 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
482 do {
483 udelay(1);
484 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
485 } while (((value & SCRATCH_PAD_ILA_READY) !=
486 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
487 if (!max_wait_count)
488 ret = -1;
489 else {
490 PM8001_MSG_DBG(pm8001_ha,
491 pm8001_printk(" ila ready status in %d millisec\n",
492 (max_wait_time - max_wait_count)));
493 }
494
495 /* check RAAE status */
496 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
497 do {
498 udelay(1);
499 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
500 } while (((value & SCRATCH_PAD_RAAE_READY) !=
501 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
502 if (!max_wait_count)
503 ret = -1;
504 else {
505 PM8001_MSG_DBG(pm8001_ha,
506 pm8001_printk(" raae ready status in %d millisec\n",
507 (max_wait_time - max_wait_count)));
508 }
509
510 /* check iop0 status */
511 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
512 do {
513 udelay(1);
514 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
515 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
516 (--max_wait_count));
517 if (!max_wait_count)
518 ret = -1;
519 else {
520 PM8001_MSG_DBG(pm8001_ha,
521 pm8001_printk(" iop0 ready status in %d millisec\n",
522 (max_wait_time - max_wait_count)));
523 }
524
525 /* check iop1 status only for 16 port controllers */
526 if ((pm8001_ha->chip_id != chip_8008) &&
527 (pm8001_ha->chip_id != chip_8009)) {
528 /* 200 milli sec */
529 max_wait_time = max_wait_count = 200 * 1000;
530 do {
531 udelay(1);
532 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
533 } while (((value & SCRATCH_PAD_IOP1_READY) !=
534 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
535 if (!max_wait_count)
536 ret = -1;
537 else {
538 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
539 "iop1 ready status in %d millisec\n",
540 (max_wait_time - max_wait_count)));
541 }
542 }
543
544 return ret;
545}
546
547static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
548{
549 void __iomem *base_addr;
550 u32 value;
551 u32 offset;
552 u32 pcibar;
553 u32 pcilogic;
554
555 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
556 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
557
558 PM8001_INIT_DBG(pm8001_ha,
559 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
560 offset, value));
561 pcilogic = (value & 0xFC000000) >> 26;
562 pcibar = get_pci_bar_index(pcilogic);
563 PM8001_INIT_DBG(pm8001_ha,
564 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
565 pm8001_ha->main_cfg_tbl_addr = base_addr =
566 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
567 pm8001_ha->general_stat_tbl_addr =
568 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
569 0xFFFFFF);
570 pm8001_ha->inbnd_q_tbl_addr =
571 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
572 0xFFFFFF);
573 pm8001_ha->outbnd_q_tbl_addr =
574 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
575 0xFFFFFF);
576 pm8001_ha->ivt_tbl_addr =
577 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
578 0xFFFFFF);
579 pm8001_ha->pspa_q_tbl_addr =
580 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
581 0xFFFFFF);
582
583 PM8001_INIT_DBG(pm8001_ha,
584 pm8001_printk("GST OFFSET 0x%x\n",
585 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
586 PM8001_INIT_DBG(pm8001_ha,
587 pm8001_printk("INBND OFFSET 0x%x\n",
588 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
589 PM8001_INIT_DBG(pm8001_ha,
590 pm8001_printk("OBND OFFSET 0x%x\n",
591 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
592 PM8001_INIT_DBG(pm8001_ha,
593 pm8001_printk("IVT OFFSET 0x%x\n",
594 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
595 PM8001_INIT_DBG(pm8001_ha,
596 pm8001_printk("PSPA OFFSET 0x%x\n",
597 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
598 PM8001_INIT_DBG(pm8001_ha,
599 pm8001_printk("addr - main cfg %p general status %p\n",
600 pm8001_ha->main_cfg_tbl_addr,
601 pm8001_ha->general_stat_tbl_addr));
602 PM8001_INIT_DBG(pm8001_ha,
603 pm8001_printk("addr - inbnd %p obnd %p\n",
604 pm8001_ha->inbnd_q_tbl_addr,
605 pm8001_ha->outbnd_q_tbl_addr));
606 PM8001_INIT_DBG(pm8001_ha,
607 pm8001_printk("addr - pspa %p ivt %p\n",
608 pm8001_ha->pspa_q_tbl_addr,
609 pm8001_ha->ivt_tbl_addr));
610}
611
612/**
613 * pm80xx_set_thermal_config - support the thermal configuration
614 * @pm8001_ha: our hba card information.
615 */
616static int
617pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
618{
619 struct set_ctrl_cfg_req payload;
620 struct inbound_queue_table *circularQ;
621 int rc;
622 u32 tag;
623 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
624
625 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
626 rc = pm8001_tag_alloc(pm8001_ha, &tag);
627 if (rc)
628 return -1;
629
630 circularQ = &pm8001_ha->inbnd_q_tbl[0];
631 payload.tag = cpu_to_le32(tag);
632 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
633 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
634 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
635
636 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
637 return rc;
638
639}
640
641/**
642 * pm80xx_get_encrypt_info - Check for encryption
643 * @pm8001_ha: our hba card information.
644 */
645static int
646pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
647{
648 u32 scratch3_value;
649 int ret;
650
651 /* Read encryption status from SCRATCH PAD 3 */
652 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
653
654 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
655 SCRATCH_PAD3_ENC_READY) {
656 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
657 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
658 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
659 SCRATCH_PAD3_SMF_ENABLED)
660 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
661 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
662 SCRATCH_PAD3_SMA_ENABLED)
663 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
664 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
665 SCRATCH_PAD3_SMB_ENABLED)
666 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
667 pm8001_ha->encrypt_info.status = 0;
668 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
669 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
670 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
671 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
672 pm8001_ha->encrypt_info.sec_mode,
673 pm8001_ha->encrypt_info.status));
674 ret = 0;
675 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
676 SCRATCH_PAD3_ENC_DISABLED) {
677 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
678 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
679 scratch3_value));
680 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
681 pm8001_ha->encrypt_info.cipher_mode = 0;
682 pm8001_ha->encrypt_info.sec_mode = 0;
683 return 0;
684 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
685 SCRATCH_PAD3_ENC_DIS_ERR) {
686 pm8001_ha->encrypt_info.status =
687 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
688 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
689 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
690 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
691 SCRATCH_PAD3_SMF_ENABLED)
692 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
693 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
694 SCRATCH_PAD3_SMA_ENABLED)
695 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
696 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
697 SCRATCH_PAD3_SMB_ENABLED)
698 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
699 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
700 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
701 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
702 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
703 pm8001_ha->encrypt_info.sec_mode,
704 pm8001_ha->encrypt_info.status));
705 ret = -1;
706 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
707 SCRATCH_PAD3_ENC_ENA_ERR) {
708
709 pm8001_ha->encrypt_info.status =
710 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
711 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
712 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
713 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
714 SCRATCH_PAD3_SMF_ENABLED)
715 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
716 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
717 SCRATCH_PAD3_SMA_ENABLED)
718 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
719 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
720 SCRATCH_PAD3_SMB_ENABLED)
721 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
722
723 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
724 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
725 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
726 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
727 pm8001_ha->encrypt_info.sec_mode,
728 pm8001_ha->encrypt_info.status));
729 ret = -1;
730 }
731 return ret;
732}
733
734/**
735 * pm80xx_encrypt_update - update flash with encryption informtion
736 * @pm8001_ha: our hba card information.
737 */
738static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
739{
740 struct kek_mgmt_req payload;
741 struct inbound_queue_table *circularQ;
742 int rc;
743 u32 tag;
744 u32 opc = OPC_INB_KEK_MANAGEMENT;
745
746 memset(&payload, 0, sizeof(struct kek_mgmt_req));
747 rc = pm8001_tag_alloc(pm8001_ha, &tag);
748 if (rc)
749 return -1;
750
751 circularQ = &pm8001_ha->inbnd_q_tbl[0];
752 payload.tag = cpu_to_le32(tag);
753 /* Currently only one key is used. New KEK index is 1.
754 * Current KEK index is 1. Store KEK to NVRAM is 1.
755 */
756 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
757 KEK_MGMT_SUBOP_KEYCARDUPDATE);
758
759 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
760
761 return rc;
762}
763
764/**
765 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
766 * @pm8001_ha: our hba card information
767 */
768static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
769{
770 int ret;
771 u8 i = 0;
772
773 /* check the firmware status */
774 if (-1 == check_fw_ready(pm8001_ha)) {
775 PM8001_FAIL_DBG(pm8001_ha,
776 pm8001_printk("Firmware is not ready!\n"));
777 return -EBUSY;
778 }
779
780 /* Initialize pci space address eg: mpi offset */
781 init_pci_device_addresses(pm8001_ha);
782 init_default_table_values(pm8001_ha);
783 read_main_config_table(pm8001_ha);
784 read_general_status_table(pm8001_ha);
785 read_inbnd_queue_table(pm8001_ha);
786 read_outbnd_queue_table(pm8001_ha);
787 read_phy_attr_table(pm8001_ha);
788
789 /* update main config table ,inbound table and outbound table */
790 update_main_config_table(pm8001_ha);
791 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
792 update_inbnd_queue_table(pm8001_ha, i);
793 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
794 update_outbnd_queue_table(pm8001_ha, i);
795
796 /* notify firmware update finished and check initialization status */
797 if (0 == mpi_init_check(pm8001_ha)) {
798 PM8001_INIT_DBG(pm8001_ha,
799 pm8001_printk("MPI initialize successful!\n"));
800 } else
801 return -EBUSY;
802
803 /* configure thermal */
804 pm80xx_set_thermal_config(pm8001_ha);
805
806 PM8001_INIT_DBG(pm8001_ha,
807 pm8001_printk("Thermal configuration successful!\n"));
808
809 /* Check for encryption */
810 if (pm8001_ha->chip->encrypt) {
811 PM8001_INIT_DBG(pm8001_ha,
812 pm8001_printk("Checking for encryption\n"));
813 ret = pm80xx_get_encrypt_info(pm8001_ha);
814 if (ret == -1) {
815 PM8001_INIT_DBG(pm8001_ha,
816 pm8001_printk("Encryption error !!\n"));
817 if (pm8001_ha->encrypt_info.status == 0x81) {
818 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
819 "Encryption enabled with error."
820 "Saving encryption key to flash\n"));
821 pm80xx_encrypt_update(pm8001_ha);
822 }
823 }
824 }
825 return 0;
826}
827
828static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
829{
830 u32 max_wait_count;
831 u32 value;
832 u32 gst_len_mpistate;
833 init_pci_device_addresses(pm8001_ha);
834 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
835 table is stop */
836 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
837
838 /* wait until Inbound DoorBell Clear Register toggled */
839 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
840 do {
841 udelay(1);
842 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
843 value &= SPCv_MSGU_CFG_TABLE_RESET;
844 } while ((value != 0) && (--max_wait_count));
845
846 if (!max_wait_count) {
847 PM8001_FAIL_DBG(pm8001_ha,
848 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
849 return -1;
850 }
851
852 /* check the MPI-State for termination in progress */
853 /* wait until Inbound DoorBell Clear Register toggled */
854 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
855 do {
856 udelay(1);
857 gst_len_mpistate =
858 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
859 GST_GSTLEN_MPIS_OFFSET);
860 if (GST_MPI_STATE_UNINIT ==
861 (gst_len_mpistate & GST_MPI_STATE_MASK))
862 break;
863 } while (--max_wait_count);
864 if (!max_wait_count) {
865 PM8001_FAIL_DBG(pm8001_ha,
866 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
867 gst_len_mpistate & GST_MPI_STATE_MASK));
868 return -1;
869 }
870
871 return 0;
872}
873
874/**
875 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
876 * the FW register status to the originated status.
877 * @pm8001_ha: our hba card information
878 */
879
880static int
881pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
882{
883 u32 regval;
884 u32 bootloader_state;
885
886 /* Check if MPI is in ready state to reset */
887 if (mpi_uninit_check(pm8001_ha) != 0) {
888 PM8001_FAIL_DBG(pm8001_ha,
889 pm8001_printk("MPI state is not ready\n"));
890 return -1;
891 }
892
893 /* checked for reset register normal state; 0x0 */
894 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
895 PM8001_INIT_DBG(pm8001_ha,
896 pm8001_printk("reset register before write : 0x%x\n", regval));
897
898 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
899 mdelay(500);
900
901 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
902 PM8001_INIT_DBG(pm8001_ha,
903 pm8001_printk("reset register after write 0x%x\n", regval));
904
905 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
906 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
907 PM8001_MSG_DBG(pm8001_ha,
908 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
909 regval));
910 } else {
911 PM8001_MSG_DBG(pm8001_ha,
912 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
913 regval));
914
915 /* check bootloader is successfully executed or in HDA mode */
916 bootloader_state =
917 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
918 SCRATCH_PAD1_BOOTSTATE_MASK;
919
920 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
921 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
922 "Bootloader state - HDA mode SEEPROM\n"));
923 } else if (bootloader_state ==
924 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
925 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
926 "Bootloader state - HDA mode Bootstrap Pin\n"));
927 } else if (bootloader_state ==
928 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
929 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
930 "Bootloader state - HDA mode soft reset\n"));
931 } else if (bootloader_state ==
932 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
933 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
934 "Bootloader state-HDA mode critical error\n"));
935 }
936 return -EBUSY;
937 }
938
939 /* check the firmware status after reset */
940 if (-1 == check_fw_ready(pm8001_ha)) {
941 PM8001_FAIL_DBG(pm8001_ha,
942 pm8001_printk("Firmware is not ready!\n"));
943 return -EBUSY;
944 }
945 PM8001_INIT_DBG(pm8001_ha,
946 pm8001_printk("SPCv soft reset Complete\n"));
947 return 0;
948}
949
950static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
951{
952 u32 i;
953
954 PM8001_INIT_DBG(pm8001_ha,
955 pm8001_printk("chip reset start\n"));
956
957 /* do SPCv chip reset. */
958 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
959 PM8001_INIT_DBG(pm8001_ha,
960 pm8001_printk("SPC soft reset Complete\n"));
961
962 /* Check this ..whether delay is required or no */
963 /* delay 10 usec */
964 udelay(10);
965
966 /* wait for 20 msec until the firmware gets reloaded */
967 i = 20;
968 do {
969 mdelay(1);
970 } while ((--i) != 0);
971
972 PM8001_INIT_DBG(pm8001_ha,
973 pm8001_printk("chip reset finished\n"));
974}
975
976/**
977 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
978 * @pm8001_ha: our hba card information
979 */
980static void
981pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
982{
983 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
984 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
985}
986
987/**
988 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
989 * @pm8001_ha: our hba card information
990 */
991static void
992pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
993{
994 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
995}
996
997/**
998 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
999 * @pm8001_ha: our hba card information
1000 */
1001static void
1002pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1003{
1004#ifdef PM8001_USE_MSIX
1005 u32 mask;
1006 mask = (u32)(1 << vec);
1007
1008 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1009 return;
1010#endif
1011 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1012
1013}
1014
1015/**
1016 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1017 * @pm8001_ha: our hba card information
1018 */
1019static void
1020pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1021{
1022#ifdef PM8001_USE_MSIX
1023 u32 mask;
1024 if (vec == 0xFF)
1025 mask = 0xFFFFFFFF;
1026 else
1027 mask = (u32)(1 << vec);
1028 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1029 return;
1030#endif
1031 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1032}
1033
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1034static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1035 struct pm8001_device *pm8001_ha_dev)
1036{
1037 int res;
1038 u32 ccb_tag;
1039 struct pm8001_ccb_info *ccb;
1040 struct sas_task *task = NULL;
1041 struct task_abort_req task_abort;
1042 struct inbound_queue_table *circularQ;
1043 u32 opc = OPC_INB_SATA_ABORT;
1044 int ret;
1045
1046 if (!pm8001_ha_dev) {
1047 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1048 return;
1049 }
1050
1051 task = sas_alloc_slow_task(GFP_ATOMIC);
1052
1053 if (!task) {
1054 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1055 "allocate task\n"));
1056 return;
1057 }
1058
1059 task->task_done = pm8001_task_done;
1060
1061 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1062 if (res)
1063 return;
1064
1065 ccb = &pm8001_ha->ccb_info[ccb_tag];
1066 ccb->device = pm8001_ha_dev;
1067 ccb->ccb_tag = ccb_tag;
1068 ccb->task = task;
1069
1070 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1071
1072 memset(&task_abort, 0, sizeof(task_abort));
1073 task_abort.abort_all = cpu_to_le32(1);
1074 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1075 task_abort.tag = cpu_to_le32(ccb_tag);
1076
1077 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1078
1079}
1080
1081static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1082 struct pm8001_device *pm8001_ha_dev)
1083{
1084 struct sata_start_req sata_cmd;
1085 int res;
1086 u32 ccb_tag;
1087 struct pm8001_ccb_info *ccb;
1088 struct sas_task *task = NULL;
1089 struct host_to_dev_fis fis;
1090 struct domain_device *dev;
1091 struct inbound_queue_table *circularQ;
1092 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1093
1094 task = sas_alloc_slow_task(GFP_ATOMIC);
1095
1096 if (!task) {
1097 PM8001_FAIL_DBG(pm8001_ha,
1098 pm8001_printk("cannot allocate task !!!\n"));
1099 return;
1100 }
1101 task->task_done = pm8001_task_done;
1102
1103 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1104 if (res) {
1105 PM8001_FAIL_DBG(pm8001_ha,
1106 pm8001_printk("cannot allocate tag !!!\n"));
1107 return;
1108 }
1109
1110 /* allocate domain device by ourselves as libsas
1111 * is not going to provide any
1112 */
1113 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1114 if (!dev) {
1115 PM8001_FAIL_DBG(pm8001_ha,
1116 pm8001_printk("Domain device cannot be allocated\n"));
1117 sas_free_task(task);
1118 return;
1119 } else {
1120 task->dev = dev;
1121 task->dev->lldd_dev = pm8001_ha_dev;
1122 }
1123
1124 ccb = &pm8001_ha->ccb_info[ccb_tag];
1125 ccb->device = pm8001_ha_dev;
1126 ccb->ccb_tag = ccb_tag;
1127 ccb->task = task;
1128 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1129 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1130
1131 memset(&sata_cmd, 0, sizeof(sata_cmd));
1132 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1133
1134 /* construct read log FIS */
1135 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1136 fis.fis_type = 0x27;
1137 fis.flags = 0x80;
1138 fis.command = ATA_CMD_READ_LOG_EXT;
1139 fis.lbal = 0x10;
1140 fis.sector_count = 0x1;
1141
1142 sata_cmd.tag = cpu_to_le32(ccb_tag);
1143 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1144 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1145 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1146
1147 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1148
1149}
1150
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1151/**
1152 * mpi_ssp_completion- process the event that FW response to the SSP request.
1153 * @pm8001_ha: our hba card information
1154 * @piomb: the message contents of this outbound message.
1155 *
1156 * When FW has completed a ssp request for example a IO request, after it has
1157 * filled the SG data with the data, it will trigger this event represent
1158 * that he has finished the job,please check the coresponding buffer.
1159 * So we will tell the caller who maybe waiting the result to tell upper layer
1160 * that the task has been finished.
1161 */
1162static void
1163mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1164{
1165 struct sas_task *t;
1166 struct pm8001_ccb_info *ccb;
1167 unsigned long flags;
1168 u32 status;
1169 u32 param;
1170 u32 tag;
1171 struct ssp_completion_resp *psspPayload;
1172 struct task_status_struct *ts;
1173 struct ssp_response_iu *iu;
1174 struct pm8001_device *pm8001_dev;
1175 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1176 status = le32_to_cpu(psspPayload->status);
1177 tag = le32_to_cpu(psspPayload->tag);
1178 ccb = &pm8001_ha->ccb_info[tag];
1179 if ((status == IO_ABORTED) && ccb->open_retry) {
1180 /* Being completed by another */
1181 ccb->open_retry = 0;
1182 return;
1183 }
1184 pm8001_dev = ccb->device;
1185 param = le32_to_cpu(psspPayload->param);
1186 t = ccb->task;
1187
1188 if (status && status != IO_UNDERFLOW)
1189 PM8001_FAIL_DBG(pm8001_ha,
1190 pm8001_printk("sas IO status 0x%x\n", status));
1191 if (unlikely(!t || !t->lldd_task || !t->dev))
1192 return;
1193 ts = &t->task_status;
1194 switch (status) {
1195 case IO_SUCCESS:
1196 PM8001_IO_DBG(pm8001_ha,
1197 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1198 param));
1199 if (param == 0) {
1200 ts->resp = SAS_TASK_COMPLETE;
1201 ts->stat = SAM_STAT_GOOD;
1202 } else {
1203 ts->resp = SAS_TASK_COMPLETE;
1204 ts->stat = SAS_PROTO_RESPONSE;
1205 ts->residual = param;
1206 iu = &psspPayload->ssp_resp_iu;
1207 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1208 }
1209 if (pm8001_dev)
1210 pm8001_dev->running_req--;
1211 break;
1212 case IO_ABORTED:
1213 PM8001_IO_DBG(pm8001_ha,
1214 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1215 ts->resp = SAS_TASK_COMPLETE;
1216 ts->stat = SAS_ABORTED_TASK;
1217 break;
1218 case IO_UNDERFLOW:
1219 /* SSP Completion with error */
1220 PM8001_IO_DBG(pm8001_ha,
1221 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1222 param));
1223 ts->resp = SAS_TASK_COMPLETE;
1224 ts->stat = SAS_DATA_UNDERRUN;
1225 ts->residual = param;
1226 if (pm8001_dev)
1227 pm8001_dev->running_req--;
1228 break;
1229 case IO_NO_DEVICE:
1230 PM8001_IO_DBG(pm8001_ha,
1231 pm8001_printk("IO_NO_DEVICE\n"));
1232 ts->resp = SAS_TASK_UNDELIVERED;
1233 ts->stat = SAS_PHY_DOWN;
1234 break;
1235 case IO_XFER_ERROR_BREAK:
1236 PM8001_IO_DBG(pm8001_ha,
1237 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1238 ts->resp = SAS_TASK_COMPLETE;
1239 ts->stat = SAS_OPEN_REJECT;
1240 /* Force the midlayer to retry */
1241 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1242 break;
1243 case IO_XFER_ERROR_PHY_NOT_READY:
1244 PM8001_IO_DBG(pm8001_ha,
1245 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1246 ts->resp = SAS_TASK_COMPLETE;
1247 ts->stat = SAS_OPEN_REJECT;
1248 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1249 break;
1250 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1251 PM8001_IO_DBG(pm8001_ha,
1252 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1253 ts->resp = SAS_TASK_COMPLETE;
1254 ts->stat = SAS_OPEN_REJECT;
1255 ts->open_rej_reason = SAS_OREJ_EPROTO;
1256 break;
1257 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1258 PM8001_IO_DBG(pm8001_ha,
1259 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1260 ts->resp = SAS_TASK_COMPLETE;
1261 ts->stat = SAS_OPEN_REJECT;
1262 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1263 break;
1264 case IO_OPEN_CNX_ERROR_BREAK:
1265 PM8001_IO_DBG(pm8001_ha,
1266 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1267 ts->resp = SAS_TASK_COMPLETE;
1268 ts->stat = SAS_OPEN_REJECT;
1269 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1270 break;
1271 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1272 PM8001_IO_DBG(pm8001_ha,
1273 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1274 ts->resp = SAS_TASK_COMPLETE;
1275 ts->stat = SAS_OPEN_REJECT;
1276 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1277 if (!t->uldd_task)
1278 pm8001_handle_event(pm8001_ha,
1279 pm8001_dev,
1280 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1281 break;
1282 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1283 PM8001_IO_DBG(pm8001_ha,
1284 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1285 ts->resp = SAS_TASK_COMPLETE;
1286 ts->stat = SAS_OPEN_REJECT;
1287 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1288 break;
1289 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1290 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1291 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1292 ts->resp = SAS_TASK_COMPLETE;
1293 ts->stat = SAS_OPEN_REJECT;
1294 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1295 break;
1296 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1297 PM8001_IO_DBG(pm8001_ha,
1298 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1299 ts->resp = SAS_TASK_UNDELIVERED;
1300 ts->stat = SAS_OPEN_REJECT;
1301 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1302 break;
1303 case IO_XFER_ERROR_NAK_RECEIVED:
1304 PM8001_IO_DBG(pm8001_ha,
1305 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1306 ts->resp = SAS_TASK_COMPLETE;
1307 ts->stat = SAS_OPEN_REJECT;
1308 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1309 break;
1310 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1311 PM8001_IO_DBG(pm8001_ha,
1312 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1313 ts->resp = SAS_TASK_COMPLETE;
1314 ts->stat = SAS_NAK_R_ERR;
1315 break;
1316 case IO_XFER_ERROR_DMA:
1317 PM8001_IO_DBG(pm8001_ha,
1318 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1319 ts->resp = SAS_TASK_COMPLETE;
1320 ts->stat = SAS_OPEN_REJECT;
1321 break;
1322 case IO_XFER_OPEN_RETRY_TIMEOUT:
1323 PM8001_IO_DBG(pm8001_ha,
1324 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1325 ts->resp = SAS_TASK_COMPLETE;
1326 ts->stat = SAS_OPEN_REJECT;
1327 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1328 break;
1329 case IO_XFER_ERROR_OFFSET_MISMATCH:
1330 PM8001_IO_DBG(pm8001_ha,
1331 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1332 ts->resp = SAS_TASK_COMPLETE;
1333 ts->stat = SAS_OPEN_REJECT;
1334 break;
1335 case IO_PORT_IN_RESET:
1336 PM8001_IO_DBG(pm8001_ha,
1337 pm8001_printk("IO_PORT_IN_RESET\n"));
1338 ts->resp = SAS_TASK_COMPLETE;
1339 ts->stat = SAS_OPEN_REJECT;
1340 break;
1341 case IO_DS_NON_OPERATIONAL:
1342 PM8001_IO_DBG(pm8001_ha,
1343 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1344 ts->resp = SAS_TASK_COMPLETE;
1345 ts->stat = SAS_OPEN_REJECT;
1346 if (!t->uldd_task)
1347 pm8001_handle_event(pm8001_ha,
1348 pm8001_dev,
1349 IO_DS_NON_OPERATIONAL);
1350 break;
1351 case IO_DS_IN_RECOVERY:
1352 PM8001_IO_DBG(pm8001_ha,
1353 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1354 ts->resp = SAS_TASK_COMPLETE;
1355 ts->stat = SAS_OPEN_REJECT;
1356 break;
1357 case IO_TM_TAG_NOT_FOUND:
1358 PM8001_IO_DBG(pm8001_ha,
1359 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1360 ts->resp = SAS_TASK_COMPLETE;
1361 ts->stat = SAS_OPEN_REJECT;
1362 break;
1363 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1364 PM8001_IO_DBG(pm8001_ha,
1365 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1366 ts->resp = SAS_TASK_COMPLETE;
1367 ts->stat = SAS_OPEN_REJECT;
1368 break;
1369 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1370 PM8001_IO_DBG(pm8001_ha,
1371 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1372 ts->resp = SAS_TASK_COMPLETE;
1373 ts->stat = SAS_OPEN_REJECT;
1374 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1375 break;
1376 default:
1377 PM8001_IO_DBG(pm8001_ha,
1378 pm8001_printk("Unknown status 0x%x\n", status));
1379 /* not allowed case. Therefore, return failed status */
1380 ts->resp = SAS_TASK_COMPLETE;
1381 ts->stat = SAS_OPEN_REJECT;
1382 break;
1383 }
1384 PM8001_IO_DBG(pm8001_ha,
1385 pm8001_printk("scsi_status = 0x%x\n ",
1386 psspPayload->ssp_resp_iu.status));
1387 spin_lock_irqsave(&t->task_state_lock, flags);
1388 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1389 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1390 t->task_state_flags |= SAS_TASK_STATE_DONE;
1391 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1392 spin_unlock_irqrestore(&t->task_state_lock, flags);
1393 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1394 "task 0x%p done with io_status 0x%x resp 0x%x "
1395 "stat 0x%x but aborted by upper layer!\n",
1396 t, status, ts->resp, ts->stat));
1397 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1398 } else {
1399 spin_unlock_irqrestore(&t->task_state_lock, flags);
1400 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1401 mb();/* in order to force CPU ordering */
1402 t->task_done(t);
1403 }
1404}
1405
1406/*See the comments for mpi_ssp_completion */
1407static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1408{
1409 struct sas_task *t;
1410 unsigned long flags;
1411 struct task_status_struct *ts;
1412 struct pm8001_ccb_info *ccb;
1413 struct pm8001_device *pm8001_dev;
1414 struct ssp_event_resp *psspPayload =
1415 (struct ssp_event_resp *)(piomb + 4);
1416 u32 event = le32_to_cpu(psspPayload->event);
1417 u32 tag = le32_to_cpu(psspPayload->tag);
1418 u32 port_id = le32_to_cpu(psspPayload->port_id);
1419
1420 ccb = &pm8001_ha->ccb_info[tag];
1421 t = ccb->task;
1422 pm8001_dev = ccb->device;
1423 if (event)
1424 PM8001_FAIL_DBG(pm8001_ha,
1425 pm8001_printk("sas IO status 0x%x\n", event));
1426 if (unlikely(!t || !t->lldd_task || !t->dev))
1427 return;
1428 ts = &t->task_status;
1429 PM8001_IO_DBG(pm8001_ha,
1430 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1431 port_id, tag, event));
1432 switch (event) {
1433 case IO_OVERFLOW:
1434 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1435 ts->resp = SAS_TASK_COMPLETE;
1436 ts->stat = SAS_DATA_OVERRUN;
1437 ts->residual = 0;
1438 if (pm8001_dev)
1439 pm8001_dev->running_req--;
1440 break;
1441 case IO_XFER_ERROR_BREAK:
1442 PM8001_IO_DBG(pm8001_ha,
1443 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1444 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1445 return;
1446 case IO_XFER_ERROR_PHY_NOT_READY:
1447 PM8001_IO_DBG(pm8001_ha,
1448 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1449 ts->resp = SAS_TASK_COMPLETE;
1450 ts->stat = SAS_OPEN_REJECT;
1451 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1452 break;
1453 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1454 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1455 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1456 ts->resp = SAS_TASK_COMPLETE;
1457 ts->stat = SAS_OPEN_REJECT;
1458 ts->open_rej_reason = SAS_OREJ_EPROTO;
1459 break;
1460 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1461 PM8001_IO_DBG(pm8001_ha,
1462 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1463 ts->resp = SAS_TASK_COMPLETE;
1464 ts->stat = SAS_OPEN_REJECT;
1465 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1466 break;
1467 case IO_OPEN_CNX_ERROR_BREAK:
1468 PM8001_IO_DBG(pm8001_ha,
1469 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1470 ts->resp = SAS_TASK_COMPLETE;
1471 ts->stat = SAS_OPEN_REJECT;
1472 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1473 break;
1474 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1475 PM8001_IO_DBG(pm8001_ha,
1476 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1477 ts->resp = SAS_TASK_COMPLETE;
1478 ts->stat = SAS_OPEN_REJECT;
1479 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1480 if (!t->uldd_task)
1481 pm8001_handle_event(pm8001_ha,
1482 pm8001_dev,
1483 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1484 break;
1485 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1486 PM8001_IO_DBG(pm8001_ha,
1487 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1488 ts->resp = SAS_TASK_COMPLETE;
1489 ts->stat = SAS_OPEN_REJECT;
1490 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1491 break;
1492 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1493 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1494 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1495 ts->resp = SAS_TASK_COMPLETE;
1496 ts->stat = SAS_OPEN_REJECT;
1497 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1498 break;
1499 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1500 PM8001_IO_DBG(pm8001_ha,
1501 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1502 ts->resp = SAS_TASK_COMPLETE;
1503 ts->stat = SAS_OPEN_REJECT;
1504 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1505 break;
1506 case IO_XFER_ERROR_NAK_RECEIVED:
1507 PM8001_IO_DBG(pm8001_ha,
1508 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1509 ts->resp = SAS_TASK_COMPLETE;
1510 ts->stat = SAS_OPEN_REJECT;
1511 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1512 break;
1513 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1514 PM8001_IO_DBG(pm8001_ha,
1515 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1516 ts->resp = SAS_TASK_COMPLETE;
1517 ts->stat = SAS_NAK_R_ERR;
1518 break;
1519 case IO_XFER_OPEN_RETRY_TIMEOUT:
1520 PM8001_IO_DBG(pm8001_ha,
1521 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1522 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1523 return;
1524 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1525 PM8001_IO_DBG(pm8001_ha,
1526 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1527 ts->resp = SAS_TASK_COMPLETE;
1528 ts->stat = SAS_DATA_OVERRUN;
1529 break;
1530 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1531 PM8001_IO_DBG(pm8001_ha,
1532 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1533 ts->resp = SAS_TASK_COMPLETE;
1534 ts->stat = SAS_DATA_OVERRUN;
1535 break;
1536 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1537 PM8001_IO_DBG(pm8001_ha,
1538 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1539 ts->resp = SAS_TASK_COMPLETE;
1540 ts->stat = SAS_DATA_OVERRUN;
1541 break;
1542 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1543 PM8001_IO_DBG(pm8001_ha,
1544 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1545 ts->resp = SAS_TASK_COMPLETE;
1546 ts->stat = SAS_DATA_OVERRUN;
1547 break;
1548 case IO_XFER_ERROR_OFFSET_MISMATCH:
1549 PM8001_IO_DBG(pm8001_ha,
1550 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1551 ts->resp = SAS_TASK_COMPLETE;
1552 ts->stat = SAS_DATA_OVERRUN;
1553 break;
1554 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1555 PM8001_IO_DBG(pm8001_ha,
1556 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1557 ts->resp = SAS_TASK_COMPLETE;
1558 ts->stat = SAS_DATA_OVERRUN;
1559 break;
1560 case IO_XFER_CMD_FRAME_ISSUED:
1561 PM8001_IO_DBG(pm8001_ha,
1562 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1563 return;
1564 default:
1565 PM8001_IO_DBG(pm8001_ha,
1566 pm8001_printk("Unknown status 0x%x\n", event));
1567 /* not allowed case. Therefore, return failed status */
1568 ts->resp = SAS_TASK_COMPLETE;
1569 ts->stat = SAS_DATA_OVERRUN;
1570 break;
1571 }
1572 spin_lock_irqsave(&t->task_state_lock, flags);
1573 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1574 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1575 t->task_state_flags |= SAS_TASK_STATE_DONE;
1576 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1577 spin_unlock_irqrestore(&t->task_state_lock, flags);
1578 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1579 "task 0x%p done with event 0x%x resp 0x%x "
1580 "stat 0x%x but aborted by upper layer!\n",
1581 t, event, ts->resp, ts->stat));
1582 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1583 } else {
1584 spin_unlock_irqrestore(&t->task_state_lock, flags);
1585 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1586 mb();/* in order to force CPU ordering */
1587 t->task_done(t);
1588 }
1589}
1590
1591/*See the comments for mpi_ssp_completion */
1592static void
1593mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1594{
1595 struct sas_task *t;
1596 struct pm8001_ccb_info *ccb;
1597 u32 param;
1598 u32 status;
1599 u32 tag;
1600 struct sata_completion_resp *psataPayload;
1601 struct task_status_struct *ts;
1602 struct ata_task_resp *resp ;
1603 u32 *sata_resp;
1604 struct pm8001_device *pm8001_dev;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1605 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1606
1607 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1608 status = le32_to_cpu(psataPayload->status);
1609 tag = le32_to_cpu(psataPayload->tag);
1610
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1611 if (!tag) {
1612 PM8001_FAIL_DBG(pm8001_ha,
1613 pm8001_printk("tag null\n"));
1614 return;
1615 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1616 ccb = &pm8001_ha->ccb_info[tag];
1617 param = le32_to_cpu(psataPayload->param);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1618 if (ccb) {
1619 t = ccb->task;
1620 pm8001_dev = ccb->device;
1621 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1622 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1623 pm8001_printk("ccb null\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1624 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1625 }
1626
1627 if (t) {
1628 if (t->dev && (t->dev->lldd_dev))
1629 pm8001_dev = t->dev->lldd_dev;
1630 } else {
1631 PM8001_FAIL_DBG(pm8001_ha,
1632 pm8001_printk("task null\n"));
1633 return;
1634 }
1635
1636 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1637 && unlikely(!t || !t->lldd_task || !t->dev)) {
1638 PM8001_FAIL_DBG(pm8001_ha,
1639 pm8001_printk("task or dev null\n"));
1640 return;
1641 }
1642
1643 ts = &t->task_status;
1644 if (!ts) {
1645 PM8001_FAIL_DBG(pm8001_ha,
1646 pm8001_printk("ts null\n"));
1647 return;
1648 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1649
1650 switch (status) {
1651 case IO_SUCCESS:
1652 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1653 if (param == 0) {
1654 ts->resp = SAS_TASK_COMPLETE;
1655 ts->stat = SAM_STAT_GOOD;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1656 /* check if response is for SEND READ LOG */
1657 if (pm8001_dev &&
1658 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
1659 /* set new bit for abort_all */
1660 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
1661 /* clear bit for read log */
1662 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
1663 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
1664 /* Free the tag */
1665 pm8001_tag_free(pm8001_ha, tag);
1666 sas_free_task(t);
1667 return;
1668 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1669 } else {
1670 u8 len;
1671 ts->resp = SAS_TASK_COMPLETE;
1672 ts->stat = SAS_PROTO_RESPONSE;
1673 ts->residual = param;
1674 PM8001_IO_DBG(pm8001_ha,
1675 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1676 param));
1677 sata_resp = &psataPayload->sata_resp[0];
1678 resp = (struct ata_task_resp *)ts->buf;
1679 if (t->ata_task.dma_xfer == 0 &&
1680 t->data_dir == PCI_DMA_FROMDEVICE) {
1681 len = sizeof(struct pio_setup_fis);
1682 PM8001_IO_DBG(pm8001_ha,
1683 pm8001_printk("PIO read len = %d\n", len));
1684 } else if (t->ata_task.use_ncq) {
1685 len = sizeof(struct set_dev_bits_fis);
1686 PM8001_IO_DBG(pm8001_ha,
1687 pm8001_printk("FPDMA len = %d\n", len));
1688 } else {
1689 len = sizeof(struct dev_to_host_fis);
1690 PM8001_IO_DBG(pm8001_ha,
1691 pm8001_printk("other len = %d\n", len));
1692 }
1693 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1694 resp->frame_len = len;
1695 memcpy(&resp->ending_fis[0], sata_resp, len);
1696 ts->buf_valid_size = sizeof(*resp);
1697 } else
1698 PM8001_IO_DBG(pm8001_ha,
1699 pm8001_printk("response to large\n"));
1700 }
1701 if (pm8001_dev)
1702 pm8001_dev->running_req--;
1703 break;
1704 case IO_ABORTED:
1705 PM8001_IO_DBG(pm8001_ha,
1706 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1707 ts->resp = SAS_TASK_COMPLETE;
1708 ts->stat = SAS_ABORTED_TASK;
1709 if (pm8001_dev)
1710 pm8001_dev->running_req--;
1711 break;
1712 /* following cases are to do cases */
1713 case IO_UNDERFLOW:
1714 /* SATA Completion with error */
1715 PM8001_IO_DBG(pm8001_ha,
1716 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1717 ts->resp = SAS_TASK_COMPLETE;
1718 ts->stat = SAS_DATA_UNDERRUN;
1719 ts->residual = param;
1720 if (pm8001_dev)
1721 pm8001_dev->running_req--;
1722 break;
1723 case IO_NO_DEVICE:
1724 PM8001_IO_DBG(pm8001_ha,
1725 pm8001_printk("IO_NO_DEVICE\n"));
1726 ts->resp = SAS_TASK_UNDELIVERED;
1727 ts->stat = SAS_PHY_DOWN;
1728 break;
1729 case IO_XFER_ERROR_BREAK:
1730 PM8001_IO_DBG(pm8001_ha,
1731 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1732 ts->resp = SAS_TASK_COMPLETE;
1733 ts->stat = SAS_INTERRUPTED;
1734 break;
1735 case IO_XFER_ERROR_PHY_NOT_READY:
1736 PM8001_IO_DBG(pm8001_ha,
1737 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1738 ts->resp = SAS_TASK_COMPLETE;
1739 ts->stat = SAS_OPEN_REJECT;
1740 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1741 break;
1742 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1743 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1744 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1745 ts->resp = SAS_TASK_COMPLETE;
1746 ts->stat = SAS_OPEN_REJECT;
1747 ts->open_rej_reason = SAS_OREJ_EPROTO;
1748 break;
1749 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1750 PM8001_IO_DBG(pm8001_ha,
1751 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1752 ts->resp = SAS_TASK_COMPLETE;
1753 ts->stat = SAS_OPEN_REJECT;
1754 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1755 break;
1756 case IO_OPEN_CNX_ERROR_BREAK:
1757 PM8001_IO_DBG(pm8001_ha,
1758 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1759 ts->resp = SAS_TASK_COMPLETE;
1760 ts->stat = SAS_OPEN_REJECT;
1761 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1762 break;
1763 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1764 PM8001_IO_DBG(pm8001_ha,
1765 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1766 ts->resp = SAS_TASK_COMPLETE;
1767 ts->stat = SAS_DEV_NO_RESPONSE;
1768 if (!t->uldd_task) {
1769 pm8001_handle_event(pm8001_ha,
1770 pm8001_dev,
1771 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1772 ts->resp = SAS_TASK_UNDELIVERED;
1773 ts->stat = SAS_QUEUE_FULL;
1774 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1775 mb();/*in order to force CPU ordering*/
1776 spin_unlock_irq(&pm8001_ha->lock);
1777 t->task_done(t);
1778 spin_lock_irq(&pm8001_ha->lock);
1779 return;
1780 }
1781 break;
1782 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1783 PM8001_IO_DBG(pm8001_ha,
1784 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1785 ts->resp = SAS_TASK_UNDELIVERED;
1786 ts->stat = SAS_OPEN_REJECT;
1787 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1788 if (!t->uldd_task) {
1789 pm8001_handle_event(pm8001_ha,
1790 pm8001_dev,
1791 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1792 ts->resp = SAS_TASK_UNDELIVERED;
1793 ts->stat = SAS_QUEUE_FULL;
1794 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1795 mb();/*ditto*/
1796 spin_unlock_irq(&pm8001_ha->lock);
1797 t->task_done(t);
1798 spin_lock_irq(&pm8001_ha->lock);
1799 return;
1800 }
1801 break;
1802 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1803 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1804 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1805 ts->resp = SAS_TASK_COMPLETE;
1806 ts->stat = SAS_OPEN_REJECT;
1807 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1808 break;
1809 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1810 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1811 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1812 ts->resp = SAS_TASK_COMPLETE;
1813 ts->stat = SAS_DEV_NO_RESPONSE;
1814 if (!t->uldd_task) {
1815 pm8001_handle_event(pm8001_ha,
1816 pm8001_dev,
1817 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1818 ts->resp = SAS_TASK_UNDELIVERED;
1819 ts->stat = SAS_QUEUE_FULL;
1820 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1821 mb();/* ditto*/
1822 spin_unlock_irq(&pm8001_ha->lock);
1823 t->task_done(t);
1824 spin_lock_irq(&pm8001_ha->lock);
1825 return;
1826 }
1827 break;
1828 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1829 PM8001_IO_DBG(pm8001_ha,
1830 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1831 ts->resp = SAS_TASK_COMPLETE;
1832 ts->stat = SAS_OPEN_REJECT;
1833 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1834 break;
1835 case IO_XFER_ERROR_NAK_RECEIVED:
1836 PM8001_IO_DBG(pm8001_ha,
1837 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1838 ts->resp = SAS_TASK_COMPLETE;
1839 ts->stat = SAS_NAK_R_ERR;
1840 break;
1841 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1842 PM8001_IO_DBG(pm8001_ha,
1843 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1844 ts->resp = SAS_TASK_COMPLETE;
1845 ts->stat = SAS_NAK_R_ERR;
1846 break;
1847 case IO_XFER_ERROR_DMA:
1848 PM8001_IO_DBG(pm8001_ha,
1849 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1850 ts->resp = SAS_TASK_COMPLETE;
1851 ts->stat = SAS_ABORTED_TASK;
1852 break;
1853 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
1854 PM8001_IO_DBG(pm8001_ha,
1855 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
1856 ts->resp = SAS_TASK_UNDELIVERED;
1857 ts->stat = SAS_DEV_NO_RESPONSE;
1858 break;
1859 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
1860 PM8001_IO_DBG(pm8001_ha,
1861 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
1862 ts->resp = SAS_TASK_COMPLETE;
1863 ts->stat = SAS_DATA_UNDERRUN;
1864 break;
1865 case IO_XFER_OPEN_RETRY_TIMEOUT:
1866 PM8001_IO_DBG(pm8001_ha,
1867 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1868 ts->resp = SAS_TASK_COMPLETE;
1869 ts->stat = SAS_OPEN_TO;
1870 break;
1871 case IO_PORT_IN_RESET:
1872 PM8001_IO_DBG(pm8001_ha,
1873 pm8001_printk("IO_PORT_IN_RESET\n"));
1874 ts->resp = SAS_TASK_COMPLETE;
1875 ts->stat = SAS_DEV_NO_RESPONSE;
1876 break;
1877 case IO_DS_NON_OPERATIONAL:
1878 PM8001_IO_DBG(pm8001_ha,
1879 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1880 ts->resp = SAS_TASK_COMPLETE;
1881 ts->stat = SAS_DEV_NO_RESPONSE;
1882 if (!t->uldd_task) {
1883 pm8001_handle_event(pm8001_ha, pm8001_dev,
1884 IO_DS_NON_OPERATIONAL);
1885 ts->resp = SAS_TASK_UNDELIVERED;
1886 ts->stat = SAS_QUEUE_FULL;
1887 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1888 mb();/*ditto*/
1889 spin_unlock_irq(&pm8001_ha->lock);
1890 t->task_done(t);
1891 spin_lock_irq(&pm8001_ha->lock);
1892 return;
1893 }
1894 break;
1895 case IO_DS_IN_RECOVERY:
1896 PM8001_IO_DBG(pm8001_ha,
1897 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1898 ts->resp = SAS_TASK_COMPLETE;
1899 ts->stat = SAS_DEV_NO_RESPONSE;
1900 break;
1901 case IO_DS_IN_ERROR:
1902 PM8001_IO_DBG(pm8001_ha,
1903 pm8001_printk("IO_DS_IN_ERROR\n"));
1904 ts->resp = SAS_TASK_COMPLETE;
1905 ts->stat = SAS_DEV_NO_RESPONSE;
1906 if (!t->uldd_task) {
1907 pm8001_handle_event(pm8001_ha, pm8001_dev,
1908 IO_DS_IN_ERROR);
1909 ts->resp = SAS_TASK_UNDELIVERED;
1910 ts->stat = SAS_QUEUE_FULL;
1911 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1912 mb();/*ditto*/
1913 spin_unlock_irq(&pm8001_ha->lock);
1914 t->task_done(t);
1915 spin_lock_irq(&pm8001_ha->lock);
1916 return;
1917 }
1918 break;
1919 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1920 PM8001_IO_DBG(pm8001_ha,
1921 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1922 ts->resp = SAS_TASK_COMPLETE;
1923 ts->stat = SAS_OPEN_REJECT;
1924 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1925 default:
1926 PM8001_IO_DBG(pm8001_ha,
1927 pm8001_printk("Unknown status 0x%x\n", status));
1928 /* not allowed case. Therefore, return failed status */
1929 ts->resp = SAS_TASK_COMPLETE;
1930 ts->stat = SAS_DEV_NO_RESPONSE;
1931 break;
1932 }
1933 spin_lock_irqsave(&t->task_state_lock, flags);
1934 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1935 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1936 t->task_state_flags |= SAS_TASK_STATE_DONE;
1937 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1938 spin_unlock_irqrestore(&t->task_state_lock, flags);
1939 PM8001_FAIL_DBG(pm8001_ha,
1940 pm8001_printk("task 0x%p done with io_status 0x%x"
1941 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
1942 t, status, ts->resp, ts->stat));
1943 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1944 } else if (t->uldd_task) {
1945 spin_unlock_irqrestore(&t->task_state_lock, flags);
1946 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1947 mb();/* ditto */
1948 spin_unlock_irq(&pm8001_ha->lock);
1949 t->task_done(t);
1950 spin_lock_irq(&pm8001_ha->lock);
1951 } else if (!t->uldd_task) {
1952 spin_unlock_irqrestore(&t->task_state_lock, flags);
1953 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1954 mb();/*ditto*/
1955 spin_unlock_irq(&pm8001_ha->lock);
1956 t->task_done(t);
1957 spin_lock_irq(&pm8001_ha->lock);
1958 }
1959}
1960
1961/*See the comments for mpi_ssp_completion */
1962static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1963{
1964 struct sas_task *t;
1965 struct task_status_struct *ts;
1966 struct pm8001_ccb_info *ccb;
1967 struct pm8001_device *pm8001_dev;
1968 struct sata_event_resp *psataPayload =
1969 (struct sata_event_resp *)(piomb + 4);
1970 u32 event = le32_to_cpu(psataPayload->event);
1971 u32 tag = le32_to_cpu(psataPayload->tag);
1972 u32 port_id = le32_to_cpu(psataPayload->port_id);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1973 u32 dev_id = le32_to_cpu(psataPayload->device_id);
1974 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1975
1976 ccb = &pm8001_ha->ccb_info[tag];
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1977
1978 if (ccb) {
1979 t = ccb->task;
1980 pm8001_dev = ccb->device;
1981 } else {
1982 PM8001_FAIL_DBG(pm8001_ha,
1983 pm8001_printk("No CCB !!!. returning\n"));
1984 return;
1985 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1986 if (event)
1987 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1988 pm8001_printk("SATA EVENT 0x%x\n", event));
1989
1990 /* Check if this is NCQ error */
1991 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
1992 /* find device using device id */
1993 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
1994 /* send read log extension */
1995 if (pm8001_dev)
1996 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1997 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]1998 }
1999
2000 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2001 PM8001_FAIL_DBG(pm8001_ha,
2002 pm8001_printk("task or dev null\n"));
2003 return;
2004 }
2005
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2006 ts = &t->task_status;
2007 PM8001_IO_DBG(pm8001_ha,
2008 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2009 port_id, tag, event));
2010 switch (event) {
2011 case IO_OVERFLOW:
2012 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2013 ts->resp = SAS_TASK_COMPLETE;
2014 ts->stat = SAS_DATA_OVERRUN;
2015 ts->residual = 0;
2016 if (pm8001_dev)
2017 pm8001_dev->running_req--;
2018 break;
2019 case IO_XFER_ERROR_BREAK:
2020 PM8001_IO_DBG(pm8001_ha,
2021 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2022 ts->resp = SAS_TASK_COMPLETE;
2023 ts->stat = SAS_INTERRUPTED;
2024 break;
2025 case IO_XFER_ERROR_PHY_NOT_READY:
2026 PM8001_IO_DBG(pm8001_ha,
2027 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2028 ts->resp = SAS_TASK_COMPLETE;
2029 ts->stat = SAS_OPEN_REJECT;
2030 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2031 break;
2032 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2033 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2034 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2035 ts->resp = SAS_TASK_COMPLETE;
2036 ts->stat = SAS_OPEN_REJECT;
2037 ts->open_rej_reason = SAS_OREJ_EPROTO;
2038 break;
2039 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2040 PM8001_IO_DBG(pm8001_ha,
2041 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2042 ts->resp = SAS_TASK_COMPLETE;
2043 ts->stat = SAS_OPEN_REJECT;
2044 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2045 break;
2046 case IO_OPEN_CNX_ERROR_BREAK:
2047 PM8001_IO_DBG(pm8001_ha,
2048 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2049 ts->resp = SAS_TASK_COMPLETE;
2050 ts->stat = SAS_OPEN_REJECT;
2051 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2052 break;
2053 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2054 PM8001_IO_DBG(pm8001_ha,
2055 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2056 ts->resp = SAS_TASK_UNDELIVERED;
2057 ts->stat = SAS_DEV_NO_RESPONSE;
2058 if (!t->uldd_task) {
2059 pm8001_handle_event(pm8001_ha,
2060 pm8001_dev,
2061 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2062 ts->resp = SAS_TASK_COMPLETE;
2063 ts->stat = SAS_QUEUE_FULL;
2064 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2065 mb();/*ditto*/
2066 spin_unlock_irq(&pm8001_ha->lock);
2067 t->task_done(t);
2068 spin_lock_irq(&pm8001_ha->lock);
2069 return;
2070 }
2071 break;
2072 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2073 PM8001_IO_DBG(pm8001_ha,
2074 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2075 ts->resp = SAS_TASK_UNDELIVERED;
2076 ts->stat = SAS_OPEN_REJECT;
2077 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2078 break;
2079 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2080 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2081 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2082 ts->resp = SAS_TASK_COMPLETE;
2083 ts->stat = SAS_OPEN_REJECT;
2084 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2085 break;
2086 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2087 PM8001_IO_DBG(pm8001_ha,
2088 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2089 ts->resp = SAS_TASK_COMPLETE;
2090 ts->stat = SAS_OPEN_REJECT;
2091 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2092 break;
2093 case IO_XFER_ERROR_NAK_RECEIVED:
2094 PM8001_IO_DBG(pm8001_ha,
2095 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2096 ts->resp = SAS_TASK_COMPLETE;
2097 ts->stat = SAS_NAK_R_ERR;
2098 break;
2099 case IO_XFER_ERROR_PEER_ABORTED:
2100 PM8001_IO_DBG(pm8001_ha,
2101 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2102 ts->resp = SAS_TASK_COMPLETE;
2103 ts->stat = SAS_NAK_R_ERR;
2104 break;
2105 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2106 PM8001_IO_DBG(pm8001_ha,
2107 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2108 ts->resp = SAS_TASK_COMPLETE;
2109 ts->stat = SAS_DATA_UNDERRUN;
2110 break;
2111 case IO_XFER_OPEN_RETRY_TIMEOUT:
2112 PM8001_IO_DBG(pm8001_ha,
2113 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2114 ts->resp = SAS_TASK_COMPLETE;
2115 ts->stat = SAS_OPEN_TO;
2116 break;
2117 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2118 PM8001_IO_DBG(pm8001_ha,
2119 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2120 ts->resp = SAS_TASK_COMPLETE;
2121 ts->stat = SAS_OPEN_TO;
2122 break;
2123 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2124 PM8001_IO_DBG(pm8001_ha,
2125 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2126 ts->resp = SAS_TASK_COMPLETE;
2127 ts->stat = SAS_OPEN_TO;
2128 break;
2129 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2130 PM8001_IO_DBG(pm8001_ha,
2131 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2132 ts->resp = SAS_TASK_COMPLETE;
2133 ts->stat = SAS_OPEN_TO;
2134 break;
2135 case IO_XFER_ERROR_OFFSET_MISMATCH:
2136 PM8001_IO_DBG(pm8001_ha,
2137 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2138 ts->resp = SAS_TASK_COMPLETE;
2139 ts->stat = SAS_OPEN_TO;
2140 break;
2141 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2142 PM8001_IO_DBG(pm8001_ha,
2143 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2144 ts->resp = SAS_TASK_COMPLETE;
2145 ts->stat = SAS_OPEN_TO;
2146 break;
2147 case IO_XFER_CMD_FRAME_ISSUED:
2148 PM8001_IO_DBG(pm8001_ha,
2149 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2150 break;
2151 case IO_XFER_PIO_SETUP_ERROR:
2152 PM8001_IO_DBG(pm8001_ha,
2153 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2154 ts->resp = SAS_TASK_COMPLETE;
2155 ts->stat = SAS_OPEN_TO;
2156 break;
2157 default:
2158 PM8001_IO_DBG(pm8001_ha,
2159 pm8001_printk("Unknown status 0x%x\n", event));
2160 /* not allowed case. Therefore, return failed status */
2161 ts->resp = SAS_TASK_COMPLETE;
2162 ts->stat = SAS_OPEN_TO;
2163 break;
2164 }
2165 spin_lock_irqsave(&t->task_state_lock, flags);
2166 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2167 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2168 t->task_state_flags |= SAS_TASK_STATE_DONE;
2169 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2170 spin_unlock_irqrestore(&t->task_state_lock, flags);
2171 PM8001_FAIL_DBG(pm8001_ha,
2172 pm8001_printk("task 0x%p done with io_status 0x%x"
2173 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2174 t, event, ts->resp, ts->stat));
2175 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2176 } else if (t->uldd_task) {
2177 spin_unlock_irqrestore(&t->task_state_lock, flags);
2178 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2179 mb();/* ditto */
2180 spin_unlock_irq(&pm8001_ha->lock);
2181 t->task_done(t);
2182 spin_lock_irq(&pm8001_ha->lock);
2183 } else if (!t->uldd_task) {
2184 spin_unlock_irqrestore(&t->task_state_lock, flags);
2185 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2186 mb();/*ditto*/
2187 spin_unlock_irq(&pm8001_ha->lock);
2188 t->task_done(t);
2189 spin_lock_irq(&pm8001_ha->lock);
2190 }
2191}
2192
2193/*See the comments for mpi_ssp_completion */
2194static void
2195mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2196{
2197 u32 param, i;
2198 struct sas_task *t;
2199 struct pm8001_ccb_info *ccb;
2200 unsigned long flags;
2201 u32 status;
2202 u32 tag;
2203 struct smp_completion_resp *psmpPayload;
2204 struct task_status_struct *ts;
2205 struct pm8001_device *pm8001_dev;
2206 char *pdma_respaddr = NULL;
2207
2208 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2209 status = le32_to_cpu(psmpPayload->status);
2210 tag = le32_to_cpu(psmpPayload->tag);
2211
2212 ccb = &pm8001_ha->ccb_info[tag];
2213 param = le32_to_cpu(psmpPayload->param);
2214 t = ccb->task;
2215 ts = &t->task_status;
2216 pm8001_dev = ccb->device;
2217 if (status)
2218 PM8001_FAIL_DBG(pm8001_ha,
2219 pm8001_printk("smp IO status 0x%x\n", status));
2220 if (unlikely(!t || !t->lldd_task || !t->dev))
2221 return;
2222
2223 switch (status) {
2224
2225 case IO_SUCCESS:
2226 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2227 ts->resp = SAS_TASK_COMPLETE;
2228 ts->stat = SAM_STAT_GOOD;
2229 if (pm8001_dev)
2230 pm8001_dev->running_req--;
2231 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2232 PM8001_IO_DBG(pm8001_ha,
2233 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2234 param));
2235 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2236 ((u64)sg_dma_address
2237 (&t->smp_task.smp_resp))));
2238 for (i = 0; i < param; i++) {
2239 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2240 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2241 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2242 i, *(pdma_respaddr+i),
2243 psmpPayload->_r_a[i]));
2244 }
2245 }
2246 break;
2247 case IO_ABORTED:
2248 PM8001_IO_DBG(pm8001_ha,
2249 pm8001_printk("IO_ABORTED IOMB\n"));
2250 ts->resp = SAS_TASK_COMPLETE;
2251 ts->stat = SAS_ABORTED_TASK;
2252 if (pm8001_dev)
2253 pm8001_dev->running_req--;
2254 break;
2255 case IO_OVERFLOW:
2256 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2257 ts->resp = SAS_TASK_COMPLETE;
2258 ts->stat = SAS_DATA_OVERRUN;
2259 ts->residual = 0;
2260 if (pm8001_dev)
2261 pm8001_dev->running_req--;
2262 break;
2263 case IO_NO_DEVICE:
2264 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2265 ts->resp = SAS_TASK_COMPLETE;
2266 ts->stat = SAS_PHY_DOWN;
2267 break;
2268 case IO_ERROR_HW_TIMEOUT:
2269 PM8001_IO_DBG(pm8001_ha,
2270 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2271 ts->resp = SAS_TASK_COMPLETE;
2272 ts->stat = SAM_STAT_BUSY;
2273 break;
2274 case IO_XFER_ERROR_BREAK:
2275 PM8001_IO_DBG(pm8001_ha,
2276 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2277 ts->resp = SAS_TASK_COMPLETE;
2278 ts->stat = SAM_STAT_BUSY;
2279 break;
2280 case IO_XFER_ERROR_PHY_NOT_READY:
2281 PM8001_IO_DBG(pm8001_ha,
2282 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2283 ts->resp = SAS_TASK_COMPLETE;
2284 ts->stat = SAM_STAT_BUSY;
2285 break;
2286 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2287 PM8001_IO_DBG(pm8001_ha,
2288 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2289 ts->resp = SAS_TASK_COMPLETE;
2290 ts->stat = SAS_OPEN_REJECT;
2291 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2292 break;
2293 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2294 PM8001_IO_DBG(pm8001_ha,
2295 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2296 ts->resp = SAS_TASK_COMPLETE;
2297 ts->stat = SAS_OPEN_REJECT;
2298 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2299 break;
2300 case IO_OPEN_CNX_ERROR_BREAK:
2301 PM8001_IO_DBG(pm8001_ha,
2302 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2303 ts->resp = SAS_TASK_COMPLETE;
2304 ts->stat = SAS_OPEN_REJECT;
2305 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2306 break;
2307 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2308 PM8001_IO_DBG(pm8001_ha,
2309 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2310 ts->resp = SAS_TASK_COMPLETE;
2311 ts->stat = SAS_OPEN_REJECT;
2312 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2313 pm8001_handle_event(pm8001_ha,
2314 pm8001_dev,
2315 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2316 break;
2317 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2318 PM8001_IO_DBG(pm8001_ha,
2319 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2320 ts->resp = SAS_TASK_COMPLETE;
2321 ts->stat = SAS_OPEN_REJECT;
2322 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2323 break;
2324 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2325 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2326 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2327 ts->resp = SAS_TASK_COMPLETE;
2328 ts->stat = SAS_OPEN_REJECT;
2329 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2330 break;
2331 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2332 PM8001_IO_DBG(pm8001_ha,
2333 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2334 ts->resp = SAS_TASK_COMPLETE;
2335 ts->stat = SAS_OPEN_REJECT;
2336 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2337 break;
2338 case IO_XFER_ERROR_RX_FRAME:
2339 PM8001_IO_DBG(pm8001_ha,
2340 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2341 ts->resp = SAS_TASK_COMPLETE;
2342 ts->stat = SAS_DEV_NO_RESPONSE;
2343 break;
2344 case IO_XFER_OPEN_RETRY_TIMEOUT:
2345 PM8001_IO_DBG(pm8001_ha,
2346 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_OPEN_REJECT;
2349 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2350 break;
2351 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2352 PM8001_IO_DBG(pm8001_ha,
2353 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2354 ts->resp = SAS_TASK_COMPLETE;
2355 ts->stat = SAS_QUEUE_FULL;
2356 break;
2357 case IO_PORT_IN_RESET:
2358 PM8001_IO_DBG(pm8001_ha,
2359 pm8001_printk("IO_PORT_IN_RESET\n"));
2360 ts->resp = SAS_TASK_COMPLETE;
2361 ts->stat = SAS_OPEN_REJECT;
2362 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2363 break;
2364 case IO_DS_NON_OPERATIONAL:
2365 PM8001_IO_DBG(pm8001_ha,
2366 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2367 ts->resp = SAS_TASK_COMPLETE;
2368 ts->stat = SAS_DEV_NO_RESPONSE;
2369 break;
2370 case IO_DS_IN_RECOVERY:
2371 PM8001_IO_DBG(pm8001_ha,
2372 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2373 ts->resp = SAS_TASK_COMPLETE;
2374 ts->stat = SAS_OPEN_REJECT;
2375 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2376 break;
2377 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2378 PM8001_IO_DBG(pm8001_ha,
2379 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2380 ts->resp = SAS_TASK_COMPLETE;
2381 ts->stat = SAS_OPEN_REJECT;
2382 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2383 break;
2384 default:
2385 PM8001_IO_DBG(pm8001_ha,
2386 pm8001_printk("Unknown status 0x%x\n", status));
2387 ts->resp = SAS_TASK_COMPLETE;
2388 ts->stat = SAS_DEV_NO_RESPONSE;
2389 /* not allowed case. Therefore, return failed status */
2390 break;
2391 }
2392 spin_lock_irqsave(&t->task_state_lock, flags);
2393 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2394 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2395 t->task_state_flags |= SAS_TASK_STATE_DONE;
2396 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2397 spin_unlock_irqrestore(&t->task_state_lock, flags);
2398 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2399 "task 0x%p done with io_status 0x%x resp 0x%x"
2400 "stat 0x%x but aborted by upper layer!\n",
2401 t, status, ts->resp, ts->stat));
2402 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2403 } else {
2404 spin_unlock_irqrestore(&t->task_state_lock, flags);
2405 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2406 mb();/* in order to force CPU ordering */
2407 t->task_done(t);
2408 }
2409}
2410
2411/**
2412 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2413 * @pm8001_ha: our hba card information
2414 * @Qnum: the outbound queue message number.
2415 * @SEA: source of event to ack
2416 * @port_id: port id.
2417 * @phyId: phy id.
2418 * @param0: parameter 0.
2419 * @param1: parameter 1.
2420 */
2421static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2422 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2423{
2424 struct hw_event_ack_req payload;
2425 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2426
2427 struct inbound_queue_table *circularQ;
2428
2429 memset((u8 *)&payload, 0, sizeof(payload));
2430 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2431 payload.tag = cpu_to_le32(1);
2432 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2433 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2434 payload.param0 = cpu_to_le32(param0);
2435 payload.param1 = cpu_to_le32(param1);
2436 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2437}
2438
2439static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2440 u32 phyId, u32 phy_op);
2441
2442/**
2443 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2444 * @pm8001_ha: our hba card information
2445 * @piomb: IO message buffer
2446 */
2447static void
2448hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2449{
2450 struct hw_event_resp *pPayload =
2451 (struct hw_event_resp *)(piomb + 4);
2452 u32 lr_status_evt_portid =
2453 le32_to_cpu(pPayload->lr_status_evt_portid);
2454 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2455
2456 u8 link_rate =
2457 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2458 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2459 u8 phy_id =
2460 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2461 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2462
2463 struct pm8001_port *port = &pm8001_ha->port[port_id];
2464 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2465 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2466 unsigned long flags;
2467 u8 deviceType = pPayload->sas_identify.dev_type;
2468 port->port_state = portstate;
2469 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2470 "portid:%d; phyid:%d; linkrate:%d; "
2471 "portstate:%x; devicetype:%x\n",
2472 port_id, phy_id, link_rate, portstate, deviceType));
2473
2474 switch (deviceType) {
2475 case SAS_PHY_UNUSED:
2476 PM8001_MSG_DBG(pm8001_ha,
2477 pm8001_printk("device type no device.\n"));
2478 break;
2479 case SAS_END_DEVICE:
2480 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2481 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2482 PHY_NOTIFY_ENABLE_SPINUP);
2483 port->port_attached = 1;
2484 pm8001_get_lrate_mode(phy, link_rate);
2485 break;
2486 case SAS_EDGE_EXPANDER_DEVICE:
2487 PM8001_MSG_DBG(pm8001_ha,
2488 pm8001_printk("expander device.\n"));
2489 port->port_attached = 1;
2490 pm8001_get_lrate_mode(phy, link_rate);
2491 break;
2492 case SAS_FANOUT_EXPANDER_DEVICE:
2493 PM8001_MSG_DBG(pm8001_ha,
2494 pm8001_printk("fanout expander device.\n"));
2495 port->port_attached = 1;
2496 pm8001_get_lrate_mode(phy, link_rate);
2497 break;
2498 default:
2499 PM8001_MSG_DBG(pm8001_ha,
2500 pm8001_printk("unknown device type(%x)\n", deviceType));
2501 break;
2502 }
2503 phy->phy_type |= PORT_TYPE_SAS;
2504 phy->identify.device_type = deviceType;
2505 phy->phy_attached = 1;
2506 if (phy->identify.device_type == SAS_END_DEVICE)
2507 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2508 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2509 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2510 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2511 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2512 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2513 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2514 sizeof(struct sas_identify_frame)-4);
2515 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2516 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2517 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2518 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2519 mdelay(200);/*delay a moment to wait disk to spinup*/
2520 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2521}
2522
2523/**
2524 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2525 * @pm8001_ha: our hba card information
2526 * @piomb: IO message buffer
2527 */
2528static void
2529hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2530{
2531 struct hw_event_resp *pPayload =
2532 (struct hw_event_resp *)(piomb + 4);
2533 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2534 u32 lr_status_evt_portid =
2535 le32_to_cpu(pPayload->lr_status_evt_portid);
2536 u8 link_rate =
2537 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2538 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2539 u8 phy_id =
2540 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2541
2542 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2543
2544 struct pm8001_port *port = &pm8001_ha->port[port_id];
2545 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2546 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2547 unsigned long flags;
2548 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2549 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2550 port_id, phy_id, link_rate, portstate));
2551
2552 port->port_state = portstate;
2553 port->port_attached = 1;
2554 pm8001_get_lrate_mode(phy, link_rate);
2555 phy->phy_type |= PORT_TYPE_SATA;
2556 phy->phy_attached = 1;
2557 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2558 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2559 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2560 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2561 sizeof(struct dev_to_host_fis));
2562 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2563 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2564 phy->identify.device_type = SATA_DEV;
2565 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2566 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2567 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2568}
2569
2570/**
2571 * hw_event_phy_down -we should notify the libsas the phy is down.
2572 * @pm8001_ha: our hba card information
2573 * @piomb: IO message buffer
2574 */
2575static void
2576hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2577{
2578 struct hw_event_resp *pPayload =
2579 (struct hw_event_resp *)(piomb + 4);
2580
2581 u32 lr_status_evt_portid =
2582 le32_to_cpu(pPayload->lr_status_evt_portid);
2583 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2584 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2585 u8 phy_id =
2586 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2587 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2588
2589 struct pm8001_port *port = &pm8001_ha->port[port_id];
2590 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2591 port->port_state = portstate;
2592 phy->phy_type = 0;
2593 phy->identify.device_type = 0;
2594 phy->phy_attached = 0;
2595 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2596 switch (portstate) {
2597 case PORT_VALID:
2598 break;
2599 case PORT_INVALID:
2600 PM8001_MSG_DBG(pm8001_ha,
2601 pm8001_printk(" PortInvalid portID %d\n", port_id));
2602 PM8001_MSG_DBG(pm8001_ha,
2603 pm8001_printk(" Last phy Down and port invalid\n"));
2604 port->port_attached = 0;
2605 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2606 port_id, phy_id, 0, 0);
2607 break;
2608 case PORT_IN_RESET:
2609 PM8001_MSG_DBG(pm8001_ha,
2610 pm8001_printk(" Port In Reset portID %d\n", port_id));
2611 break;
2612 case PORT_NOT_ESTABLISHED:
2613 PM8001_MSG_DBG(pm8001_ha,
2614 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2615 port->port_attached = 0;
2616 break;
2617 case PORT_LOSTCOMM:
2618 PM8001_MSG_DBG(pm8001_ha,
2619 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2620 PM8001_MSG_DBG(pm8001_ha,
2621 pm8001_printk(" Last phy Down and port invalid\n"));
2622 port->port_attached = 0;
2623 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2624 port_id, phy_id, 0, 0);
2625 break;
2626 default:
2627 port->port_attached = 0;
2628 PM8001_MSG_DBG(pm8001_ha,
2629 pm8001_printk(" phy Down and(default) = 0x%x\n",
2630 portstate));
2631 break;
2632
2633 }
2634}
2635
2636static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2637{
2638 struct phy_start_resp *pPayload =
2639 (struct phy_start_resp *)(piomb + 4);
2640 u32 status =
2641 le32_to_cpu(pPayload->status);
2642 u32 phy_id =
2643 le32_to_cpu(pPayload->phyid);
2644 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2645
2646 PM8001_INIT_DBG(pm8001_ha,
2647 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2648 status, phy_id));
2649 if (status == 0) {
2650 phy->phy_state = 1;
2651 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2652 complete(phy->enable_completion);
2653 }
2654 return 0;
2655
2656}
2657
2658/**
2659 * mpi_thermal_hw_event -The hw event has come.
2660 * @pm8001_ha: our hba card information
2661 * @piomb: IO message buffer
2662 */
2663static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2664{
2665 struct thermal_hw_event *pPayload =
2666 (struct thermal_hw_event *)(piomb + 4);
2667
2668 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2669 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2670
2671 if (thermal_event & 0x40) {
2672 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2673 "Thermal Event: Local high temperature violated!\n"));
2674 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2675 "Thermal Event: Measured local high temperature %d\n",
2676 ((rht_lht & 0xFF00) >> 8)));
2677 }
2678 if (thermal_event & 0x10) {
2679 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2680 "Thermal Event: Remote high temperature violated!\n"));
2681 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2682 "Thermal Event: Measured remote high temperature %d\n",
2683 ((rht_lht & 0xFF000000) >> 24)));
2684 }
2685 return 0;
2686}
2687
2688/**
2689 * mpi_hw_event -The hw event has come.
2690 * @pm8001_ha: our hba card information
2691 * @piomb: IO message buffer
2692 */
2693static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2694{
2695 unsigned long flags;
2696 struct hw_event_resp *pPayload =
2697 (struct hw_event_resp *)(piomb + 4);
2698 u32 lr_status_evt_portid =
2699 le32_to_cpu(pPayload->lr_status_evt_portid);
2700 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2701 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2702 u8 phy_id =
2703 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2704 u16 eventType =
2705 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2706 u8 status =
2707 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2708
2709 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2710 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2711 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2712 PM8001_MSG_DBG(pm8001_ha,
2713 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2714 port_id, phy_id, eventType, status));
2715
2716 switch (eventType) {
2717
2718 case HW_EVENT_SAS_PHY_UP:
2719 PM8001_MSG_DBG(pm8001_ha,
2720 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2721 hw_event_sas_phy_up(pm8001_ha, piomb);
2722 break;
2723 case HW_EVENT_SATA_PHY_UP:
2724 PM8001_MSG_DBG(pm8001_ha,
2725 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2726 hw_event_sata_phy_up(pm8001_ha, piomb);
2727 break;
2728 case HW_EVENT_SATA_SPINUP_HOLD:
2729 PM8001_MSG_DBG(pm8001_ha,
2730 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2731 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2732 break;
2733 case HW_EVENT_PHY_DOWN:
2734 PM8001_MSG_DBG(pm8001_ha,
2735 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2736 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2737 phy->phy_attached = 0;
2738 phy->phy_state = 0;
2739 hw_event_phy_down(pm8001_ha, piomb);
2740 break;
2741 case HW_EVENT_PORT_INVALID:
2742 PM8001_MSG_DBG(pm8001_ha,
2743 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2744 sas_phy_disconnected(sas_phy);
2745 phy->phy_attached = 0;
2746 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2747 break;
2748 /* the broadcast change primitive received, tell the LIBSAS this event
2749 to revalidate the sas domain*/
2750 case HW_EVENT_BROADCAST_CHANGE:
2751 PM8001_MSG_DBG(pm8001_ha,
2752 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2753 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2754 port_id, phy_id, 1, 0);
2755 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2756 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2757 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2758 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2759 break;
2760 case HW_EVENT_PHY_ERROR:
2761 PM8001_MSG_DBG(pm8001_ha,
2762 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2763 sas_phy_disconnected(&phy->sas_phy);
2764 phy->phy_attached = 0;
2765 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2766 break;
2767 case HW_EVENT_BROADCAST_EXP:
2768 PM8001_MSG_DBG(pm8001_ha,
2769 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2770 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2771 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2772 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2773 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2774 break;
2775 case HW_EVENT_LINK_ERR_INVALID_DWORD:
2776 PM8001_MSG_DBG(pm8001_ha,
2777 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2778 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2779 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2780 sas_phy_disconnected(sas_phy);
2781 phy->phy_attached = 0;
2782 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2783 break;
2784 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2785 PM8001_MSG_DBG(pm8001_ha,
2786 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2787 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2788 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2789 port_id, phy_id, 0, 0);
2790 sas_phy_disconnected(sas_phy);
2791 phy->phy_attached = 0;
2792 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2793 break;
2794 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2795 PM8001_MSG_DBG(pm8001_ha,
2796 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
2797 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2798 HW_EVENT_LINK_ERR_CODE_VIOLATION,
2799 port_id, phy_id, 0, 0);
2800 sas_phy_disconnected(sas_phy);
2801 phy->phy_attached = 0;
2802 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2803 break;
2804 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
2805 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2806 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
2807 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2808 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
2809 port_id, phy_id, 0, 0);
2810 sas_phy_disconnected(sas_phy);
2811 phy->phy_attached = 0;
2812 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2813 break;
2814 case HW_EVENT_MALFUNCTION:
2815 PM8001_MSG_DBG(pm8001_ha,
2816 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
2817 break;
2818 case HW_EVENT_BROADCAST_SES:
2819 PM8001_MSG_DBG(pm8001_ha,
2820 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
2821 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2822 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
2823 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2824 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2825 break;
2826 case HW_EVENT_INBOUND_CRC_ERROR:
2827 PM8001_MSG_DBG(pm8001_ha,
2828 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
2829 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2830 HW_EVENT_INBOUND_CRC_ERROR,
2831 port_id, phy_id, 0, 0);
2832 break;
2833 case HW_EVENT_HARD_RESET_RECEIVED:
2834 PM8001_MSG_DBG(pm8001_ha,
2835 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
2836 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
2837 break;
2838 case HW_EVENT_ID_FRAME_TIMEOUT:
2839 PM8001_MSG_DBG(pm8001_ha,
2840 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
2841 sas_phy_disconnected(sas_phy);
2842 phy->phy_attached = 0;
2843 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2844 break;
2845 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
2846 PM8001_MSG_DBG(pm8001_ha,
2847 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
2848 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2849 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
2850 port_id, phy_id, 0, 0);
2851 sas_phy_disconnected(sas_phy);
2852 phy->phy_attached = 0;
2853 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2854 break;
2855 case HW_EVENT_PORT_RESET_TIMER_TMO:
2856 PM8001_MSG_DBG(pm8001_ha,
2857 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
2858 sas_phy_disconnected(sas_phy);
2859 phy->phy_attached = 0;
2860 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2861 break;
2862 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
2863 PM8001_MSG_DBG(pm8001_ha,
2864 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
2865 sas_phy_disconnected(sas_phy);
2866 phy->phy_attached = 0;
2867 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2868 break;
2869 case HW_EVENT_PORT_RECOVER:
2870 PM8001_MSG_DBG(pm8001_ha,
2871 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
2872 break;
2873 case HW_EVENT_PORT_RESET_COMPLETE:
2874 PM8001_MSG_DBG(pm8001_ha,
2875 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
2876 break;
2877 case EVENT_BROADCAST_ASYNCH_EVENT:
2878 PM8001_MSG_DBG(pm8001_ha,
2879 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
2880 break;
2881 default:
2882 PM8001_MSG_DBG(pm8001_ha,
2883 pm8001_printk("Unknown event type 0x%x\n", eventType));
2884 break;
2885 }
2886 return 0;
2887}
2888
2889/**
2890 * mpi_phy_stop_resp - SPCv specific
2891 * @pm8001_ha: our hba card information
2892 * @piomb: IO message buffer
2893 */
2894static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2895{
2896 struct phy_stop_resp *pPayload =
2897 (struct phy_stop_resp *)(piomb + 4);
2898 u32 status =
2899 le32_to_cpu(pPayload->status);
2900 u32 phyid =
2901 le32_to_cpu(pPayload->phyid);
2902 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
2903 PM8001_MSG_DBG(pm8001_ha,
2904 pm8001_printk("phy:0x%x status:0x%x\n",
2905 phyid, status));
2906 if (status == 0)
2907 phy->phy_state = 0;
2908 return 0;
2909}
2910
2911/**
2912 * mpi_set_controller_config_resp - SPCv specific
2913 * @pm8001_ha: our hba card information
2914 * @piomb: IO message buffer
2915 */
2916static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
2917 void *piomb)
2918{
2919 struct set_ctrl_cfg_resp *pPayload =
2920 (struct set_ctrl_cfg_resp *)(piomb + 4);
2921 u32 status = le32_to_cpu(pPayload->status);
2922 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
2923
2924 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2925 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
2926 status, err_qlfr_pgcd));
2927
2928 return 0;
2929}
2930
2931/**
2932 * mpi_get_controller_config_resp - SPCv specific
2933 * @pm8001_ha: our hba card information
2934 * @piomb: IO message buffer
2935 */
2936static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
2937 void *piomb)
2938{
2939 PM8001_MSG_DBG(pm8001_ha,
2940 pm8001_printk(" pm80xx_addition_functionality\n"));
2941
2942 return 0;
2943}
2944
2945/**
2946 * mpi_get_phy_profile_resp - SPCv specific
2947 * @pm8001_ha: our hba card information
2948 * @piomb: IO message buffer
2949 */
2950static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
2951 void *piomb)
2952{
2953 PM8001_MSG_DBG(pm8001_ha,
2954 pm8001_printk(" pm80xx_addition_functionality\n"));
2955
2956 return 0;
2957}
2958
2959/**
2960 * mpi_flash_op_ext_resp - SPCv specific
2961 * @pm8001_ha: our hba card information
2962 * @piomb: IO message buffer
2963 */
2964static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2965{
2966 PM8001_MSG_DBG(pm8001_ha,
2967 pm8001_printk(" pm80xx_addition_functionality\n"));
2968
2969 return 0;
2970}
2971
2972/**
2973 * mpi_set_phy_profile_resp - SPCv specific
2974 * @pm8001_ha: our hba card information
2975 * @piomb: IO message buffer
2976 */
2977static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
2978 void *piomb)
2979{
2980 PM8001_MSG_DBG(pm8001_ha,
2981 pm8001_printk(" pm80xx_addition_functionality\n"));
2982
2983 return 0;
2984}
2985
2986/**
2987 * mpi_kek_management_resp - SPCv specific
2988 * @pm8001_ha: our hba card information
2989 * @piomb: IO message buffer
2990 */
2991static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
2992 void *piomb)
2993{
2994 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
2995
2996 u32 status = le32_to_cpu(pPayload->status);
2997 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
2998 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
2999
3000 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3001 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3002 status, kidx_new_curr_ksop, err_qlfr));
3003
3004 return 0;
3005}
3006
3007/**
3008 * mpi_dek_management_resp - SPCv specific
3009 * @pm8001_ha: our hba card information
3010 * @piomb: IO message buffer
3011 */
3012static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3013 void *piomb)
3014{
3015 PM8001_MSG_DBG(pm8001_ha,
3016 pm8001_printk(" pm80xx_addition_functionality\n"));
3017
3018 return 0;
3019}
3020
3021/**
3022 * ssp_coalesced_comp_resp - SPCv specific
3023 * @pm8001_ha: our hba card information
3024 * @piomb: IO message buffer
3025 */
3026static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3027 void *piomb)
3028{
3029 PM8001_MSG_DBG(pm8001_ha,
3030 pm8001_printk(" pm80xx_addition_functionality\n"));
3031
3032 return 0;
3033}
3034
3035/**
3036 * process_one_iomb - process one outbound Queue memory block
3037 * @pm8001_ha: our hba card information
3038 * @piomb: IO message buffer
3039 */
3040static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3041{
3042 __le32 pHeader = *(__le32 *)piomb;
3043 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3044
3045 switch (opc) {
3046 case OPC_OUB_ECHO:
3047 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3048 break;
3049 case OPC_OUB_HW_EVENT:
3050 PM8001_MSG_DBG(pm8001_ha,
3051 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3052 mpi_hw_event(pm8001_ha, piomb);
3053 break;
3054 case OPC_OUB_THERM_HW_EVENT:
3055 PM8001_MSG_DBG(pm8001_ha,
3056 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3057 mpi_thermal_hw_event(pm8001_ha, piomb);
3058 break;
3059 case OPC_OUB_SSP_COMP:
3060 PM8001_MSG_DBG(pm8001_ha,
3061 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3062 mpi_ssp_completion(pm8001_ha, piomb);
3063 break;
3064 case OPC_OUB_SMP_COMP:
3065 PM8001_MSG_DBG(pm8001_ha,
3066 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3067 mpi_smp_completion(pm8001_ha, piomb);
3068 break;
3069 case OPC_OUB_LOCAL_PHY_CNTRL:
3070 PM8001_MSG_DBG(pm8001_ha,
3071 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3072 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3073 break;
3074 case OPC_OUB_DEV_REGIST:
3075 PM8001_MSG_DBG(pm8001_ha,
3076 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3077 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3078 break;
3079 case OPC_OUB_DEREG_DEV:
3080 PM8001_MSG_DBG(pm8001_ha,
3081 pm8001_printk("unresgister the deviece\n"));
3082 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3083 break;
3084 case OPC_OUB_GET_DEV_HANDLE:
3085 PM8001_MSG_DBG(pm8001_ha,
3086 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3087 break;
3088 case OPC_OUB_SATA_COMP:
3089 PM8001_MSG_DBG(pm8001_ha,
3090 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3091 mpi_sata_completion(pm8001_ha, piomb);
3092 break;
3093 case OPC_OUB_SATA_EVENT:
3094 PM8001_MSG_DBG(pm8001_ha,
3095 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3096 mpi_sata_event(pm8001_ha, piomb);
3097 break;
3098 case OPC_OUB_SSP_EVENT:
3099 PM8001_MSG_DBG(pm8001_ha,
3100 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3101 mpi_ssp_event(pm8001_ha, piomb);
3102 break;
3103 case OPC_OUB_DEV_HANDLE_ARRIV:
3104 PM8001_MSG_DBG(pm8001_ha,
3105 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3106 /*This is for target*/
3107 break;
3108 case OPC_OUB_SSP_RECV_EVENT:
3109 PM8001_MSG_DBG(pm8001_ha,
3110 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3111 /*This is for target*/
3112 break;
3113 case OPC_OUB_FW_FLASH_UPDATE:
3114 PM8001_MSG_DBG(pm8001_ha,
3115 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3116 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3117 break;
3118 case OPC_OUB_GPIO_RESPONSE:
3119 PM8001_MSG_DBG(pm8001_ha,
3120 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3121 break;
3122 case OPC_OUB_GPIO_EVENT:
3123 PM8001_MSG_DBG(pm8001_ha,
3124 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3125 break;
3126 case OPC_OUB_GENERAL_EVENT:
3127 PM8001_MSG_DBG(pm8001_ha,
3128 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3129 pm8001_mpi_general_event(pm8001_ha, piomb);
3130 break;
3131 case OPC_OUB_SSP_ABORT_RSP:
3132 PM8001_MSG_DBG(pm8001_ha,
3133 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3134 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3135 break;
3136 case OPC_OUB_SATA_ABORT_RSP:
3137 PM8001_MSG_DBG(pm8001_ha,
3138 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3139 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3140 break;
3141 case OPC_OUB_SAS_DIAG_MODE_START_END:
3142 PM8001_MSG_DBG(pm8001_ha,
3143 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3144 break;
3145 case OPC_OUB_SAS_DIAG_EXECUTE:
3146 PM8001_MSG_DBG(pm8001_ha,
3147 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3148 break;
3149 case OPC_OUB_GET_TIME_STAMP:
3150 PM8001_MSG_DBG(pm8001_ha,
3151 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3152 break;
3153 case OPC_OUB_SAS_HW_EVENT_ACK:
3154 PM8001_MSG_DBG(pm8001_ha,
3155 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3156 break;
3157 case OPC_OUB_PORT_CONTROL:
3158 PM8001_MSG_DBG(pm8001_ha,
3159 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3160 break;
3161 case OPC_OUB_SMP_ABORT_RSP:
3162 PM8001_MSG_DBG(pm8001_ha,
3163 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3164 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3165 break;
3166 case OPC_OUB_GET_NVMD_DATA:
3167 PM8001_MSG_DBG(pm8001_ha,
3168 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3169 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3170 break;
3171 case OPC_OUB_SET_NVMD_DATA:
3172 PM8001_MSG_DBG(pm8001_ha,
3173 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3174 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3175 break;
3176 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3177 PM8001_MSG_DBG(pm8001_ha,
3178 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3179 break;
3180 case OPC_OUB_SET_DEVICE_STATE:
3181 PM8001_MSG_DBG(pm8001_ha,
3182 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3183 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3184 break;
3185 case OPC_OUB_GET_DEVICE_STATE:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3188 break;
3189 case OPC_OUB_SET_DEV_INFO:
3190 PM8001_MSG_DBG(pm8001_ha,
3191 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3192 break;
3193 /* spcv specifc commands */
3194 case OPC_OUB_PHY_START_RESP:
3195 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3196 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3197 mpi_phy_start_resp(pm8001_ha, piomb);
3198 break;
3199 case OPC_OUB_PHY_STOP_RESP:
3200 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3201 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3202 mpi_phy_stop_resp(pm8001_ha, piomb);
3203 break;
3204 case OPC_OUB_SET_CONTROLLER_CONFIG:
3205 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3206 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3207 mpi_set_controller_config_resp(pm8001_ha, piomb);
3208 break;
3209 case OPC_OUB_GET_CONTROLLER_CONFIG:
3210 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3211 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3212 mpi_get_controller_config_resp(pm8001_ha, piomb);
3213 break;
3214 case OPC_OUB_GET_PHY_PROFILE:
3215 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3216 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3217 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3218 break;
3219 case OPC_OUB_FLASH_OP_EXT:
3220 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3221 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3222 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3223 break;
3224 case OPC_OUB_SET_PHY_PROFILE:
3225 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3226 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3227 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3228 break;
3229 case OPC_OUB_KEK_MANAGEMENT_RESP:
3230 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3231 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3232 mpi_kek_management_resp(pm8001_ha, piomb);
3233 break;
3234 case OPC_OUB_DEK_MANAGEMENT_RESP:
3235 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3236 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3237 mpi_dek_management_resp(pm8001_ha, piomb);
3238 break;
3239 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3240 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3241 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3242 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3243 break;
3244 default:
3245 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3246 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3247 break;
3248 }
3249}
3250
3251static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3252{
3253 struct outbound_queue_table *circularQ;
3254 void *pMsg1 = NULL;
3255 u8 uninitialized_var(bc);
3256 u32 ret = MPI_IO_STATUS_FAIL;
3257 unsigned long flags;
3258
3259 spin_lock_irqsave(&pm8001_ha->lock, flags);
3260 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3261 do {
3262 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3263 if (MPI_IO_STATUS_SUCCESS == ret) {
3264 /* process the outbound message */
3265 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3266 /* free the message from the outbound circular buffer */
3267 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3268 circularQ, bc);
3269 }
3270 if (MPI_IO_STATUS_BUSY == ret) {
3271 /* Update the producer index from SPC */
3272 circularQ->producer_index =
3273 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3274 if (le32_to_cpu(circularQ->producer_index) ==
3275 circularQ->consumer_idx)
3276 /* OQ is empty */
3277 break;
3278 }
3279 } while (1);
3280 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3281 return ret;
3282}
3283
3284/* PCI_DMA_... to our direction translation. */
3285static const u8 data_dir_flags[] = {
3286 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3287 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3288 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3289 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3290};
3291
3292static void build_smp_cmd(u32 deviceID, __le32 hTag,
3293 struct smp_req *psmp_cmd, int mode, int length)
3294{
3295 psmp_cmd->tag = hTag;
3296 psmp_cmd->device_id = cpu_to_le32(deviceID);
3297 if (mode == SMP_DIRECT) {
3298 length = length - 4; /* subtract crc */
3299 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3300 } else {
3301 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3302 }
3303}
3304
3305/**
3306 * pm8001_chip_smp_req - send a SMP task to FW
3307 * @pm8001_ha: our hba card information.
3308 * @ccb: the ccb information this request used.
3309 */
3310static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3311 struct pm8001_ccb_info *ccb)
3312{
3313 int elem, rc;
3314 struct sas_task *task = ccb->task;
3315 struct domain_device *dev = task->dev;
3316 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3317 struct scatterlist *sg_req, *sg_resp;
3318 u32 req_len, resp_len;
3319 struct smp_req smp_cmd;
3320 u32 opc;
3321 struct inbound_queue_table *circularQ;
3322 char *preq_dma_addr = NULL;
3323 __le64 tmp_addr;
3324 u32 i, length;
3325
3326 memset(&smp_cmd, 0, sizeof(smp_cmd));
3327 /*
3328 * DMA-map SMP request, response buffers
3329 */
3330 sg_req = &task->smp_task.smp_req;
3331 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3332 if (!elem)
3333 return -ENOMEM;
3334 req_len = sg_dma_len(sg_req);
3335
3336 sg_resp = &task->smp_task.smp_resp;
3337 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3338 if (!elem) {
3339 rc = -ENOMEM;
3340 goto err_out;
3341 }
3342 resp_len = sg_dma_len(sg_resp);
3343 /* must be in dwords */
3344 if ((req_len & 0x3) || (resp_len & 0x3)) {
3345 rc = -EINVAL;
3346 goto err_out_2;
3347 }
3348
3349 opc = OPC_INB_SMP_REQUEST;
3350 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3351 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3352
3353 length = sg_req->length;
3354 PM8001_IO_DBG(pm8001_ha,
3355 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3356 if (!(length - 8))
3357 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3358 else
3359 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3360
3361 /* DIRECT MODE support only in spcv/ve */
3362 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3363
3364 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3365 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3366
3367 /* INDIRECT MODE command settings. Use DMA */
3368 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3369 PM8001_IO_DBG(pm8001_ha,
3370 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3371 /* for SPCv indirect mode. Place the top 4 bytes of
3372 * SMP Request header here. */
3373 for (i = 0; i < 4; i++)
3374 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3375 /* exclude top 4 bytes for SMP req header */
3376 smp_cmd.long_smp_req.long_req_addr =
3377 cpu_to_le64((u64)sg_dma_address
3378 (&task->smp_task.smp_req) - 4);
3379 /* exclude 4 bytes for SMP req header and CRC */
3380 smp_cmd.long_smp_req.long_req_size =
3381 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3382 smp_cmd.long_smp_req.long_resp_addr =
3383 cpu_to_le64((u64)sg_dma_address
3384 (&task->smp_task.smp_resp));
3385 smp_cmd.long_smp_req.long_resp_size =
3386 cpu_to_le32((u32)sg_dma_len
3387 (&task->smp_task.smp_resp)-4);
3388 } else { /* DIRECT MODE */
3389 smp_cmd.long_smp_req.long_req_addr =
3390 cpu_to_le64((u64)sg_dma_address
3391 (&task->smp_task.smp_req));
3392 smp_cmd.long_smp_req.long_req_size =
3393 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3394 smp_cmd.long_smp_req.long_resp_addr =
3395 cpu_to_le64((u64)sg_dma_address
3396 (&task->smp_task.smp_resp));
3397 smp_cmd.long_smp_req.long_resp_size =
3398 cpu_to_le32
3399 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3400 }
3401 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3402 PM8001_IO_DBG(pm8001_ha,
3403 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3404 for (i = 0; i < length; i++)
3405 if (i < 16) {
3406 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3407 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3408 "Byte[%d]:%x (DMA data:%x)\n",
3409 i, smp_cmd.smp_req16[i],
3410 *(preq_dma_addr)));
3411 } else {
3412 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3413 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3414 "Byte[%d]:%x (DMA data:%x)\n",
3415 i, smp_cmd.smp_req[i],
3416 *(preq_dma_addr)));
3417 }
3418 }
3419
3420 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3421 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3422 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3423 return 0;
3424
3425err_out_2:
3426 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3427 PCI_DMA_FROMDEVICE);
3428err_out:
3429 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3430 PCI_DMA_TODEVICE);
3431 return rc;
3432}
3433
3434static int check_enc_sas_cmd(struct sas_task *task)
3435{
3436 if ((task->ssp_task.cdb[0] == READ_10)
3437 || (task->ssp_task.cdb[0] == WRITE_10)
3438 || (task->ssp_task.cdb[0] == WRITE_VERIFY))
3439 return 1;
3440 else
3441 return 0;
3442}
3443
3444static int check_enc_sat_cmd(struct sas_task *task)
3445{
3446 int ret = 0;
3447 switch (task->ata_task.fis.command) {
3448 case ATA_CMD_FPDMA_READ:
3449 case ATA_CMD_READ_EXT:
3450 case ATA_CMD_READ:
3451 case ATA_CMD_FPDMA_WRITE:
3452 case ATA_CMD_WRITE_EXT:
3453 case ATA_CMD_WRITE:
3454 case ATA_CMD_PIO_READ:
3455 case ATA_CMD_PIO_READ_EXT:
3456 case ATA_CMD_PIO_WRITE:
3457 case ATA_CMD_PIO_WRITE_EXT:
3458 ret = 1;
3459 break;
3460 default:
3461 ret = 0;
3462 break;
3463 }
3464 return ret;
3465}
3466
3467/**
3468 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3469 * @pm8001_ha: our hba card information.
3470 * @ccb: the ccb information this request used.
3471 */
3472static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3473 struct pm8001_ccb_info *ccb)
3474{
3475 struct sas_task *task = ccb->task;
3476 struct domain_device *dev = task->dev;
3477 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3478 struct ssp_ini_io_start_req ssp_cmd;
3479 u32 tag = ccb->ccb_tag;
3480 int ret;
3481 u64 phys_addr;
3482 struct inbound_queue_table *circularQ;
3483 static u32 inb;
3484 static u32 outb;
3485 u32 opc = OPC_INB_SSPINIIOSTART;
3486 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3487 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3488 /* data address domain added for spcv; set to 0 by host,
3489 * used internally by controller
3490 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3491 */
3492 ssp_cmd.dad_dir_m_tlr =
3493 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3494 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3495 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3496 ssp_cmd.tag = cpu_to_le32(tag);
3497 if (task->ssp_task.enable_first_burst)
3498 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3499 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3500 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3501 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3502 circularQ = &pm8001_ha->inbnd_q_tbl[inb++];
3503
3504 /* rotate the inb queue */
3505 inb = inb%PM8001_MAX_SPCV_INB_NUM;
3506
3507 /* Check if encryption is set */
3508 if (pm8001_ha->chip->encrypt &&
3509 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3510 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3511 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3512 task->ssp_task.cdb[0]));
3513 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3514 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3515 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3516 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3517
3518 /* fill in PRD (scatter/gather) table, if any */
3519 if (task->num_scatter > 1) {
3520 pm8001_chip_make_sg(task->scatter,
3521 ccb->n_elem, ccb->buf_prd);
3522 phys_addr = ccb->ccb_dma_handle +
3523 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3524 ssp_cmd.enc_addr_low =
3525 cpu_to_le32(lower_32_bits(phys_addr));
3526 ssp_cmd.enc_addr_high =
3527 cpu_to_le32(upper_32_bits(phys_addr));
3528 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3529 } else if (task->num_scatter == 1) {
3530 u64 dma_addr = sg_dma_address(task->scatter);
3531 ssp_cmd.enc_addr_low =
3532 cpu_to_le32(lower_32_bits(dma_addr));
3533 ssp_cmd.enc_addr_high =
3534 cpu_to_le32(upper_32_bits(dma_addr));
3535 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3536 ssp_cmd.enc_esgl = 0;
3537 } else if (task->num_scatter == 0) {
3538 ssp_cmd.enc_addr_low = 0;
3539 ssp_cmd.enc_addr_high = 0;
3540 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3541 ssp_cmd.enc_esgl = 0;
3542 }
3543 /* XTS mode. All other fields are 0 */
3544 ssp_cmd.key_cmode = 0x6 << 4;
3545 /* set tweak values. Should be the start lba */
3546 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cdb[2] << 24) |
3547 (task->ssp_task.cdb[3] << 16) |
3548 (task->ssp_task.cdb[4] << 8) |
3549 (task->ssp_task.cdb[5]));
3550 } else {
3551 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3552 "Sending Normal SAS command 0x%x inb q %x\n",
3553 task->ssp_task.cdb[0], inb));
3554 /* fill in PRD (scatter/gather) table, if any */
3555 if (task->num_scatter > 1) {
3556 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3557 ccb->buf_prd);
3558 phys_addr = ccb->ccb_dma_handle +
3559 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3560 ssp_cmd.addr_low =
3561 cpu_to_le32(lower_32_bits(phys_addr));
3562 ssp_cmd.addr_high =
3563 cpu_to_le32(upper_32_bits(phys_addr));
3564 ssp_cmd.esgl = cpu_to_le32(1<<31);
3565 } else if (task->num_scatter == 1) {
3566 u64 dma_addr = sg_dma_address(task->scatter);
3567 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3568 ssp_cmd.addr_high =
3569 cpu_to_le32(upper_32_bits(dma_addr));
3570 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3571 ssp_cmd.esgl = 0;
3572 } else if (task->num_scatter == 0) {
3573 ssp_cmd.addr_low = 0;
3574 ssp_cmd.addr_high = 0;
3575 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3576 ssp_cmd.esgl = 0;
3577 }
3578 }
3579 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, outb++);
3580
3581 /* rotate the outb queue */
3582 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3583
3584 return ret;
3585}
3586
3587static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3588 struct pm8001_ccb_info *ccb)
3589{
3590 struct sas_task *task = ccb->task;
3591 struct domain_device *dev = task->dev;
3592 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3593 u32 tag = ccb->ccb_tag;
3594 int ret;
3595 static u32 inb;
3596 static u32 outb;
3597 struct sata_start_req sata_cmd;
3598 u32 hdr_tag, ncg_tag = 0;
3599 u64 phys_addr;
3600 u32 ATAP = 0x0;
3601 u32 dir;
3602 struct inbound_queue_table *circularQ;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]3603 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3604 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3605 memset(&sata_cmd, 0, sizeof(sata_cmd));
3606 circularQ = &pm8001_ha->inbnd_q_tbl[inb++];
3607
3608 /* rotate the inb queue */
3609 inb = inb%PM8001_MAX_SPCV_INB_NUM;
3610
3611 if (task->data_dir == PCI_DMA_NONE) {
3612 ATAP = 0x04; /* no data*/
3613 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3614 } else if (likely(!task->ata_task.device_control_reg_update)) {
3615 if (task->ata_task.dma_xfer) {
3616 ATAP = 0x06; /* DMA */
3617 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3618 } else {
3619 ATAP = 0x05; /* PIO*/
3620 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3621 }
3622 if (task->ata_task.use_ncq &&
3623 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3624 ATAP = 0x07; /* FPDMA */
3625 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3626 }
3627 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]3628 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
3629 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3630 ncg_tag = hdr_tag;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]3631 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3632 dir = data_dir_flags[task->data_dir] << 8;
3633 sata_cmd.tag = cpu_to_le32(tag);
3634 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3635 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3636
3637 sata_cmd.sata_fis = task->ata_task.fis;
3638 if (likely(!task->ata_task.device_control_reg_update))
3639 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3640 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3641
3642 /* Check if encryption is set */
3643 if (pm8001_ha->chip->encrypt &&
3644 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3645 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3646 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3647 sata_cmd.sata_fis.command));
3648 opc = OPC_INB_SATA_DIF_ENC_IO;
3649
3650 /* set encryption bit */
3651 sata_cmd.ncqtag_atap_dir_m_dad =
3652 cpu_to_le32(((ncg_tag & 0xff)<<16)|
3653 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3654 /* dad (bit 0-1) is 0 */
3655 /* fill in PRD (scatter/gather) table, if any */
3656 if (task->num_scatter > 1) {
3657 pm8001_chip_make_sg(task->scatter,
3658 ccb->n_elem, ccb->buf_prd);
3659 phys_addr = ccb->ccb_dma_handle +
3660 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3661 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3662 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3663 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3664 } else if (task->num_scatter == 1) {
3665 u64 dma_addr = sg_dma_address(task->scatter);
3666 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3667 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3668 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3669 sata_cmd.enc_esgl = 0;
3670 } else if (task->num_scatter == 0) {
3671 sata_cmd.enc_addr_low = 0;
3672 sata_cmd.enc_addr_high = 0;
3673 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3674 sata_cmd.enc_esgl = 0;
3675 }
3676 /* XTS mode. All other fields are 0 */
3677 sata_cmd.key_index_mode = 0x6 << 4;
3678 /* set tweak values. Should be the start lba */
3679 sata_cmd.twk_val0 =
3680 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3681 (sata_cmd.sata_fis.lbah << 16) |
3682 (sata_cmd.sata_fis.lbam << 8) |
3683 (sata_cmd.sata_fis.lbal));
3684 sata_cmd.twk_val1 =
3685 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3686 (sata_cmd.sata_fis.lbam_exp));
3687 } else {
3688 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3689 "Sending Normal SATA command 0x%x inb %x\n",
3690 sata_cmd.sata_fis.command, inb));
3691 /* dad (bit 0-1) is 0 */
3692 sata_cmd.ncqtag_atap_dir_m_dad =
3693 cpu_to_le32(((ncg_tag & 0xff)<<16) |
3694 ((ATAP & 0x3f) << 10) | dir);
3695
3696 /* fill in PRD (scatter/gather) table, if any */
3697 if (task->num_scatter > 1) {
3698 pm8001_chip_make_sg(task->scatter,
3699 ccb->n_elem, ccb->buf_prd);
3700 phys_addr = ccb->ccb_dma_handle +
3701 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3702 sata_cmd.addr_low = lower_32_bits(phys_addr);
3703 sata_cmd.addr_high = upper_32_bits(phys_addr);
3704 sata_cmd.esgl = cpu_to_le32(1 << 31);
3705 } else if (task->num_scatter == 1) {
3706 u64 dma_addr = sg_dma_address(task->scatter);
3707 sata_cmd.addr_low = lower_32_bits(dma_addr);
3708 sata_cmd.addr_high = upper_32_bits(dma_addr);
3709 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3710 sata_cmd.esgl = 0;
3711 } else if (task->num_scatter == 0) {
3712 sata_cmd.addr_low = 0;
3713 sata_cmd.addr_high = 0;
3714 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3715 sata_cmd.esgl = 0;
3716 }
3717 /* scsi cdb */
3718 sata_cmd.atapi_scsi_cdb[0] =
3719 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
3720 (task->ata_task.atapi_packet[1] << 8) |
3721 (task->ata_task.atapi_packet[2] << 16) |
3722 (task->ata_task.atapi_packet[3] << 24)));
3723 sata_cmd.atapi_scsi_cdb[1] =
3724 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
3725 (task->ata_task.atapi_packet[5] << 8) |
3726 (task->ata_task.atapi_packet[6] << 16) |
3727 (task->ata_task.atapi_packet[7] << 24)));
3728 sata_cmd.atapi_scsi_cdb[2] =
3729 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
3730 (task->ata_task.atapi_packet[9] << 8) |
3731 (task->ata_task.atapi_packet[10] << 16) |
3732 (task->ata_task.atapi_packet[11] << 24)));
3733 sata_cmd.atapi_scsi_cdb[3] =
3734 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
3735 (task->ata_task.atapi_packet[13] << 8) |
3736 (task->ata_task.atapi_packet[14] << 16) |
3737 (task->ata_task.atapi_packet[15] << 24)));
3738 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame^]3739
3740 /* Check for read log for failed drive and return */
3741 if (sata_cmd.sata_fis.command == 0x2f) {
3742 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
3743 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
3744 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
3745 struct task_status_struct *ts;
3746
3747 pm8001_ha_dev->id &= 0xDFFFFFFF;
3748 ts = &task->task_status;
3749
3750 spin_lock_irqsave(&task->task_state_lock, flags);
3751 ts->resp = SAS_TASK_COMPLETE;
3752 ts->stat = SAM_STAT_GOOD;
3753 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3754 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3755 task->task_state_flags |= SAS_TASK_STATE_DONE;
3756 if (unlikely((task->task_state_flags &
3757 SAS_TASK_STATE_ABORTED))) {
3758 spin_unlock_irqrestore(&task->task_state_lock,
3759 flags);
3760 PM8001_FAIL_DBG(pm8001_ha,
3761 pm8001_printk("task 0x%p resp 0x%x "
3762 " stat 0x%x but aborted by upper layer "
3763 "\n", task, ts->resp, ts->stat));
3764 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3765 return 0;
3766 } else if (task->uldd_task) {
3767 spin_unlock_irqrestore(&task->task_state_lock,
3768 flags);
3769 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3770 mb();/* ditto */
3771 spin_unlock_irq(&pm8001_ha->lock);
3772 task->task_done(task);
3773 spin_lock_irq(&pm8001_ha->lock);
3774 return 0;
3775 } else if (!task->uldd_task) {
3776 spin_unlock_irqrestore(&task->task_state_lock,
3777 flags);
3778 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3779 mb();/*ditto*/
3780 spin_unlock_irq(&pm8001_ha->lock);
3781 task->task_done(task);
3782 spin_lock_irq(&pm8001_ha->lock);
3783 return 0;
3784 }
3785 }
3786 }
3787
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3788 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3789 &sata_cmd, outb++);
3790
3791 /* rotate the outb queue */
3792 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3793 return ret;
3794}
3795
3796/**
3797 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
3798 * @pm8001_ha: our hba card information.
3799 * @num: the inbound queue number
3800 * @phy_id: the phy id which we wanted to start up.
3801 */
3802static int
3803pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3804{
3805 struct phy_start_req payload;
3806 struct inbound_queue_table *circularQ;
3807 int ret;
3808 u32 tag = 0x01;
3809 u32 opcode = OPC_INB_PHYSTART;
3810 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3811 memset(&payload, 0, sizeof(payload));
3812 payload.tag = cpu_to_le32(tag);
3813
3814 PM8001_INIT_DBG(pm8001_ha,
3815 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
3816 /*
3817 ** [0:7] PHY Identifier
3818 ** [8:11] link rate 1.5G, 3G, 6G
3819 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
3820 ** [14] 0b disable spin up hold; 1b enable spin up hold
3821 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
3822 */
3823 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3824 LINKMODE_AUTO | LINKRATE_15 |
3825 LINKRATE_30 | LINKRATE_60 | phy_id);
3826 /* SSC Disable and SAS Analog ST configuration */
3827 /**
3828 payload.ase_sh_lm_slr_phyid =
3829 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
3830 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
3831 phy_id);
3832 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
3833 **/
3834
3835 payload.sas_identify.dev_type = SAS_END_DEV;
3836 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3837 memcpy(payload.sas_identify.sas_addr,
3838 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3839 payload.sas_identify.phy_id = phy_id;
3840 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3841 return ret;
3842}
3843
3844/**
3845 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3846 * @pm8001_ha: our hba card information.
3847 * @num: the inbound queue number
3848 * @phy_id: the phy id which we wanted to start up.
3849 */
3850static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3851 u8 phy_id)
3852{
3853 struct phy_stop_req payload;
3854 struct inbound_queue_table *circularQ;
3855 int ret;
3856 u32 tag = 0x01;
3857 u32 opcode = OPC_INB_PHYSTOP;
3858 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3859 memset(&payload, 0, sizeof(payload));
3860 payload.tag = cpu_to_le32(tag);
3861 payload.phy_id = cpu_to_le32(phy_id);
3862 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3863 return ret;
3864}
3865
3866/**
3867 * see comments on pm8001_mpi_reg_resp.
3868 */
3869static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3870 struct pm8001_device *pm8001_dev, u32 flag)
3871{
3872 struct reg_dev_req payload;
3873 u32 opc;
3874 u32 stp_sspsmp_sata = 0x4;
3875 struct inbound_queue_table *circularQ;
3876 u32 linkrate, phy_id;
3877 int rc, tag = 0xdeadbeef;
3878 struct pm8001_ccb_info *ccb;
3879 u8 retryFlag = 0x1;
3880 u16 firstBurstSize = 0;
3881 u16 ITNT = 2000;
3882 struct domain_device *dev = pm8001_dev->sas_device;
3883 struct domain_device *parent_dev = dev->parent;
3884 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3885
3886 memset(&payload, 0, sizeof(payload));
3887 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3888 if (rc)
3889 return rc;
3890 ccb = &pm8001_ha->ccb_info[tag];
3891 ccb->device = pm8001_dev;
3892 ccb->ccb_tag = tag;
3893 payload.tag = cpu_to_le32(tag);
3894
3895 if (flag == 1) {
3896 stp_sspsmp_sata = 0x02; /*direct attached sata */
3897 } else {
3898 if (pm8001_dev->dev_type == SATA_DEV)
3899 stp_sspsmp_sata = 0x00; /* stp*/
3900 else if (pm8001_dev->dev_type == SAS_END_DEV ||
3901 pm8001_dev->dev_type == EDGE_DEV ||
3902 pm8001_dev->dev_type == FANOUT_DEV)
3903 stp_sspsmp_sata = 0x01; /*ssp or smp*/
3904 }
3905 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
3906 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
3907 else
3908 phy_id = pm8001_dev->attached_phy;
3909
3910 opc = OPC_INB_REG_DEV;
3911
3912 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
3913 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
3914
3915 payload.phyid_portid =
3916 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
3917 ((phy_id & 0xFF) << 8));
3918
3919 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
3920 ((linkrate & 0x0F) << 24) |
3921 ((stp_sspsmp_sata & 0x03) << 28));
3922 payload.firstburstsize_ITNexustimeout =
3923 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
3924
3925 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
3926 SAS_ADDR_SIZE);
3927
3928 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3929
3930 return rc;
3931}
3932
3933/**
3934 * pm80xx_chip_phy_ctl_req - support the local phy operation
3935 * @pm8001_ha: our hba card information.
3936 * @num: the inbound queue number
3937 * @phy_id: the phy id which we wanted to operate
3938 * @phy_op:
3939 */
3940static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3941 u32 phyId, u32 phy_op)
3942{
3943 struct local_phy_ctl_req payload;
3944 struct inbound_queue_table *circularQ;
3945 int ret;
3946 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
3947 memset(&payload, 0, sizeof(payload));
3948 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3949 payload.tag = cpu_to_le32(1);
3950 payload.phyop_phyid =
3951 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
3952 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3953 return ret;
3954}
3955
3956static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
3957{
3958 u32 value;
3959#ifdef PM8001_USE_MSIX
3960 return 1;
3961#endif
3962 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
3963 if (value)
3964 return 1;
3965 return 0;
3966
3967}
3968
3969/**
3970 * pm8001_chip_isr - PM8001 isr handler.
3971 * @pm8001_ha: our hba card information.
3972 * @irq: irq number.
3973 * @stat: stat.
3974 */
3975static irqreturn_t
3976pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
3977{
3978 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
3979 process_oq(pm8001_ha, vec);
3980 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
3981 return IRQ_HANDLED;
3982}
3983
3984const struct pm8001_dispatch pm8001_80xx_dispatch = {
3985 .name = "pmc80xx",
3986 .chip_init = pm80xx_chip_init,
3987 .chip_soft_rst = pm80xx_chip_soft_rst,
3988 .chip_rst = pm80xx_hw_chip_rst,
3989 .chip_iounmap = pm8001_chip_iounmap,
3990 .isr = pm80xx_chip_isr,
3991 .is_our_interupt = pm80xx_chip_is_our_interupt,
3992 .isr_process_oq = process_oq,
3993 .interrupt_enable = pm80xx_chip_interrupt_enable,
3994 .interrupt_disable = pm80xx_chip_interrupt_disable,
3995 .make_prd = pm8001_chip_make_sg,
3996 .smp_req = pm80xx_chip_smp_req,
3997 .ssp_io_req = pm80xx_chip_ssp_io_req,
3998 .sata_req = pm80xx_chip_sata_req,
3999 .phy_start_req = pm80xx_chip_phy_start_req,
4000 .phy_stop_req = pm80xx_chip_phy_stop_req,
4001 .reg_dev_req = pm80xx_chip_reg_dev_req,
4002 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4003 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4004 .task_abort = pm8001_chip_abort_task,
4005 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4006 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4007 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4008 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4009 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4010};