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Vitaly Wool9325fa32006-06-26 19:31:49 +04001/*
2 * drivers/char/watchdog/pnx4008_wdt.c
3 *
4 * Watchdog driver for PNX4008 board
5 *
6 * Authors: Dmitry Chigirev <source@mvista.com>,
Wim Van Sebroeck5f3b2752011-02-23 20:04:38 +00007 * Vitaly Wool <vitalywool@gmail.com>
Vitaly Wool9325fa32006-06-26 19:31:49 +04008 * Based on sa1100 driver,
9 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
10 *
Wolfram Sang6b1e8382012-02-02 18:48:11 +010011 * 2005-2006 (c) MontaVista Software, Inc.
12 *
13 * (C) 2012 Wolfram Sang, Pengutronix
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
Vitaly Wool9325fa32006-06-26 19:31:49 +040018 */
19
Joe Perches27c766a2012-02-15 15:06:19 -080020#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
Vitaly Wool9325fa32006-06-26 19:31:49 +040022#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/types.h>
25#include <linux/kernel.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040026#include <linux/watchdog.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040027#include <linux/platform_device.h>
28#include <linux/clk.h>
Wim Van Sebroeck99d28532006-09-10 12:48:15 +020029#include <linux/spinlock.h>
Alan Cox84ca9952008-05-19 14:07:48 +010030#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Wolfram Sang6b1e8382012-02-02 18:48:11 +010032#include <linux/err.h>
Roland Stigge3ba37742012-04-20 21:55:29 +020033#include <linux/of.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010034#include <mach/hardware.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040035
Vitaly Wool9325fa32006-06-26 19:31:49 +040036/* WatchDog Timer - Chapter 23 Page 207 */
37
38#define DEFAULT_HEARTBEAT 19
39#define MAX_HEARTBEAT 60
40
41/* Watchdog timer register set definition */
42#define WDTIM_INT(p) ((p) + 0x0)
43#define WDTIM_CTRL(p) ((p) + 0x4)
44#define WDTIM_COUNTER(p) ((p) + 0x8)
45#define WDTIM_MCTRL(p) ((p) + 0xC)
46#define WDTIM_MATCH0(p) ((p) + 0x10)
47#define WDTIM_EMR(p) ((p) + 0x14)
48#define WDTIM_PULSE(p) ((p) + 0x18)
49#define WDTIM_RES(p) ((p) + 0x1C)
50
51/* WDTIM_INT bit definitions */
52#define MATCH_INT 1
53
54/* WDTIM_CTRL bit definitions */
55#define COUNT_ENAB 1
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000056#define RESET_COUNT (1 << 1)
57#define DEBUG_EN (1 << 2)
Vitaly Wool9325fa32006-06-26 19:31:49 +040058
59/* WDTIM_MCTRL bit definitions */
60#define MR0_INT 1
61#undef RESET_COUNT0
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000062#define RESET_COUNT0 (1 << 2)
63#define STOP_COUNT0 (1 << 2)
64#define M_RES1 (1 << 3)
65#define M_RES2 (1 << 4)
66#define RESFRC1 (1 << 5)
67#define RESFRC2 (1 << 6)
Vitaly Wool9325fa32006-06-26 19:31:49 +040068
69/* WDTIM_EMR bit definitions */
70#define EXT_MATCH0 1
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000071#define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */
Vitaly Wool9325fa32006-06-26 19:31:49 +040072
73/* WDTIM_RES bit definitions */
74#define WDOG_RESET 1 /* read only */
75
76#define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
77
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010078static bool nowayout = WATCHDOG_NOWAYOUT;
Wolfram Sang6b1e8382012-02-02 18:48:11 +010079static unsigned int heartbeat = DEFAULT_HEARTBEAT;
Vitaly Wool9325fa32006-06-26 19:31:49 +040080
Alexey Dobriyanc7dfd0c2007-11-01 16:27:08 -070081static DEFINE_SPINLOCK(io_lock);
Vitaly Wool9325fa32006-06-26 19:31:49 +040082static void __iomem *wdt_base;
83struct clk *wdt_clk;
84
Wolfram Sang6b1e8382012-02-02 18:48:11 +010085static int pnx4008_wdt_start(struct watchdog_device *wdd)
Vitaly Wool9325fa32006-06-26 19:31:49 +040086{
Wim Van Sebroeck99d28532006-09-10 12:48:15 +020087 spin_lock(&io_lock);
88
Vitaly Wool9325fa32006-06-26 19:31:49 +040089 /* stop counter, initiate counter reset */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010090 writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +040091 /*wait for reset to complete. 100% guarantee event */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010092 while (readl(WDTIM_COUNTER(wdt_base)))
Vitaly Wool65a64ec2006-09-11 14:42:39 +040093 cpu_relax();
Vitaly Wool9325fa32006-06-26 19:31:49 +040094 /* internal and external reset, stop after that */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010095 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +040096 /* configure match output */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010097 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +040098 /* clear interrupt, just in case */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010099 writel(MATCH_INT, WDTIM_INT(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +0400100 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100101 writel(0xFFFF, WDTIM_PULSE(wdt_base));
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100102 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +0400103 /*enable counter, stop when debugger active */
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100104 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200105
106 spin_unlock(&io_lock);
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100107 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400108}
109
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100110static int pnx4008_wdt_stop(struct watchdog_device *wdd)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400111{
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200112 spin_lock(&io_lock);
113
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200115
116 spin_unlock(&io_lock);
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100117 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400118}
119
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100120static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
121 unsigned int new_timeout)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400122{
Wim Van Sebroeck0197c1c2012-02-29 20:20:58 +0100123 wdd->timeout = new_timeout;
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100124 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400125}
126
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100127static const struct watchdog_info pnx4008_wdt_ident = {
Vitaly Wool9325fa32006-06-26 19:31:49 +0400128 .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
129 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
130 .identity = "PNX4008 Watchdog",
131};
132
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100133static const struct watchdog_ops pnx4008_wdt_ops = {
Vitaly Wool9325fa32006-06-26 19:31:49 +0400134 .owner = THIS_MODULE,
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100135 .start = pnx4008_wdt_start,
136 .stop = pnx4008_wdt_stop,
137 .set_timeout = pnx4008_wdt_set_timeout,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400138};
139
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100140static struct watchdog_device pnx4008_wdd = {
141 .info = &pnx4008_wdt_ident,
142 .ops = &pnx4008_wdt_ops,
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100143 .timeout = DEFAULT_HEARTBEAT,
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100144 .min_timeout = 1,
145 .max_timeout = MAX_HEARTBEAT,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400146};
147
Bill Pemberton2d991a12012-11-19 13:21:41 -0500148static int pnx4008_wdt_probe(struct platform_device *pdev)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400149{
Wolfram Sang19f505f2012-02-02 18:48:08 +0100150 struct resource *r;
151 int ret = 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400152
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100153 watchdog_init_timeout(&pnx4008_wdd, heartbeat, &pdev->dev);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400154
Wolfram Sang19f505f2012-02-02 18:48:08 +0100155 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding4c271bb2013-01-21 11:09:25 +0100156 wdt_base = devm_ioremap_resource(&pdev->dev, r);
157 if (IS_ERR(wdt_base))
158 return PTR_ERR(wdt_base);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400159
Jingoo Han259181f2013-04-29 18:16:14 +0900160 wdt_clk = devm_clk_get(&pdev->dev, NULL);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100161 if (IS_ERR(wdt_clk))
162 return PTR_ERR(wdt_clk);
Russell King24fd1ed2009-11-20 13:04:14 +0000163
164 ret = clk_enable(wdt_clk);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100165 if (ret)
Jingoo Han259181f2013-04-29 18:16:14 +0900166 return ret;
Wolfram Sang19f505f2012-02-02 18:48:08 +0100167
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100168 pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100169 WDIOF_CARDRESET : 0;
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100170 watchdog_set_nowayout(&pnx4008_wdd, nowayout);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400171
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100172 pnx4008_wdt_stop(&pnx4008_wdd); /* disable for now */
173
174 ret = watchdog_register_device(&pnx4008_wdd);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400175 if (ret < 0) {
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100176 dev_err(&pdev->dev, "cannot register watchdog device\n");
177 goto disable_clk;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400178 }
179
Wolfram Sang19f505f2012-02-02 18:48:08 +0100180 dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100181 pnx4008_wdd.timeout);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100182
183 return 0;
184
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100185disable_clk:
186 clk_disable(wdt_clk);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400187 return ret;
188}
189
Bill Pemberton4b12b892012-11-19 13:26:24 -0500190static int pnx4008_wdt_remove(struct platform_device *pdev)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400191{
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100192 watchdog_unregister_device(&pnx4008_wdd);
Russell King24fd1ed2009-11-20 13:04:14 +0000193
194 clk_disable(wdt_clk);
Russell King24fd1ed2009-11-20 13:04:14 +0000195
Vitaly Wool9325fa32006-06-26 19:31:49 +0400196 return 0;
197}
198
Roland Stigge3ba37742012-04-20 21:55:29 +0200199#ifdef CONFIG_OF
200static const struct of_device_id pnx4008_wdt_match[] = {
201 { .compatible = "nxp,pnx4008-wdt" },
202 { }
203};
204MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
205#endif
206
Vitaly Wool9325fa32006-06-26 19:31:49 +0400207static struct platform_driver platform_wdt_driver = {
208 .driver = {
Russell King1508c992009-11-20 13:07:57 +0000209 .name = "pnx4008-watchdog",
Roland Stigge3ba37742012-04-20 21:55:29 +0200210 .of_match_table = of_match_ptr(pnx4008_wdt_match),
Vitaly Wool9325fa32006-06-26 19:31:49 +0400211 },
212 .probe = pnx4008_wdt_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500213 .remove = pnx4008_wdt_remove,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400214};
215
Axel Linb8ec6112011-11-29 13:56:27 +0800216module_platform_driver(platform_wdt_driver);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400217
218MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
Wolfram Sange8cc5362015-04-20 15:51:43 +0200219MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
Vitaly Wool9325fa32006-06-26 19:31:49 +0400220MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
221
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100222module_param(heartbeat, uint, 0);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400223MODULE_PARM_DESC(heartbeat,
224 "Watchdog heartbeat period in seconds from 1 to "
225 __MODULE_STRING(MAX_HEARTBEAT) ", default "
226 __MODULE_STRING(DEFAULT_HEARTBEAT));
227
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +0100228module_param(nowayout, bool, 0);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400229MODULE_PARM_DESC(nowayout,
230 "Set to 1 to keep watchdog running after device release");
231
232MODULE_LICENSE("GPL");
Russell King1508c992009-11-20 13:07:57 +0000233MODULE_ALIAS("platform:pnx4008-watchdog");