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gerrit-public.fairphone.software / kernel / msm-4.9 / c7841473f7ecbff624809f31f36aab0df5041ef9 / . / arch / arm / boot / dts / tegra20-tec.dts
blob: c572c43751b180ac3e6112f0110a89dd046654d7 [file] [log] [blame]
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]1/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]3#include "tegra20-tamonten.dtsi"
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]4
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
Thierry Redingcab2ed62012-11-16 16:56:52 +0100[diff] [blame]9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]15 i2c@7000c000 {
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]16 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]20 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]21
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = <0xffffffff
28 0xffffffff
29 0
30 0xffffffff
31 0xffffffff>;
32 };
33 };
34
35 sound {
36 compatible = "ad,tegra-audio-wm8903-tec",
37 "nvidia,tegra-audio-wm8903";
38 nvidia,model = "Avionic Design TEC";
39
40 nvidia,audio-routing =
41 "Headphone Jack", "HPOUTR",
42 "Headphone Jack", "HPOUTL",
43 "Int Spk", "ROP",
44 "Int Spk", "RON",
45 "Int Spk", "LOP",
46 "Int Spk", "LON",
47 "Mic Jack", "MICBIAS",
48 "IN1L", "Mic Jack";
49
50 nvidia,i2s-controller = <&tegra_i2s1>;
51 nvidia,audio-codec = <&wm8903>;
52
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]53 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
54 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
55 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]56
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]57 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
59 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]60 clock-names = "pll_a", "pll_a_out0", "mclk";
Thierry Reding175f16f2012-09-20 17:06:09 +0200[diff] [blame]61 };
62};