Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2015 Intel Corporation. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of version 2 of the GNU General Public License as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * BSD LICENSE |
| 20 | * |
| 21 | * Copyright(c) 2015 Intel Corporation. |
| 22 | * |
| 23 | * Redistribution and use in source and binary forms, with or without |
| 24 | * modification, are permitted provided that the following conditions |
| 25 | * are met: |
| 26 | * |
| 27 | * - Redistributions of source code must retain the above copyright |
| 28 | * notice, this list of conditions and the following disclaimer. |
| 29 | * - Redistributions in binary form must reproduce the above copyright |
| 30 | * notice, this list of conditions and the following disclaimer in |
| 31 | * the documentation and/or other materials provided with the |
| 32 | * distribution. |
| 33 | * - Neither the name of Intel Corporation nor the names of its |
| 34 | * contributors may be used to endorse or promote products derived |
| 35 | * from this software without specific prior written permission. |
| 36 | * |
| 37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | #include <linux/delay.h> |
| 52 | #include <linux/pci.h> |
| 53 | #include <linux/vmalloc.h> |
| 54 | |
| 55 | #include "hfi.h" |
| 56 | #include "twsi.h" |
| 57 | |
| 58 | /* |
| 59 | * "Two Wire Serial Interface" support. |
| 60 | * |
| 61 | * Originally written for a not-quite-i2c serial eeprom, which is |
| 62 | * still used on some supported boards. Later boards have added a |
| 63 | * variety of other uses, most board-specific, so the bit-boffing |
| 64 | * part has been split off to this file, while the other parts |
| 65 | * have been moved to chip-specific files. |
| 66 | * |
| 67 | * We have also dropped all pretense of fully generic (e.g. pretend |
| 68 | * we don't know whether '1' is the higher voltage) interface, as |
| 69 | * the restrictions of the generic i2c interface (e.g. no access from |
| 70 | * driver itself) make it unsuitable for this use. |
| 71 | */ |
| 72 | |
| 73 | #define READ_CMD 1 |
| 74 | #define WRITE_CMD 0 |
| 75 | |
| 76 | /** |
| 77 | * i2c_wait_for_writes - wait for a write |
| 78 | * @dd: the hfi1_ib device |
| 79 | * |
| 80 | * We use this instead of udelay directly, so we can make sure |
| 81 | * that previous register writes have been flushed all the way |
| 82 | * to the chip. Since we are delaying anyway, the cost doesn't |
| 83 | * hurt, and makes the bit twiddling more regular |
| 84 | */ |
| 85 | static void i2c_wait_for_writes(struct hfi1_devdata *dd, u32 target) |
| 86 | { |
| 87 | /* |
| 88 | * implicit read of EXTStatus is as good as explicit |
| 89 | * read of scratch, if all we want to do is flush |
| 90 | * writes. |
| 91 | */ |
| 92 | hfi1_gpio_mod(dd, target, 0, 0, 0); |
| 93 | rmb(); /* inlined, so prevent compiler reordering */ |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that |
| 98 | * for "almost compliant" modules |
| 99 | */ |
| 100 | #define SCL_WAIT_USEC 1000 |
| 101 | |
| 102 | /* BUF_WAIT is time bus must be free between STOP or ACK and to next START. |
| 103 | * Should be 20, but some chips need more. |
| 104 | */ |
| 105 | #define TWSI_BUF_WAIT_USEC 60 |
| 106 | |
| 107 | static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit) |
| 108 | { |
| 109 | u32 mask; |
| 110 | |
| 111 | udelay(1); |
| 112 | |
| 113 | mask = QSFP_HFI0_I2CCLK; |
| 114 | |
| 115 | /* SCL is meant to be bare-drain, so never set "OUT", just DIR */ |
| 116 | hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask); |
| 117 | |
| 118 | /* |
| 119 | * Allow for slow slaves by simple |
| 120 | * delay for falling edge, sampling on rise. |
| 121 | */ |
| 122 | if (!bit) |
| 123 | udelay(2); |
| 124 | else { |
| 125 | int rise_usec; |
| 126 | |
| 127 | for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) { |
| 128 | if (mask & hfi1_gpio_mod(dd, target, 0, 0, 0)) |
| 129 | break; |
| 130 | udelay(2); |
| 131 | } |
| 132 | if (rise_usec <= 0) |
| 133 | dd_dev_err(dd, "SCL interface stuck low > %d uSec\n", |
| 134 | SCL_WAIT_USEC); |
| 135 | } |
| 136 | i2c_wait_for_writes(dd, target); |
| 137 | } |
| 138 | |
| 139 | static void sda_out(struct hfi1_devdata *dd, u32 target, u8 bit) |
| 140 | { |
| 141 | u32 mask; |
| 142 | |
| 143 | mask = QSFP_HFI0_I2CDAT; |
| 144 | |
| 145 | /* SDA is meant to be bare-drain, so never set "OUT", just DIR */ |
| 146 | hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask); |
| 147 | |
| 148 | i2c_wait_for_writes(dd, target); |
| 149 | udelay(2); |
| 150 | } |
| 151 | |
| 152 | static u8 sda_in(struct hfi1_devdata *dd, u32 target, int wait) |
| 153 | { |
| 154 | u32 read_val, mask; |
| 155 | |
| 156 | mask = QSFP_HFI0_I2CDAT; |
| 157 | /* SDA is meant to be bare-drain, so never set "OUT", just DIR */ |
| 158 | hfi1_gpio_mod(dd, target, 0, 0, mask); |
| 159 | read_val = hfi1_gpio_mod(dd, target, 0, 0, 0); |
| 160 | if (wait) |
| 161 | i2c_wait_for_writes(dd, target); |
| 162 | return (read_val & mask) >> GPIO_SDA_NUM; |
| 163 | } |
| 164 | |
| 165 | /** |
| 166 | * i2c_ackrcv - see if ack following write is true |
| 167 | * @dd: the hfi1_ib device |
| 168 | */ |
| 169 | static int i2c_ackrcv(struct hfi1_devdata *dd, u32 target) |
| 170 | { |
| 171 | u8 ack_received; |
| 172 | |
| 173 | /* AT ENTRY SCL = LOW */ |
| 174 | /* change direction, ignore data */ |
| 175 | ack_received = sda_in(dd, target, 1); |
| 176 | scl_out(dd, target, 1); |
| 177 | ack_received = sda_in(dd, target, 1) == 0; |
| 178 | scl_out(dd, target, 0); |
| 179 | return ack_received; |
| 180 | } |
| 181 | |
| 182 | static void stop_cmd(struct hfi1_devdata *dd, u32 target); |
| 183 | |
| 184 | /** |
| 185 | * rd_byte - read a byte, sending STOP on last, else ACK |
| 186 | * @dd: the hfi1_ib device |
| 187 | * |
| 188 | * Returns byte shifted out of device |
| 189 | */ |
| 190 | static int rd_byte(struct hfi1_devdata *dd, u32 target, int last) |
| 191 | { |
| 192 | int bit_cntr, data; |
| 193 | |
| 194 | data = 0; |
| 195 | |
| 196 | for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) { |
| 197 | data <<= 1; |
| 198 | scl_out(dd, target, 1); |
| 199 | data |= sda_in(dd, target, 0); |
| 200 | scl_out(dd, target, 0); |
| 201 | } |
| 202 | if (last) { |
| 203 | scl_out(dd, target, 1); |
| 204 | stop_cmd(dd, target); |
| 205 | } else { |
| 206 | sda_out(dd, target, 0); |
| 207 | scl_out(dd, target, 1); |
| 208 | scl_out(dd, target, 0); |
| 209 | sda_out(dd, target, 1); |
| 210 | } |
| 211 | return data; |
| 212 | } |
| 213 | |
| 214 | /** |
| 215 | * wr_byte - write a byte, one bit at a time |
| 216 | * @dd: the hfi1_ib device |
| 217 | * @data: the byte to write |
| 218 | * |
| 219 | * Returns 0 if we got the following ack, otherwise 1 |
| 220 | */ |
| 221 | static int wr_byte(struct hfi1_devdata *dd, u32 target, u8 data) |
| 222 | { |
| 223 | int bit_cntr; |
| 224 | u8 bit; |
| 225 | |
| 226 | for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) { |
| 227 | bit = (data >> bit_cntr) & 1; |
| 228 | sda_out(dd, target, bit); |
| 229 | scl_out(dd, target, 1); |
| 230 | scl_out(dd, target, 0); |
| 231 | } |
| 232 | return (!i2c_ackrcv(dd, target)) ? 1 : 0; |
| 233 | } |
| 234 | |
| 235 | /* |
| 236 | * issue TWSI start sequence: |
| 237 | * (both clock/data high, clock high, data low while clock is high) |
| 238 | */ |
| 239 | static void start_seq(struct hfi1_devdata *dd, u32 target) |
| 240 | { |
| 241 | sda_out(dd, target, 1); |
| 242 | scl_out(dd, target, 1); |
| 243 | sda_out(dd, target, 0); |
| 244 | udelay(1); |
| 245 | scl_out(dd, target, 0); |
| 246 | } |
| 247 | |
| 248 | /** |
| 249 | * stop_seq - transmit the stop sequence |
| 250 | * @dd: the hfi1_ib device |
| 251 | * |
| 252 | * (both clock/data low, clock high, data high while clock is high) |
| 253 | */ |
| 254 | static void stop_seq(struct hfi1_devdata *dd, u32 target) |
| 255 | { |
| 256 | scl_out(dd, target, 0); |
| 257 | sda_out(dd, target, 0); |
| 258 | scl_out(dd, target, 1); |
| 259 | sda_out(dd, target, 1); |
| 260 | } |
| 261 | |
| 262 | /** |
| 263 | * stop_cmd - transmit the stop condition |
| 264 | * @dd: the hfi1_ib device |
| 265 | * |
| 266 | * (both clock/data low, clock high, data high while clock is high) |
| 267 | */ |
| 268 | static void stop_cmd(struct hfi1_devdata *dd, u32 target) |
| 269 | { |
| 270 | stop_seq(dd, target); |
| 271 | udelay(TWSI_BUF_WAIT_USEC); |
| 272 | } |
| 273 | |
| 274 | /** |
| 275 | * hfi1_twsi_reset - reset I2C communication |
| 276 | * @dd: the hfi1_ib device |
| 277 | */ |
| 278 | |
| 279 | int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target) |
| 280 | { |
| 281 | int clock_cycles_left = 9; |
| 282 | int was_high = 0; |
| 283 | u32 pins, mask; |
| 284 | |
| 285 | /* Both SCL and SDA should be high. If not, there |
| 286 | * is something wrong. |
| 287 | */ |
| 288 | mask = QSFP_HFI0_I2CCLK | QSFP_HFI0_I2CDAT; |
| 289 | |
| 290 | /* |
| 291 | * Force pins to desired innocuous state. |
| 292 | * This is the default power-on state with out=0 and dir=0, |
| 293 | * So tri-stated and should be floating high (barring HW problems) |
| 294 | */ |
| 295 | hfi1_gpio_mod(dd, target, 0, 0, mask); |
| 296 | |
| 297 | /* |
| 298 | * Clock nine times to get all listeners into a sane state. |
| 299 | * If SDA does not go high at any point, we are wedged. |
| 300 | * One vendor recommends then issuing START followed by STOP. |
| 301 | * we cannot use our "normal" functions to do that, because |
| 302 | * if SCL drops between them, another vendor's part will |
| 303 | * wedge, dropping SDA and keeping it low forever, at the end of |
| 304 | * the next transaction (even if it was not the device addressed). |
| 305 | * So our START and STOP take place with SCL held high. |
| 306 | */ |
| 307 | while (clock_cycles_left--) { |
| 308 | scl_out(dd, target, 0); |
| 309 | scl_out(dd, target, 1); |
| 310 | /* Note if SDA is high, but keep clocking to sync slave */ |
| 311 | was_high |= sda_in(dd, target, 0); |
| 312 | } |
| 313 | |
| 314 | if (was_high) { |
| 315 | /* |
| 316 | * We saw a high, which we hope means the slave is sync'd. |
| 317 | * Issue START, STOP, pause for T_BUF. |
| 318 | */ |
| 319 | |
| 320 | pins = hfi1_gpio_mod(dd, target, 0, 0, 0); |
| 321 | if ((pins & mask) != mask) |
| 322 | dd_dev_err(dd, "GPIO pins not at rest: %d\n", |
| 323 | pins & mask); |
| 324 | /* Drop SDA to issue START */ |
| 325 | udelay(1); /* Guarantee .6 uSec setup */ |
| 326 | sda_out(dd, target, 0); |
| 327 | udelay(1); /* Guarantee .6 uSec hold */ |
| 328 | /* At this point, SCL is high, SDA low. Raise SDA for STOP */ |
| 329 | sda_out(dd, target, 1); |
| 330 | udelay(TWSI_BUF_WAIT_USEC); |
| 331 | } |
| 332 | |
| 333 | return !was_high; |
| 334 | } |
| 335 | |
| 336 | #define HFI1_TWSI_START 0x100 |
| 337 | #define HFI1_TWSI_STOP 0x200 |
| 338 | |
| 339 | /* Write byte to TWSI, optionally prefixed with START or suffixed with |
| 340 | * STOP. |
| 341 | * returns 0 if OK (ACK received), else != 0 |
| 342 | */ |
| 343 | static int twsi_wr(struct hfi1_devdata *dd, u32 target, int data, int flags) |
| 344 | { |
| 345 | int ret = 1; |
| 346 | |
| 347 | if (flags & HFI1_TWSI_START) |
| 348 | start_seq(dd, target); |
| 349 | |
| 350 | /* Leaves SCL low (from i2c_ackrcv()) */ |
| 351 | ret = wr_byte(dd, target, data); |
| 352 | |
| 353 | if (flags & HFI1_TWSI_STOP) |
| 354 | stop_cmd(dd, target); |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | /* Added functionality for IBA7220-based cards */ |
| 359 | #define HFI1_TEMP_DEV 0x98 |
| 360 | |
| 361 | /* |
| 362 | * hfi1_twsi_blk_rd |
| 363 | * General interface for data transfer from twsi devices. |
| 364 | * One vestige of its former role is that it recognizes a device |
| 365 | * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part, |
| 366 | * which responded to all TWSI device codes, interpreting them as |
| 367 | * address within device. On all other devices found on board handled by |
| 368 | * this driver, the device is followed by a one-byte "address" which selects |
| 369 | * the "register" or "offset" within the device from which data should |
| 370 | * be read. |
| 371 | */ |
| 372 | int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr, |
| 373 | void *buffer, int len) |
| 374 | { |
| 375 | int ret; |
| 376 | u8 *bp = buffer; |
| 377 | |
| 378 | ret = 1; |
| 379 | |
| 380 | if (dev == HFI1_TWSI_NO_DEV) { |
| 381 | /* legacy not-really-I2C */ |
| 382 | addr = (addr << 1) | READ_CMD; |
| 383 | ret = twsi_wr(dd, target, addr, HFI1_TWSI_START); |
| 384 | } else { |
| 385 | /* Actual I2C */ |
| 386 | ret = twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START); |
| 387 | if (ret) { |
| 388 | stop_cmd(dd, target); |
| 389 | ret = 1; |
| 390 | goto bail; |
| 391 | } |
| 392 | /* |
| 393 | * SFF spec claims we do _not_ stop after the addr |
| 394 | * but simply issue a start with the "read" dev-addr. |
| 395 | * Since we are implicitly waiting for ACK here, |
| 396 | * we need t_buf (nominally 20uSec) before that start, |
| 397 | * and cannot rely on the delay built in to the STOP |
| 398 | */ |
| 399 | ret = twsi_wr(dd, target, addr, 0); |
| 400 | udelay(TWSI_BUF_WAIT_USEC); |
| 401 | |
| 402 | if (ret) { |
| 403 | dd_dev_err(dd, |
| 404 | "Failed to write interface read addr %02X\n", |
| 405 | addr); |
| 406 | ret = 1; |
| 407 | goto bail; |
| 408 | } |
| 409 | ret = twsi_wr(dd, target, dev | READ_CMD, HFI1_TWSI_START); |
| 410 | } |
| 411 | if (ret) { |
| 412 | stop_cmd(dd, target); |
| 413 | ret = 1; |
| 414 | goto bail; |
| 415 | } |
| 416 | |
| 417 | /* |
| 418 | * block devices keeps clocking data out as long as we ack, |
| 419 | * automatically incrementing the address. Some have "pages" |
| 420 | * whose boundaries will not be crossed, but the handling |
| 421 | * of these is left to the caller, who is in a better |
| 422 | * position to know. |
| 423 | */ |
| 424 | while (len-- > 0) { |
| 425 | /* |
| 426 | * Get and store data, sending ACK if length remaining, |
| 427 | * else STOP |
| 428 | */ |
| 429 | *bp++ = rd_byte(dd, target, !len); |
| 430 | } |
| 431 | |
| 432 | ret = 0; |
| 433 | |
| 434 | bail: |
| 435 | return ret; |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * hfi1_twsi_blk_wr |
| 440 | * General interface for data transfer to twsi devices. |
| 441 | * One vestige of its former role is that it recognizes a device |
| 442 | * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part, |
| 443 | * which responded to all TWSI device codes, interpreting them as |
| 444 | * address within device. On all other devices found on board handled by |
| 445 | * this driver, the device is followed by a one-byte "address" which selects |
| 446 | * the "register" or "offset" within the device to which data should |
| 447 | * be written. |
| 448 | */ |
| 449 | int hfi1_twsi_blk_wr(struct hfi1_devdata *dd, u32 target, int dev, int addr, |
| 450 | const void *buffer, int len) |
| 451 | { |
| 452 | int sub_len; |
| 453 | const u8 *bp = buffer; |
| 454 | int max_wait_time, i; |
| 455 | int ret = 1; |
| 456 | |
| 457 | while (len > 0) { |
| 458 | if (dev == HFI1_TWSI_NO_DEV) { |
| 459 | if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD, |
| 460 | HFI1_TWSI_START)) { |
| 461 | goto failed_write; |
| 462 | } |
| 463 | } else { |
| 464 | /* Real I2C */ |
| 465 | if (twsi_wr(dd, target, |
| 466 | dev | WRITE_CMD, HFI1_TWSI_START)) |
| 467 | goto failed_write; |
| 468 | ret = twsi_wr(dd, target, addr, 0); |
| 469 | if (ret) { |
| 470 | dd_dev_err(dd, |
| 471 | "Failed to write interface write addr %02X\n", |
| 472 | addr); |
| 473 | goto failed_write; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | sub_len = min(len, 4); |
| 478 | addr += sub_len; |
| 479 | len -= sub_len; |
| 480 | |
| 481 | for (i = 0; i < sub_len; i++) |
| 482 | if (twsi_wr(dd, target, *bp++, 0)) |
| 483 | goto failed_write; |
| 484 | |
| 485 | stop_cmd(dd, target); |
| 486 | |
| 487 | /* |
| 488 | * Wait for write complete by waiting for a successful |
| 489 | * read (the chip replies with a zero after the write |
| 490 | * cmd completes, and before it writes to the eeprom. |
| 491 | * The startcmd for the read will fail the ack until |
| 492 | * the writes have completed. We do this inline to avoid |
| 493 | * the debug prints that are in the real read routine |
| 494 | * if the startcmd fails. |
| 495 | * We also use the proper device address, so it doesn't matter |
| 496 | * whether we have real eeprom_dev. Legacy likes any address. |
| 497 | */ |
| 498 | max_wait_time = 100; |
| 499 | while (twsi_wr(dd, target, |
| 500 | dev | READ_CMD, HFI1_TWSI_START)) { |
| 501 | stop_cmd(dd, target); |
| 502 | if (!--max_wait_time) |
| 503 | goto failed_write; |
| 504 | } |
| 505 | /* now read (and ignore) the resulting byte */ |
| 506 | rd_byte(dd, target, 1); |
| 507 | } |
| 508 | |
| 509 | ret = 0; |
| 510 | goto bail; |
| 511 | |
| 512 | failed_write: |
| 513 | stop_cmd(dd, target); |
| 514 | ret = 1; |
| 515 | |
| 516 | bail: |
| 517 | return ret; |
| 518 | } |