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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* ppc.h -- Header file for PowerPC opcode table
Michael Ellerman897f1122006-11-23 00:46:47 +01002 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
111, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
Michael Ellerman897f1122006-11-23 00:46:47 +010020Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22#ifndef PPC_H
23#define PPC_H
24
25/* The opcode table is an array of struct powerpc_opcode. */
26
27struct powerpc_opcode
28{
29 /* The opcode name. */
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
34 unsigned long opcode;
35
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
40 unsigned long mask;
41
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
44 are listed below. */
45 unsigned long flags;
46
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
51};
52
53/* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
55 instructions. */
56extern const struct powerpc_opcode powerpc_opcodes[];
57extern const int powerpc_num_opcodes;
58
59/* Values defined for the flags field of a struct powerpc_opcode. */
60
61/* Opcode is defined for the PowerPC architecture. */
62#define PPC_OPCODE_PPC 1
63
64/* Opcode is defined for the POWER (RS/6000) architecture. */
65#define PPC_OPCODE_POWER 2
66
67/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68#define PPC_OPCODE_POWER2 4
69
70/* Opcode is only defined on 32 bit architectures. */
71#define PPC_OPCODE_32 8
72
73/* Opcode is only defined on 64 bit architectures. */
74#define PPC_OPCODE_64 0x10
75
76/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79#define PPC_OPCODE_601 0x20
80
81/* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83#define PPC_OPCODE_COMMON 0x40
84
85/* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87#define PPC_OPCODE_ANY 0x80
88
89/* Opcode is supported as part of the 64-bit bridge. */
90#define PPC_OPCODE_64_BRIDGE 0x100
91
92/* Opcode is supported by Altivec Vector Unit */
93#define PPC_OPCODE_ALTIVEC 0x200
94
95/* Opcode is supported by PowerPC 403 processor. */
96#define PPC_OPCODE_403 0x400
97
98/* Opcode is supported by PowerPC BookE processor. */
99#define PPC_OPCODE_BOOKE 0x800
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor. */
102#define PPC_OPCODE_BOOKE64 0x1000
103
104/* Opcode is supported by PowerPC 440 processor. */
105#define PPC_OPCODE_440 0x2000
106
107/* Opcode is only supported by Power4 architecture. */
108#define PPC_OPCODE_POWER4 0x4000
109
110/* Opcode isn't supported by Power4 architecture. */
111#define PPC_OPCODE_NOPOWER4 0x8000
112
113/* Opcode is only supported by POWERPC Classic architecture. */
114#define PPC_OPCODE_CLASSIC 0x10000
115
116/* Opcode is only supported by e500x2 Core. */
117#define PPC_OPCODE_SPE 0x20000
118
119/* Opcode is supported by e500x2 Integer select APU. */
120#define PPC_OPCODE_ISEL 0x40000
121
122/* Opcode is an e500 SPE floating point instruction. */
123#define PPC_OPCODE_EFS 0x80000
124
125/* Opcode is supported by branch locking APU. */
126#define PPC_OPCODE_BRLOCK 0x100000
127
128/* Opcode is supported by performance monitor APU. */
129#define PPC_OPCODE_PMR 0x200000
130
131/* Opcode is supported by cache locking APU. */
132#define PPC_OPCODE_CACHELCK 0x400000
133
134/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000
136
Michael Ellerman897f1122006-11-23 00:46:47 +0100137/* Opcode is only supported by Power5 architecture. */
138#define PPC_OPCODE_POWER5 0x1000000
139
140/* Opcode is supported by PowerPC e300 family. */
141#define PPC_OPCODE_E300 0x2000000
142
143/* Opcode is only supported by Power6 architecture. */
144#define PPC_OPCODE_POWER6 0x4000000
145
146/* Opcode is only supported by PowerPC Cell family. */
147#define PPC_OPCODE_CELL 0x8000000
148
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149/* A macro to extract the major opcode from an instruction. */
150#define PPC_OP(i) (((i) >> 26) & 0x3f)
151
152/* The operands table is an array of struct powerpc_operand. */
153
154struct powerpc_operand
155{
156 /* The number of bits in the operand. */
157 int bits;
158
159 /* How far the operand is left shifted in the instruction. */
160 int shift;
161
162 /* Insertion function. This is used by the assembler. To insert an
163 operand value into an instruction, check this field.
164
165 If it is NULL, execute
166 i |= (op & ((1 << o->bits) - 1)) << o->shift;
167 (i is the instruction which we are filling in, o is a pointer to
168 this structure, and op is the opcode value; this assumes twos
169 complement arithmetic).
170
171 If this field is not NULL, then simply call it with the
172 instruction and the operand value. It will return the new value
173 of the instruction. If the ERRMSG argument is not NULL, then if
174 the operand value is illegal, *ERRMSG will be set to a warning
175 string (the operand will be inserted in any case). If the
176 operand value is legal, *ERRMSG will be unchanged (most operands
177 can accept any value). */
178 unsigned long (*insert)
179 (unsigned long instruction, long op, int dialect, const char **errmsg);
180
181 /* Extraction function. This is used by the disassembler. To
182 extract this operand type from an instruction, check this field.
183
184 If it is NULL, compute
185 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
186 if ((o->flags & PPC_OPERAND_SIGNED) != 0
187 && (op & (1 << (o->bits - 1))) != 0)
188 op -= 1 << o->bits;
189 (i is the instruction, o is a pointer to this structure, and op
190 is the result; this assumes twos complement arithmetic).
191
192 If this field is not NULL, then simply call it with the
193 instruction value. It will return the value of the operand. If
194 the INVALID argument is not NULL, *INVALID will be set to
195 non-zero if this operand type can not actually be extracted from
196 this operand (i.e., the instruction does not match). If the
197 operand is valid, *INVALID will not be changed. */
198 long (*extract) (unsigned long instruction, int dialect, int *invalid);
199
200 /* One bit syntax flags. */
201 unsigned long flags;
202};
203
204/* Elements in the table are retrieved by indexing with values from
205 the operands field of the powerpc_opcodes table. */
206
207extern const struct powerpc_operand powerpc_operands[];
208
209/* Values defined for the flags field of a struct powerpc_operand. */
210
211/* This operand takes signed values. */
212#define PPC_OPERAND_SIGNED (01)
213
214/* This operand takes signed values, but also accepts a full positive
215 range of values when running in 32 bit mode. That is, if bits is
216 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
217 this flag is ignored. */
218#define PPC_OPERAND_SIGNOPT (02)
219
220/* This operand does not actually exist in the assembler input. This
221 is used to support extended mnemonics such as mr, for which two
222 operands fields are identical. The assembler should call the
223 insert function with any op value. The disassembler should call
224 the extract function, ignore the return value, and check the value
225 placed in the valid argument. */
226#define PPC_OPERAND_FAKE (04)
227
228/* The next operand should be wrapped in parentheses rather than
229 separated from this one by a comma. This is used for the load and
230 store instructions which want their operands to look like
231 reg,displacement(reg)
232 */
233#define PPC_OPERAND_PARENS (010)
234
235/* This operand may use the symbolic names for the CR fields, which
236 are
237 lt 0 gt 1 eq 2 so 3 un 3
238 cr0 0 cr1 1 cr2 2 cr3 3
239 cr4 4 cr5 5 cr6 6 cr7 7
240 These may be combined arithmetically, as in cr2*4+gt. These are
241 only supported on the PowerPC, not the POWER. */
242#define PPC_OPERAND_CR (020)
243
244/* This operand names a register. The disassembler uses this to print
245 register names with a leading 'r'. */
246#define PPC_OPERAND_GPR (040)
247
Michael Ellerman897f1122006-11-23 00:46:47 +0100248/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
249#define PPC_OPERAND_GPR_0 (0100)
250
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251/* This operand names a floating point register. The disassembler
252 prints these with a leading 'f'. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100253#define PPC_OPERAND_FPR (0200)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
255/* This operand is a relative branch displacement. The disassembler
256 prints these symbolically if possible. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100257#define PPC_OPERAND_RELATIVE (0400)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
259/* This operand is an absolute branch address. The disassembler
260 prints these symbolically if possible. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100261#define PPC_OPERAND_ABSOLUTE (01000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262
263/* This operand is optional, and is zero if omitted. This is used for
Michael Ellerman897f1122006-11-23 00:46:47 +0100264 example, in the optional BF field in the comparison instructions. The
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 assembler must count the number of operands remaining on the line,
266 and the number of operands remaining for the opcode, and decide
267 whether this operand is present or not. The disassembler should
268 print this operand out only if it is not zero. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100269#define PPC_OPERAND_OPTIONAL (02000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270
271/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
272 is omitted, then for the next operand use this operand value plus
273 1, ignoring the next operand field for the opcode. This wretched
274 hack is needed because the Power rotate instructions can take
275 either 4 or 5 operands. The disassembler should print this operand
276 out regardless of the PPC_OPERAND_OPTIONAL field. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100277#define PPC_OPERAND_NEXT (04000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278
279/* This operand should be regarded as a negative number for the
280 purposes of overflow checking (i.e., the normal most negative
281 number is disallowed and one more than the normal most positive
282 number is allowed). This flag will only be set for a signed
283 operand. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100284#define PPC_OPERAND_NEGATIVE (010000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285
286/* This operand names a vector unit register. The disassembler
287 prints these with a leading 'v'. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100288#define PPC_OPERAND_VR (020000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
290/* This operand is for the DS field in a DS form instruction. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100291#define PPC_OPERAND_DS (040000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
293/* This operand is for the DQ field in a DQ form instruction. */
Michael Ellerman897f1122006-11-23 00:46:47 +0100294#define PPC_OPERAND_DQ (0100000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
296/* The POWER and PowerPC assemblers use a few macros. We keep them
297 with the operands table for simplicity. The macro table is an
298 array of struct powerpc_macro. */
299
300struct powerpc_macro
301{
302 /* The macro name. */
303 const char *name;
304
305 /* The number of operands the macro takes. */
306 unsigned int operands;
307
308 /* One bit flags for the opcode. These are used to indicate which
309 specific processors support the instructions. The values are the
310 same as those for the struct powerpc_opcode flags field. */
311 unsigned long flags;
312
313 /* A format string to turn the macro into a normal instruction.
314 Each %N in the string is replaced with operand number N (zero
315 based). */
316 const char *format;
317};
318
319extern const struct powerpc_macro powerpc_macros[];
320extern const int powerpc_num_macros;
321
322#endif /* PPC_H */