Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Thierry Reding | 146db0e | 2013-12-19 17:06:19 +0100 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 4 | #include "tegra124.dtsi" |
| 5 | |
| 6 | / { |
| 7 | model = "NVIDIA Tegra124 Venice2"; |
| 8 | compatible = "nvidia,venice2", "nvidia,tegra124"; |
| 9 | |
Stephen Warren | b1afa78 | 2013-12-19 11:32:15 -0700 | [diff] [blame] | 10 | aliases { |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 11 | rtc0 = "/i2c@0,7000d000/pmic@40"; |
| 12 | rtc1 = "/rtc@0,7000e000"; |
Stephen Warren | b1afa78 | 2013-12-19 11:32:15 -0700 | [diff] [blame] | 13 | }; |
| 14 | |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 15 | memory { |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 16 | reg = <0x0 0x80000000 0x0 0x80000000>; |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 17 | }; |
| 18 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 19 | host1x@0,50000000 { |
| 20 | sor@0,54540000 { |
Thierry Reding | 40e231c | 2014-02-28 17:40:24 +0100 | [diff] [blame] | 21 | status = "okay"; |
| 22 | |
| 23 | nvidia,dpaux = <&dpaux>; |
| 24 | nvidia,panel = <&panel>; |
| 25 | }; |
| 26 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 27 | dpaux: dpaux@0,545c0000 { |
Thierry Reding | 40e231c | 2014-02-28 17:40:24 +0100 | [diff] [blame] | 28 | vdd-supply = <&vdd_3v3_panel>; |
| 29 | status = "okay"; |
| 30 | }; |
| 31 | }; |
| 32 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 33 | pinmux: pinmux@0,70000868 { |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 34 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&pinmux_default>; |
| 36 | |
| 37 | pinmux_default: common { |
| 38 | dap_mclk1_pw4 { |
| 39 | nvidia,pins = "dap_mclk1_pw4"; |
| 40 | nvidia,function = "extperiph1"; |
| 41 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 42 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 43 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 44 | }; |
| 45 | dap1_din_pn1 { |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 46 | nvidia,pins = "dap1_din_pn1"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 47 | nvidia,function = "i2s0"; |
| 48 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 49 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 50 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 51 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 52 | dap1_dout_pn2 { |
| 53 | nvidia,pins = "dap1_dout_pn2", |
| 54 | "dap1_fs_pn0", |
| 55 | "dap1_sclk_pn3"; |
| 56 | nvidia,function = "i2s0"; |
| 57 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 58 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 59 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 60 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 61 | dap2_din_pa4 { |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 62 | nvidia,pins = "dap2_din_pa4"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 63 | nvidia,function = "i2s1"; |
| 64 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 65 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | 4ffb938 | 2013-12-12 14:40:30 -0700 | [diff] [blame] | 66 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 67 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 68 | dap2_dout_pa5 { |
| 69 | nvidia,pins = "dap2_dout_pa5", |
| 70 | "dap2_fs_pa2", |
| 71 | "dap2_sclk_pa3"; |
| 72 | nvidia,function = "i2s1"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 73 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 74 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 76 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 77 | dvfs_pwm_px0 { |
| 78 | nvidia,pins = "dvfs_pwm_px0", |
| 79 | "dvfs_clk_px2"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 80 | nvidia,function = "cldvfs"; |
| 81 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 82 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 83 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 84 | }; |
| 85 | ulpi_clk_py0 { |
| 86 | nvidia,pins = "ulpi_clk_py0", |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 87 | "ulpi_nxt_py2", |
| 88 | "ulpi_stp_py3"; |
| 89 | nvidia,function = "spi1"; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 90 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 91 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 92 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 93 | }; |
| 94 | ulpi_dir_py1 { |
| 95 | nvidia,pins = "ulpi_dir_py1"; |
| 96 | nvidia,function = "spi1"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 97 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 98 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 99 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 100 | }; |
| 101 | cam_i2c_scl_pbb1 { |
| 102 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 103 | "cam_i2c_sda_pbb2"; |
| 104 | nvidia,function = "i2c3"; |
| 105 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 106 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 108 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 109 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 110 | }; |
| 111 | gen2_i2c_scl_pt5 { |
| 112 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 113 | "gen2_i2c_sda_pt6"; |
| 114 | nvidia,function = "i2c2"; |
| 115 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 116 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 118 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 119 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 120 | }; |
| 121 | pg4 { |
| 122 | nvidia,pins = "pg4", |
| 123 | "pg5", |
| 124 | "pg6", |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 125 | "pi3"; |
| 126 | nvidia,function = "spi4"; |
| 127 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 130 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 131 | pg7 { |
| 132 | nvidia,pins = "pg7"; |
| 133 | nvidia,function = "spi4"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 137 | }; |
| 138 | ph1 { |
| 139 | nvidia,pins = "ph1"; |
| 140 | nvidia,function = "pwm1"; |
| 141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 142 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 143 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 144 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 145 | pk0 { |
| 146 | nvidia,pins = "pk0", |
| 147 | "kb_row15_ps7", |
| 148 | "clk_32k_out_pa0"; |
| 149 | nvidia,function = "soc"; |
| 150 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Thierry Reding | f5cb19b | 2013-12-13 17:25:04 +0100 | [diff] [blame] | 151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 152 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Thierry Reding | f5cb19b | 2013-12-13 17:25:04 +0100 | [diff] [blame] | 153 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 154 | sdmmc1_clk_pz0 { |
Stephen Warren | bf5fd5b | 2014-03-20 18:06:01 -0600 | [diff] [blame] | 155 | nvidia,pins = "sdmmc1_clk_pz0"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 156 | nvidia,function = "sdmmc1"; |
Stephen Warren | bf5fd5b | 2014-03-20 18:06:01 -0600 | [diff] [blame] | 157 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 160 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 161 | sdmmc1_cmd_pz1 { |
| 162 | nvidia,pins = "sdmmc1_cmd_pz1", |
| 163 | "sdmmc1_dat0_py7", |
| 164 | "sdmmc1_dat1_py6", |
| 165 | "sdmmc1_dat2_py5", |
| 166 | "sdmmc1_dat3_py4"; |
| 167 | nvidia,function = "sdmmc1"; |
| 168 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 169 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 170 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 171 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 172 | sdmmc3_clk_pa6 { |
| 173 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 174 | nvidia,function = "sdmmc3"; |
| 175 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 178 | }; |
| 179 | sdmmc3_cmd_pa7 { |
| 180 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 181 | "sdmmc3_dat0_pb7", |
| 182 | "sdmmc3_dat1_pb6", |
| 183 | "sdmmc3_dat2_pb5", |
| 184 | "sdmmc3_dat3_pb4", |
| 185 | "sdmmc3_clk_lb_out_pee4", |
| 186 | "sdmmc3_clk_lb_in_pee5"; |
| 187 | nvidia,function = "sdmmc3"; |
| 188 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 189 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 190 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 191 | }; |
| 192 | sdmmc4_clk_pcc4 { |
| 193 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 194 | nvidia,function = "sdmmc4"; |
| 195 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 196 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 197 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 198 | }; |
| 199 | sdmmc4_cmd_pt7 { |
| 200 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 201 | "sdmmc4_dat0_paa0", |
| 202 | "sdmmc4_dat1_paa1", |
| 203 | "sdmmc4_dat2_paa2", |
| 204 | "sdmmc4_dat3_paa3", |
| 205 | "sdmmc4_dat4_paa4", |
| 206 | "sdmmc4_dat5_paa5", |
| 207 | "sdmmc4_dat6_paa6", |
| 208 | "sdmmc4_dat7_paa7"; |
| 209 | nvidia,function = "sdmmc4"; |
| 210 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 211 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 213 | }; |
| 214 | pwr_i2c_scl_pz6 { |
| 215 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 216 | "pwr_i2c_sda_pz7"; |
| 217 | nvidia,function = "i2cpwr"; |
| 218 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 219 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 220 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 221 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 222 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 223 | }; |
| 224 | jtag_rtck { |
| 225 | nvidia,pins = "jtag_rtck"; |
| 226 | nvidia,function = "rtck"; |
| 227 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 228 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 229 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 230 | }; |
| 231 | clk_32k_in { |
| 232 | nvidia,pins = "clk_32k_in"; |
| 233 | nvidia,function = "clk"; |
| 234 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 235 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 236 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 237 | }; |
| 238 | core_pwr_req { |
| 239 | nvidia,pins = "core_pwr_req"; |
| 240 | nvidia,function = "pwron"; |
| 241 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 242 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 244 | }; |
| 245 | cpu_pwr_req { |
| 246 | nvidia,pins = "cpu_pwr_req"; |
| 247 | nvidia,function = "cpu"; |
| 248 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 249 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 250 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 251 | }; |
| 252 | pwr_int_n { |
| 253 | nvidia,pins = "pwr_int_n"; |
| 254 | nvidia,function = "pmi"; |
| 255 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 256 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 258 | }; |
| 259 | reset_out_n { |
| 260 | nvidia,pins = "reset_out_n"; |
| 261 | nvidia,function = "reset_out_n"; |
| 262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 263 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 265 | }; |
| 266 | clk3_out_pee0 { |
| 267 | nvidia,pins = "clk3_out_pee0"; |
| 268 | nvidia,function = "extperiph3"; |
| 269 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 272 | }; |
| 273 | dap4_din_pp5 { |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 274 | nvidia,pins = "dap4_din_pp5"; |
| 275 | nvidia,function = "i2s3"; |
| 276 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 279 | }; |
| 280 | dap4_dout_pp6 { |
| 281 | nvidia,pins = "dap4_dout_pp6", |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 282 | "dap4_fs_pp4", |
| 283 | "dap4_sclk_pp7"; |
| 284 | nvidia,function = "i2s3"; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 285 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 287 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 288 | }; |
| 289 | gen1_i2c_sda_pc5 { |
| 290 | nvidia,pins = "gen1_i2c_sda_pc5", |
| 291 | "gen1_i2c_scl_pc4"; |
| 292 | nvidia,function = "i2c1"; |
| 293 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 296 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 297 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 298 | }; |
| 299 | uart2_cts_n_pj5 { |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 300 | nvidia,pins = "uart2_cts_n_pj5"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 301 | nvidia,function = "uartb"; |
| 302 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 304 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 305 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 306 | uart2_rts_n_pj6 { |
| 307 | nvidia,pins = "uart2_rts_n_pj6"; |
| 308 | nvidia,function = "uartb"; |
| 309 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 310 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 311 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 312 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 313 | uart2_rxd_pc3 { |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 314 | nvidia,pins = "uart2_rxd_pc3"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 315 | nvidia,function = "irda"; |
| 316 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 317 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 318 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 319 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 320 | uart2_txd_pc2 { |
| 321 | nvidia,pins = "uart2_txd_pc2"; |
| 322 | nvidia,function = "irda"; |
| 323 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 324 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 325 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 326 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 327 | uart3_cts_n_pa1 { |
| 328 | nvidia,pins = "uart3_cts_n_pa1", |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 329 | "uart3_rxd_pw7"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 330 | nvidia,function = "uartc"; |
| 331 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 332 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 334 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 335 | uart3_rts_n_pc0 { |
| 336 | nvidia,pins = "uart3_rts_n_pc0", |
| 337 | "uart3_txd_pw6"; |
| 338 | nvidia,function = "uartc"; |
| 339 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 340 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 341 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 342 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 343 | hdmi_cec_pee3 { |
| 344 | nvidia,pins = "hdmi_cec_pee3"; |
| 345 | nvidia,function = "cec"; |
| 346 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 347 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 349 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 350 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 351 | }; |
| 352 | hdmi_int_pn7 { |
| 353 | nvidia,pins = "hdmi_int_pn7"; |
| 354 | nvidia,function = "rsvd1"; |
| 355 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 356 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 357 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 358 | }; |
| 359 | ddc_scl_pv4 { |
| 360 | nvidia,pins = "ddc_scl_pv4", |
| 361 | "ddc_sda_pv5"; |
| 362 | nvidia,function = "i2c4"; |
| 363 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 364 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 365 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 366 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
| 367 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; |
| 368 | }; |
| 369 | pj7 { |
| 370 | nvidia,pins = "pj7", |
| 371 | "pk7"; |
| 372 | nvidia,function = "uartd"; |
| 373 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 374 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 375 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 376 | }; |
| 377 | pb0 { |
| 378 | nvidia,pins = "pb0", |
| 379 | "pb1"; |
| 380 | nvidia,function = "uartd"; |
| 381 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 382 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 383 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 384 | }; |
| 385 | ph0 { |
| 386 | nvidia,pins = "ph0"; |
| 387 | nvidia,function = "pwm0"; |
| 388 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 389 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 390 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 391 | }; |
| 392 | kb_row10_ps2 { |
| 393 | nvidia,pins = "kb_row10_ps2"; |
| 394 | nvidia,function = "uarta"; |
| 395 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 396 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 397 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 398 | }; |
| 399 | kb_row9_ps1 { |
| 400 | nvidia,pins = "kb_row9_ps1"; |
| 401 | nvidia,function = "uarta"; |
| 402 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 403 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 404 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 405 | }; |
| 406 | kb_row6_pr6 { |
| 407 | nvidia,pins = "kb_row6_pr6"; |
| 408 | nvidia,function = "displaya_alt"; |
| 409 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 410 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 411 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 412 | }; |
| 413 | usb_vbus_en0_pn4 { |
Thierry Reding | fa15ffa | 2014-02-25 16:45:04 +0100 | [diff] [blame] | 414 | nvidia,pins = "usb_vbus_en0_pn4", |
| 415 | "usb_vbus_en1_pn5"; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 416 | nvidia,function = "usb"; |
| 417 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Thierry Reding | fa15ffa | 2014-02-25 16:45:04 +0100 | [diff] [blame] | 418 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 419 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 420 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 421 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 422 | }; |
| 423 | drive_sdio1 { |
| 424 | nvidia,pins = "drive_sdio1"; |
| 425 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 426 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 427 | nvidia,pull-down-strength = <32>; |
| 428 | nvidia,pull-up-strength = <42>; |
| 429 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 430 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 431 | }; |
| 432 | drive_sdio3 { |
| 433 | nvidia,pins = "drive_sdio3"; |
| 434 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 435 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 436 | nvidia,pull-down-strength = <20>; |
| 437 | nvidia,pull-up-strength = <36>; |
| 438 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 439 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 440 | }; |
| 441 | drive_gma { |
| 442 | nvidia,pins = "drive_gma"; |
| 443 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| 444 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 445 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 446 | nvidia,pull-down-strength = <1>; |
| 447 | nvidia,pull-up-strength = <2>; |
| 448 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 449 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 450 | nvidia,drive-type = <1>; |
| 451 | }; |
Laxman Dewangan | 365c483 | 2013-12-18 18:22:58 +0530 | [diff] [blame] | 452 | als_irq_l { |
| 453 | nvidia,pins = "gpio_x3_aud_px3"; |
| 454 | nvidia,function = "gmi"; |
| 455 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 456 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 457 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 458 | }; |
| 459 | codec_irq_l { |
| 460 | nvidia,pins = "ph4"; |
| 461 | nvidia,function = "gmi"; |
| 462 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 463 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 464 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 465 | }; |
| 466 | lcd_bl_en { |
| 467 | nvidia,pins = "ph2"; |
| 468 | nvidia,function = "gmi"; |
| 469 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 472 | }; |
| 473 | touch_irq_l { |
| 474 | nvidia,pins = "gpio_w3_aud_pw3"; |
| 475 | nvidia,function = "spi6"; |
| 476 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 477 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 478 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 479 | }; |
| 480 | tpm_davint_l { |
| 481 | nvidia,pins = "ph6"; |
| 482 | nvidia,function = "gmi"; |
| 483 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 484 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 485 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 486 | }; |
| 487 | ts_irq_l { |
| 488 | nvidia,pins = "pk2"; |
| 489 | nvidia,function = "gmi"; |
| 490 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 491 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 492 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 493 | }; |
| 494 | ts_reset_l { |
| 495 | nvidia,pins = "pk4"; |
| 496 | nvidia,function = "gmi"; |
| 497 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 498 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 499 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 500 | }; |
| 501 | ts_shdn_l { |
| 502 | nvidia,pins = "pk1"; |
| 503 | nvidia,function = "gmi"; |
| 504 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 506 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 507 | }; |
| 508 | ph7 { |
| 509 | nvidia,pins = "ph7"; |
| 510 | nvidia,function = "gmi"; |
| 511 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 512 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 513 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 514 | }; |
| 515 | kb_col0_ap { |
| 516 | nvidia,pins = "kb_col0_pq0"; |
| 517 | nvidia,function = "rsvd4"; |
| 518 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 519 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 520 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 521 | }; |
| 522 | lid_open { |
| 523 | nvidia,pins = "kb_row4_pr4"; |
| 524 | nvidia,function = "rsvd3"; |
| 525 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 526 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 527 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 528 | }; |
| 529 | en_vdd_sd { |
| 530 | nvidia,pins = "kb_row0_pr0"; |
| 531 | nvidia,function = "rsvd4"; |
| 532 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 534 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 535 | }; |
| 536 | ac_ok { |
| 537 | nvidia,pins = "pj0"; |
| 538 | nvidia,function = "gmi"; |
| 539 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 540 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 541 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 542 | }; |
| 543 | sensor_irq_l { |
| 544 | nvidia,pins = "pi6"; |
| 545 | nvidia,function = "gmi"; |
| 546 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 547 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 548 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 549 | }; |
| 550 | wifi_en { |
| 551 | nvidia,pins = "gpio_x7_aud_px7"; |
| 552 | nvidia,function = "rsvd4"; |
| 553 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 555 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 556 | }; |
| 557 | wifi_rst_l { |
| 558 | nvidia,pins = "clk2_req_pcc5"; |
| 559 | nvidia,function = "dap"; |
| 560 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 563 | }; |
| 564 | hp_det_l { |
| 565 | nvidia,pins = "ulpi_data1_po2"; |
| 566 | nvidia,function = "spi3"; |
| 567 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 569 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 570 | }; |
Laxman Dewangan | 4b20bcb | 2013-12-09 16:03:51 +0530 | [diff] [blame] | 571 | }; |
| 572 | }; |
| 573 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 574 | serial@0,70006000 { |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 575 | status = "okay"; |
| 576 | }; |
| 577 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 578 | pwm: pwm@0,7000a000 { |
Thierry Reding | e013485 | 2013-11-18 17:00:35 +0100 | [diff] [blame] | 579 | status = "okay"; |
| 580 | }; |
| 581 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 582 | i2c@0,7000c000 { |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 583 | status = "okay"; |
| 584 | clock-frequency = <100000>; |
Stephen Warren | b0e1cae | 2013-12-03 17:26:12 -0700 | [diff] [blame] | 585 | |
| 586 | acodec: audio-codec@10 { |
| 587 | compatible = "maxim,max98090"; |
| 588 | reg = <0x10>; |
| 589 | interrupt-parent = <&gpio>; |
| 590 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; |
| 591 | }; |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 592 | }; |
| 593 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 594 | i2c@0,7000c400 { |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 595 | status = "okay"; |
| 596 | clock-frequency = <100000>; |
| 597 | }; |
| 598 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 599 | i2c@0,7000c500 { |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 600 | status = "okay"; |
| 601 | clock-frequency = <100000>; |
| 602 | }; |
| 603 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 604 | i2c@0,7000c700 { |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 605 | status = "okay"; |
| 606 | clock-frequency = <100000>; |
| 607 | }; |
| 608 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 609 | i2c@0,7000d000 { |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 610 | status = "okay"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 611 | clock-frequency = <400000>; |
| 612 | |
Thierry Reding | fdc44f9 | 2014-02-28 17:40:28 +0100 | [diff] [blame] | 613 | pmic: pmic@40 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 614 | compatible = "ams,as3722"; |
| 615 | reg = <0x40>; |
| 616 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 617 | |
Laxman Dewangan | 7be75df | 2014-01-09 16:31:48 +0530 | [diff] [blame] | 618 | ams,system-power-controller; |
| 619 | |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 620 | #interrupt-cells = <2>; |
| 621 | interrupt-controller; |
| 622 | |
| 623 | gpio-controller; |
| 624 | #gpio-cells = <2>; |
| 625 | |
| 626 | pinctrl-names = "default"; |
| 627 | pinctrl-0 = <&as3722_default>; |
| 628 | |
| 629 | as3722_default: pinmux { |
| 630 | gpio0 { |
| 631 | pins = "gpio0"; |
| 632 | function = "gpio"; |
| 633 | bias-pull-down; |
| 634 | }; |
| 635 | |
| 636 | gpio1_2_4_7 { |
| 637 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; |
| 638 | function = "gpio"; |
| 639 | bias-pull-up; |
| 640 | }; |
| 641 | |
| 642 | gpio3_6 { |
| 643 | pins = "gpio3", "gpio6"; |
| 644 | bias-high-impedance; |
| 645 | }; |
| 646 | |
| 647 | gpio5 { |
| 648 | pins = "gpio5"; |
| 649 | function = "clk32k-out"; |
| 650 | }; |
| 651 | }; |
| 652 | |
| 653 | regulators { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 654 | vsup-sd2-supply = <&vdd_5v0_sys>; |
| 655 | vsup-sd3-supply = <&vdd_5v0_sys>; |
| 656 | vsup-sd4-supply = <&vdd_5v0_sys>; |
| 657 | vsup-sd5-supply = <&vdd_5v0_sys>; |
| 658 | vin-ldo0-supply = <&vdd_1v35_lp0>; |
| 659 | vin-ldo1-6-supply = <&vdd_3v3_run>; |
| 660 | vin-ldo2-5-7-supply = <&vddio_1v8>; |
| 661 | vin-ldo3-4-supply = <&vdd_3v3_sys>; |
| 662 | vin-ldo9-10-supply = <&vdd_5v0_sys>; |
| 663 | vin-ldo11-supply = <&vdd_3v3_run>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 664 | |
| 665 | sd0 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 666 | regulator-name = "+VDD_CPU_AP"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 667 | regulator-min-microvolt = <700000>; |
| 668 | regulator-max-microvolt = <1400000>; |
| 669 | regulator-min-microamp = <3500000>; |
| 670 | regulator-max-microamp = <3500000>; |
| 671 | regulator-always-on; |
| 672 | regulator-boot-on; |
| 673 | ams,external-control = <2>; |
| 674 | }; |
| 675 | |
| 676 | sd1 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 677 | regulator-name = "+VDD_CORE"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 678 | regulator-min-microvolt = <700000>; |
| 679 | regulator-max-microvolt = <1350000>; |
| 680 | regulator-min-microamp = <2500000>; |
| 681 | regulator-max-microamp = <2500000>; |
| 682 | regulator-always-on; |
| 683 | regulator-boot-on; |
| 684 | ams,external-control = <1>; |
| 685 | }; |
| 686 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 687 | vdd_1v35_lp0: sd2 { |
| 688 | regulator-name = "+1.35V_LP0(sd2)"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 689 | regulator-min-microvolt = <1350000>; |
| 690 | regulator-max-microvolt = <1350000>; |
| 691 | regulator-always-on; |
| 692 | regulator-boot-on; |
| 693 | }; |
| 694 | |
| 695 | sd3 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 696 | regulator-name = "+1.35V_LP0(sd3)"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 697 | regulator-min-microvolt = <1350000>; |
| 698 | regulator-max-microvolt = <1350000>; |
| 699 | regulator-always-on; |
| 700 | regulator-boot-on; |
| 701 | }; |
| 702 | |
| 703 | sd4 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 704 | regulator-name = "+1.05V_RUN"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 705 | regulator-min-microvolt = <1050000>; |
| 706 | regulator-max-microvolt = <1050000>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 707 | }; |
| 708 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 709 | vddio_1v8: sd5 { |
| 710 | regulator-name = "+1.8V_VDDIO"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 711 | regulator-min-microvolt = <1800000>; |
| 712 | regulator-max-microvolt = <1800000>; |
| 713 | regulator-boot-on; |
| 714 | regulator-always-on; |
| 715 | }; |
| 716 | |
| 717 | sd6 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 718 | regulator-name = "+VDD_GPU_AP"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 719 | regulator-min-microvolt = <650000>; |
| 720 | regulator-max-microvolt = <1200000>; |
| 721 | regulator-min-microamp = <3500000>; |
| 722 | regulator-max-microamp = <3500000>; |
| 723 | regulator-boot-on; |
| 724 | regulator-always-on; |
| 725 | }; |
| 726 | |
| 727 | ldo0 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 728 | regulator-name = "+1.05V_RUN_AVDD"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 729 | regulator-min-microvolt = <1050000>; |
| 730 | regulator-max-microvolt = <1050000>; |
| 731 | regulator-boot-on; |
| 732 | regulator-always-on; |
| 733 | ams,external-control = <1>; |
| 734 | }; |
| 735 | |
| 736 | ldo1 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 737 | regulator-name = "+1.8V_RUN_CAM"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 738 | regulator-min-microvolt = <1800000>; |
| 739 | regulator-max-microvolt = <1800000>; |
| 740 | }; |
| 741 | |
| 742 | ldo2 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 743 | regulator-name = "+1.2V_GEN_AVDD"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 744 | regulator-min-microvolt = <1200000>; |
| 745 | regulator-max-microvolt = <1200000>; |
| 746 | regulator-boot-on; |
| 747 | regulator-always-on; |
| 748 | }; |
| 749 | |
| 750 | ldo3 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 751 | regulator-name = "+1.00V_LP0_VDD_RTC"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 752 | regulator-min-microvolt = <1000000>; |
| 753 | regulator-max-microvolt = <1000000>; |
| 754 | regulator-boot-on; |
| 755 | regulator-always-on; |
| 756 | ams,enable-tracking; |
| 757 | }; |
| 758 | |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 759 | vdd_run_cam: ldo4 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 760 | regulator-name = "+3.3V_RUN_CAM"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 761 | regulator-min-microvolt = <2800000>; |
| 762 | regulator-max-microvolt = <2800000>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 763 | }; |
| 764 | |
| 765 | ldo5 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 766 | regulator-name = "+1.2V_RUN_CAM_FRONT"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 767 | regulator-min-microvolt = <1200000>; |
| 768 | regulator-max-microvolt = <1200000>; |
| 769 | }; |
| 770 | |
Thierry Reding | 4989b43 | 2014-02-28 17:40:21 +0100 | [diff] [blame] | 771 | vddio_sdmmc3: ldo6 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 772 | regulator-name = "+VDDIO_SDMMC3"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 773 | regulator-min-microvolt = <1800000>; |
| 774 | regulator-max-microvolt = <3300000>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 775 | }; |
| 776 | |
| 777 | ldo7 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 778 | regulator-name = "+1.05V_RUN_CAM_REAR"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 779 | regulator-min-microvolt = <1050000>; |
| 780 | regulator-max-microvolt = <1050000>; |
| 781 | }; |
| 782 | |
| 783 | ldo9 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 784 | regulator-name = "+2.8V_RUN_TOUCH"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 785 | regulator-min-microvolt = <2800000>; |
| 786 | regulator-max-microvolt = <2800000>; |
| 787 | }; |
| 788 | |
| 789 | ldo10 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 790 | regulator-name = "+2.8V_RUN_CAM_AF"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 791 | regulator-min-microvolt = <2800000>; |
| 792 | regulator-max-microvolt = <2800000>; |
| 793 | }; |
| 794 | |
| 795 | ldo11 { |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 796 | regulator-name = "+1.8V_RUN_VPP_FUSE"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 797 | regulator-min-microvolt = <1800000>; |
| 798 | regulator-max-microvolt = <1800000>; |
| 799 | }; |
| 800 | }; |
| 801 | }; |
Stephen Warren | 9d5b250 | 2013-12-03 16:44:35 -0700 | [diff] [blame] | 802 | }; |
| 803 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 804 | spi@0,7000d400 { |
Thierry Reding | 146db0e | 2013-12-19 17:06:19 +0100 | [diff] [blame] | 805 | status = "okay"; |
| 806 | |
| 807 | cros-ec@0 { |
| 808 | compatible = "google,cros-ec-spi"; |
| 809 | spi-max-frequency = <4000000>; |
| 810 | interrupt-parent = <&gpio>; |
| 811 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; |
| 812 | reg = <0>; |
| 813 | |
| 814 | google,cros-ec-spi-msg-delay = <2000>; |
| 815 | |
| 816 | cros-ec-keyb { |
| 817 | compatible = "google,cros-ec-keyb"; |
| 818 | keypad,num-rows = <8>; |
| 819 | keypad,num-columns = <13>; |
| 820 | google,needs-ghost-filter; |
| 821 | |
| 822 | linux,keymap = < |
| 823 | MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) |
| 824 | MATRIX_KEY(0x00, 0x02, KEY_F1) |
| 825 | MATRIX_KEY(0x00, 0x03, KEY_B) |
| 826 | MATRIX_KEY(0x00, 0x04, KEY_F10) |
| 827 | MATRIX_KEY(0x00, 0x06, KEY_N) |
| 828 | MATRIX_KEY(0x00, 0x08, KEY_EQUAL) |
| 829 | MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) |
| 830 | |
| 831 | MATRIX_KEY(0x01, 0x01, KEY_ESC) |
| 832 | MATRIX_KEY(0x01, 0x02, KEY_F4) |
| 833 | MATRIX_KEY(0x01, 0x03, KEY_G) |
| 834 | MATRIX_KEY(0x01, 0x04, KEY_F7) |
| 835 | MATRIX_KEY(0x01, 0x06, KEY_H) |
| 836 | MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) |
| 837 | MATRIX_KEY(0x01, 0x09, KEY_F9) |
| 838 | MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) |
| 839 | |
| 840 | MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) |
| 841 | MATRIX_KEY(0x02, 0x01, KEY_TAB) |
| 842 | MATRIX_KEY(0x02, 0x02, KEY_F3) |
| 843 | MATRIX_KEY(0x02, 0x03, KEY_T) |
| 844 | MATRIX_KEY(0x02, 0x04, KEY_F6) |
| 845 | MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) |
| 846 | MATRIX_KEY(0x02, 0x06, KEY_Y) |
| 847 | MATRIX_KEY(0x02, 0x07, KEY_102ND) |
| 848 | MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) |
| 849 | MATRIX_KEY(0x02, 0x09, KEY_F8) |
| 850 | |
| 851 | MATRIX_KEY(0x03, 0x01, KEY_GRAVE) |
| 852 | MATRIX_KEY(0x03, 0x02, KEY_F2) |
| 853 | MATRIX_KEY(0x03, 0x03, KEY_5) |
| 854 | MATRIX_KEY(0x03, 0x04, KEY_F5) |
| 855 | MATRIX_KEY(0x03, 0x06, KEY_6) |
| 856 | MATRIX_KEY(0x03, 0x08, KEY_MINUS) |
| 857 | MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) |
| 858 | |
| 859 | MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) |
| 860 | MATRIX_KEY(0x04, 0x01, KEY_A) |
| 861 | MATRIX_KEY(0x04, 0x02, KEY_D) |
| 862 | MATRIX_KEY(0x04, 0x03, KEY_F) |
| 863 | MATRIX_KEY(0x04, 0x04, KEY_S) |
| 864 | MATRIX_KEY(0x04, 0x05, KEY_K) |
| 865 | MATRIX_KEY(0x04, 0x06, KEY_J) |
| 866 | MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) |
| 867 | MATRIX_KEY(0x04, 0x09, KEY_L) |
| 868 | MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) |
| 869 | MATRIX_KEY(0x04, 0x0b, KEY_ENTER) |
| 870 | |
| 871 | MATRIX_KEY(0x05, 0x01, KEY_Z) |
| 872 | MATRIX_KEY(0x05, 0x02, KEY_C) |
| 873 | MATRIX_KEY(0x05, 0x03, KEY_V) |
| 874 | MATRIX_KEY(0x05, 0x04, KEY_X) |
| 875 | MATRIX_KEY(0x05, 0x05, KEY_COMMA) |
| 876 | MATRIX_KEY(0x05, 0x06, KEY_M) |
| 877 | MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) |
| 878 | MATRIX_KEY(0x05, 0x08, KEY_SLASH) |
| 879 | MATRIX_KEY(0x05, 0x09, KEY_DOT) |
| 880 | MATRIX_KEY(0x05, 0x0b, KEY_SPACE) |
| 881 | |
| 882 | MATRIX_KEY(0x06, 0x01, KEY_1) |
| 883 | MATRIX_KEY(0x06, 0x02, KEY_3) |
| 884 | MATRIX_KEY(0x06, 0x03, KEY_4) |
| 885 | MATRIX_KEY(0x06, 0x04, KEY_2) |
| 886 | MATRIX_KEY(0x06, 0x05, KEY_8) |
| 887 | MATRIX_KEY(0x06, 0x06, KEY_7) |
| 888 | MATRIX_KEY(0x06, 0x08, KEY_0) |
| 889 | MATRIX_KEY(0x06, 0x09, KEY_9) |
| 890 | MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) |
| 891 | MATRIX_KEY(0x06, 0x0b, KEY_DOWN) |
| 892 | MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) |
| 893 | |
| 894 | MATRIX_KEY(0x07, 0x01, KEY_Q) |
| 895 | MATRIX_KEY(0x07, 0x02, KEY_E) |
| 896 | MATRIX_KEY(0x07, 0x03, KEY_R) |
| 897 | MATRIX_KEY(0x07, 0x04, KEY_W) |
| 898 | MATRIX_KEY(0x07, 0x05, KEY_I) |
| 899 | MATRIX_KEY(0x07, 0x06, KEY_U) |
| 900 | MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) |
| 901 | MATRIX_KEY(0x07, 0x08, KEY_P) |
| 902 | MATRIX_KEY(0x07, 0x09, KEY_O) |
| 903 | MATRIX_KEY(0x07, 0x0b, KEY_UP) |
| 904 | MATRIX_KEY(0x07, 0x0c, KEY_LEFT) |
| 905 | >; |
| 906 | }; |
| 907 | }; |
| 908 | }; |
| 909 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 910 | spi@0,7000da00 { |
Stephen Warren | 11e5b4f | 2014-02-18 15:03:21 -0700 | [diff] [blame] | 911 | status = "okay"; |
| 912 | spi-max-frequency = <25000000>; |
| 913 | spi-flash@0 { |
| 914 | compatible = "winbond,w25q32dw"; |
| 915 | reg = <0>; |
| 916 | spi-max-frequency = <20000000>; |
| 917 | }; |
| 918 | }; |
| 919 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 920 | pmc@0,7000e400 { |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 921 | nvidia,invert-interrupt; |
Joseph Lo | 6ec1d12 | 2013-10-11 17:58:39 +0800 | [diff] [blame] | 922 | nvidia,suspend-mode = <1>; |
| 923 | nvidia,cpu-pwr-good-time = <500>; |
| 924 | nvidia,cpu-pwr-off-time = <300>; |
| 925 | nvidia,core-pwr-good-time = <641 3845>; |
| 926 | nvidia,core-pwr-off-time = <61036>; |
| 927 | nvidia,core-power-req-active-high; |
| 928 | nvidia,sys-clock-req-active-high; |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 929 | }; |
Joseph Lo | 3b86baf | 2013-10-08 15:47:40 +0800 | [diff] [blame] | 930 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 931 | sdhci@0,700b0400 { |
Stephen Warren | 784c744 | 2013-10-31 17:23:05 -0600 | [diff] [blame] | 932 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| 933 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
| 934 | status = "okay"; |
| 935 | bus-width = <4>; |
Thierry Reding | 4989b43 | 2014-02-28 17:40:21 +0100 | [diff] [blame] | 936 | vmmc-supply = <&vddio_sdmmc3>; |
Stephen Warren | 784c744 | 2013-10-31 17:23:05 -0600 | [diff] [blame] | 937 | }; |
| 938 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 939 | sdhci@0,700b0600 { |
Stephen Warren | 784c744 | 2013-10-31 17:23:05 -0600 | [diff] [blame] | 940 | status = "okay"; |
| 941 | bus-width = <8>; |
| 942 | }; |
| 943 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 944 | ahub@0,70300000 { |
| 945 | i2s@0,70301100 { |
Stephen Warren | b0e1cae | 2013-12-03 17:26:12 -0700 | [diff] [blame] | 946 | status = "okay"; |
| 947 | }; |
| 948 | }; |
| 949 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 950 | usb@0,7d000000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 951 | status = "okay"; |
| 952 | }; |
| 953 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 954 | usb-phy@0,7d000000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 955 | status = "okay"; |
| 956 | vbus-supply = <&vdd_usb1_vbus>; |
| 957 | }; |
| 958 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 959 | usb@0,7d004000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 960 | status = "okay"; |
| 961 | }; |
| 962 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 963 | usb-phy@0,7d004000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 964 | status = "okay"; |
| 965 | vbus-supply = <&vdd_run_cam>; |
| 966 | }; |
| 967 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 968 | usb@0,7d008000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 969 | status = "okay"; |
| 970 | }; |
| 971 | |
Stephen Warren | e30cb23 | 2014-03-03 14:51:15 -0700 | [diff] [blame] | 972 | usb-phy@0,7d008000 { |
Thierry Reding | 431b7be | 2014-02-28 17:40:26 +0100 | [diff] [blame] | 973 | status = "okay"; |
| 974 | vbus-supply = <&vdd_usb3_vbus>; |
| 975 | }; |
| 976 | |
Thierry Reding | 40e231c | 2014-02-28 17:40:24 +0100 | [diff] [blame] | 977 | backlight: backlight { |
| 978 | compatible = "pwm-backlight"; |
| 979 | |
| 980 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 981 | power-supply = <&vdd_led>; |
| 982 | pwms = <&pwm 1 1000000>; |
| 983 | |
| 984 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 985 | default-brightness-level = <6>; |
| 986 | }; |
| 987 | |
Joseph Lo | 3b86baf | 2013-10-08 15:47:40 +0800 | [diff] [blame] | 988 | clocks { |
| 989 | compatible = "simple-bus"; |
| 990 | #address-cells = <1>; |
| 991 | #size-cells = <0>; |
| 992 | |
| 993 | clk32k_in: clock@0 { |
| 994 | compatible = "fixed-clock"; |
Thierry Reding | 4b35660 | 2014-02-28 17:40:27 +0100 | [diff] [blame] | 995 | reg = <0>; |
Joseph Lo | 3b86baf | 2013-10-08 15:47:40 +0800 | [diff] [blame] | 996 | #clock-cells = <0>; |
| 997 | clock-frequency = <32768>; |
| 998 | }; |
| 999 | }; |
Stephen Warren | b0e1cae | 2013-12-03 17:26:12 -0700 | [diff] [blame] | 1000 | |
Thierry Reding | 3f748d4 | 2013-12-19 17:06:20 +0100 | [diff] [blame] | 1001 | gpio-keys { |
| 1002 | compatible = "gpio-keys"; |
| 1003 | |
| 1004 | power { |
| 1005 | label = "Power"; |
| 1006 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 1007 | linux,code = <KEY_POWER>; |
| 1008 | debounce-interval = <10>; |
| 1009 | gpio-key,wakeup; |
| 1010 | }; |
| 1011 | }; |
| 1012 | |
Thierry Reding | 40e231c | 2014-02-28 17:40:24 +0100 | [diff] [blame] | 1013 | panel: panel { |
| 1014 | compatible = "lg,lp129qe", "simple-panel"; |
| 1015 | |
| 1016 | backlight = <&backlight>; |
| 1017 | ddc-i2c-bus = <&dpaux>; |
| 1018 | }; |
| 1019 | |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1020 | regulators { |
| 1021 | compatible = "simple-bus"; |
| 1022 | #address-cells = <1>; |
| 1023 | #size-cells = <0>; |
| 1024 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1025 | vdd_mux: regulator@0 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1026 | compatible = "regulator-fixed"; |
| 1027 | reg = <0>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1028 | regulator-name = "+VDD_MUX"; |
| 1029 | regulator-min-microvolt = <12000000>; |
| 1030 | regulator-max-microvolt = <12000000>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1031 | regulator-always-on; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1032 | regulator-boot-on; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1033 | }; |
| 1034 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1035 | vdd_5v0_sys: regulator@1 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1036 | compatible = "regulator-fixed"; |
| 1037 | reg = <1>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1038 | regulator-name = "+5V_SYS"; |
| 1039 | regulator-min-microvolt = <5000000>; |
| 1040 | regulator-max-microvolt = <5000000>; |
| 1041 | regulator-always-on; |
| 1042 | regulator-boot-on; |
| 1043 | vin-supply = <&vdd_mux>; |
| 1044 | }; |
| 1045 | |
| 1046 | vdd_3v3_sys: regulator@2 { |
| 1047 | compatible = "regulator-fixed"; |
| 1048 | reg = <2>; |
| 1049 | regulator-name = "+3.3V_SYS"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1050 | regulator-min-microvolt = <3300000>; |
| 1051 | regulator-max-microvolt = <3300000>; |
| 1052 | regulator-always-on; |
| 1053 | regulator-boot-on; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1054 | vin-supply = <&vdd_mux>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1055 | }; |
| 1056 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1057 | vdd_3v3_run: regulator@3 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1058 | compatible = "regulator-fixed"; |
| 1059 | reg = <3>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1060 | regulator-name = "+3.3V_RUN"; |
| 1061 | regulator-min-microvolt = <3300000>; |
| 1062 | regulator-max-microvolt = <3300000>; |
Stephen Warren | c7fe767 | 2014-04-15 16:27:01 -0600 | [diff] [blame^] | 1063 | regulator-always-on; |
| 1064 | regulator-boot-on; |
Thierry Reding | fdc44f9 | 2014-02-28 17:40:28 +0100 | [diff] [blame] | 1065 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1066 | enable-active-high; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1067 | vin-supply = <&vdd_3v3_sys>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1068 | }; |
| 1069 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1070 | vdd_3v3_hdmi: regulator@4 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1071 | compatible = "regulator-fixed"; |
| 1072 | reg = <4>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1073 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1074 | regulator-min-microvolt = <3300000>; |
| 1075 | regulator-max-microvolt = <3300000>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1076 | vin-supply = <&vdd_3v3_run>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1077 | }; |
| 1078 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1079 | vdd_led: regulator@5 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1080 | compatible = "regulator-fixed"; |
| 1081 | reg = <5>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1082 | regulator-name = "+VDD_LED"; |
| 1083 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1084 | enable-active-high; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1085 | vin-supply = <&vdd_mux>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1086 | }; |
| 1087 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1088 | vdd_5v0_ts: regulator@6 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1089 | compatible = "regulator-fixed"; |
| 1090 | reg = <6>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1091 | regulator-name = "+5V_VDD_TS_SW"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1092 | regulator-min-microvolt = <5000000>; |
| 1093 | regulator-max-microvolt = <5000000>; |
| 1094 | regulator-boot-on; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1095 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1096 | enable-active-high; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1097 | vin-supply = <&vdd_5v0_sys>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1098 | }; |
| 1099 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1100 | vdd_usb1_vbus: regulator@7 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1101 | compatible = "regulator-fixed"; |
| 1102 | reg = <7>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1103 | regulator-name = "+5V_USB_HS"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1104 | regulator-min-microvolt = <5000000>; |
| 1105 | regulator-max-microvolt = <5000000>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1106 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1107 | enable-active-high; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1108 | gpio-open-drain; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1109 | vin-supply = <&vdd_5v0_sys>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1110 | }; |
| 1111 | |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1112 | vdd_usb3_vbus: regulator@8 { |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1113 | compatible = "regulator-fixed"; |
| 1114 | reg = <8>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1115 | regulator-name = "+5V_USB_SS"; |
| 1116 | regulator-min-microvolt = <5000000>; |
| 1117 | regulator-max-microvolt = <5000000>; |
| 1118 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; |
| 1119 | enable-active-high; |
| 1120 | gpio-open-drain; |
| 1121 | vin-supply = <&vdd_5v0_sys>; |
| 1122 | }; |
| 1123 | |
| 1124 | vdd_3v3_panel: regulator@9 { |
| 1125 | compatible = "regulator-fixed"; |
| 1126 | reg = <9>; |
| 1127 | regulator-name = "+3.3V_PANEL"; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1128 | regulator-min-microvolt = <3300000>; |
| 1129 | regulator-max-microvolt = <3300000>; |
Thierry Reding | fdc44f9 | 2014-02-28 17:40:28 +0100 | [diff] [blame] | 1130 | gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1131 | enable-active-high; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1132 | vin-supply = <&vdd_3v3_run>; |
| 1133 | }; |
| 1134 | |
| 1135 | vdd_3v3_lp0: regulator@10 { |
| 1136 | compatible = "regulator-fixed"; |
| 1137 | reg = <10>; |
| 1138 | regulator-name = "+3.3V_LP0"; |
| 1139 | regulator-min-microvolt = <3300000>; |
| 1140 | regulator-max-microvolt = <3300000>; |
| 1141 | /* |
| 1142 | * TODO: find a way to wire this up with the USB EHCI |
| 1143 | * controllers so that it can be enabled on demand. |
| 1144 | */ |
| 1145 | regulator-always-on; |
Thierry Reding | fdc44f9 | 2014-02-28 17:40:28 +0100 | [diff] [blame] | 1146 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
Thierry Reding | af144b8 | 2014-02-28 17:40:20 +0100 | [diff] [blame] | 1147 | enable-active-high; |
| 1148 | vin-supply = <&vdd_3v3_sys>; |
Laxman Dewangan | fcacaba | 2013-12-18 18:22:59 +0530 | [diff] [blame] | 1149 | }; |
| 1150 | }; |
| 1151 | |
Stephen Warren | b0e1cae | 2013-12-03 17:26:12 -0700 | [diff] [blame] | 1152 | sound { |
| 1153 | compatible = "nvidia,tegra-audio-max98090-venice2", |
| 1154 | "nvidia,tegra-audio-max98090"; |
| 1155 | nvidia,model = "NVIDIA Tegra Venice2"; |
| 1156 | |
| 1157 | nvidia,audio-routing = |
| 1158 | "Headphones", "HPR", |
| 1159 | "Headphones", "HPL", |
| 1160 | "Speakers", "SPKR", |
| 1161 | "Speakers", "SPKL", |
| 1162 | "Mic Jack", "MICBIAS", |
| 1163 | "IN34", "Mic Jack"; |
| 1164 | |
| 1165 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 1166 | nvidia,audio-codec = <&acodec>; |
| 1167 | |
| 1168 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, |
| 1169 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
| 1170 | <&tegra_car TEGRA124_CLK_EXTERN1>; |
| 1171 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 1172 | }; |
Joseph Lo | a1425d4 | 2013-10-08 12:50:06 +0800 | [diff] [blame] | 1173 | }; |