Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* -*- mode: c; c-basic-offset: 8 -*- */ |
| 2 | |
| 3 | /* Copyright (C) 1999,2001 |
| 4 | * |
| 5 | * Author: J.E.J.Bottomley@HansenPartnership.com |
| 6 | * |
| 7 | * linux/arch/i386/kernel/voyager_smp.c |
| 8 | * |
| 9 | * This file provides all the same external entries as smp.c but uses |
| 10 | * the voyager hal to provide the functionality |
| 11 | */ |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 12 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/mm.h> |
| 14 | #include <linux/kernel_stat.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/mc146818rtc.h> |
| 17 | #include <linux/cache.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/smp_lock.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/bootmem.h> |
| 23 | #include <linux/completion.h> |
| 24 | #include <asm/desc.h> |
| 25 | #include <asm/voyager.h> |
| 26 | #include <asm/vic.h> |
| 27 | #include <asm/mtrr.h> |
| 28 | #include <asm/pgalloc.h> |
| 29 | #include <asm/tlbflush.h> |
| 30 | #include <asm/arch_hooks.h> |
| 31 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | /* TLB state -- visible externally, indexed physically */ |
| 33 | DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 }; |
| 34 | |
| 35 | /* CPU IRQ affinity -- set to all ones initially */ |
| 36 | static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL }; |
| 37 | |
| 38 | /* per CPU data structure (for /proc/cpuinfo et al), visible externally |
| 39 | * indexed physically */ |
| 40 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 41 | EXPORT_SYMBOL(cpu_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
| 43 | /* physical ID of the CPU used to boot the system */ |
| 44 | unsigned char boot_cpu_id; |
| 45 | |
| 46 | /* The memory line addresses for the Quad CPIs */ |
| 47 | struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned; |
| 48 | |
| 49 | /* The masks for the Extended VIC processors, filled in by cat_init */ |
| 50 | __u32 voyager_extended_vic_processors = 0; |
| 51 | |
| 52 | /* Masks for the extended Quad processors which cannot be VIC booted */ |
| 53 | __u32 voyager_allowed_boot_processors = 0; |
| 54 | |
| 55 | /* The mask for the Quad Processors (both extended and non-extended) */ |
| 56 | __u32 voyager_quad_processors = 0; |
| 57 | |
| 58 | /* Total count of live CPUs, used in process.c to display |
| 59 | * the CPU information and in irq.c for the per CPU irq |
| 60 | * activity count. Finally exported by i386_ksyms.c */ |
| 61 | static int voyager_extended_cpus = 1; |
| 62 | |
| 63 | /* Have we found an SMP box - used by time.c to do the profiling |
| 64 | interrupt for timeslicing; do not set to 1 until the per CPU timer |
| 65 | interrupt is active */ |
| 66 | int smp_found_config = 0; |
| 67 | |
| 68 | /* Used for the invalidate map that's also checked in the spinlock */ |
| 69 | static volatile unsigned long smp_invalidate_needed; |
| 70 | |
| 71 | /* Bitmask of currently online CPUs - used by setup.c for |
| 72 | /proc/cpuinfo, visible externally but still physical */ |
| 73 | cpumask_t cpu_online_map = CPU_MASK_NONE; |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 74 | EXPORT_SYMBOL(cpu_online_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
| 76 | /* Bitmask of CPUs present in the system - exported by i386_syms.c, used |
| 77 | * by scheduler but indexed physically */ |
| 78 | cpumask_t phys_cpu_present_map = CPU_MASK_NONE; |
| 79 | |
| 80 | |
| 81 | /* The internal functions */ |
| 82 | static void send_CPI(__u32 cpuset, __u8 cpi); |
| 83 | static void ack_CPI(__u8 cpi); |
| 84 | static int ack_QIC_CPI(__u8 cpi); |
| 85 | static void ack_special_QIC_CPI(__u8 cpi); |
| 86 | static void ack_VIC_CPI(__u8 cpi); |
| 87 | static void send_CPI_allbutself(__u8 cpi); |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 88 | static void mask_vic_irq(unsigned int irq); |
| 89 | static void unmask_vic_irq(unsigned int irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | static unsigned int startup_vic_irq(unsigned int irq); |
| 91 | static void enable_local_vic_irq(unsigned int irq); |
| 92 | static void disable_local_vic_irq(unsigned int irq); |
| 93 | static void before_handle_vic_irq(unsigned int irq); |
| 94 | static void after_handle_vic_irq(unsigned int irq); |
| 95 | static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask); |
| 96 | static void ack_vic_irq(unsigned int irq); |
| 97 | static void vic_enable_cpi(void); |
| 98 | static void do_boot_cpu(__u8 cpuid); |
| 99 | static void do_quad_bootstrap(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | |
| 101 | int hard_smp_processor_id(void); |
Fernando Vazquez | 2654c08 | 2006-09-30 23:29:08 -0700 | [diff] [blame] | 102 | int safe_smp_processor_id(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
| 104 | /* Inline functions */ |
| 105 | static inline void |
| 106 | send_one_QIC_CPI(__u8 cpu, __u8 cpi) |
| 107 | { |
| 108 | voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi = |
| 109 | (smp_processor_id() << 16) + cpi; |
| 110 | } |
| 111 | |
| 112 | static inline void |
| 113 | send_QIC_CPI(__u32 cpuset, __u8 cpi) |
| 114 | { |
| 115 | int cpu; |
| 116 | |
| 117 | for_each_online_cpu(cpu) { |
| 118 | if(cpuset & (1<<cpu)) { |
| 119 | #ifdef VOYAGER_DEBUG |
| 120 | if(!cpu_isset(cpu, cpu_online_map)) |
| 121 | VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu)); |
| 122 | #endif |
| 123 | send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET); |
| 124 | } |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | static inline void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 129 | wrapper_smp_local_timer_interrupt(void) |
Dominik Hackl | 6431e6a | 2005-05-24 19:29:46 -0700 | [diff] [blame] | 130 | { |
| 131 | irq_enter(); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 132 | smp_local_timer_interrupt(); |
Dominik Hackl | 6431e6a | 2005-05-24 19:29:46 -0700 | [diff] [blame] | 133 | irq_exit(); |
| 134 | } |
| 135 | |
| 136 | static inline void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | send_one_CPI(__u8 cpu, __u8 cpi) |
| 138 | { |
| 139 | if(voyager_quad_processors & (1<<cpu)) |
| 140 | send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET); |
| 141 | else |
| 142 | send_CPI(1<<cpu, cpi); |
| 143 | } |
| 144 | |
| 145 | static inline void |
| 146 | send_CPI_allbutself(__u8 cpi) |
| 147 | { |
| 148 | __u8 cpu = smp_processor_id(); |
| 149 | __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu); |
| 150 | send_CPI(mask, cpi); |
| 151 | } |
| 152 | |
| 153 | static inline int |
| 154 | is_cpu_quad(void) |
| 155 | { |
| 156 | __u8 cpumask = inb(VIC_PROC_WHO_AM_I); |
| 157 | return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER); |
| 158 | } |
| 159 | |
| 160 | static inline int |
| 161 | is_cpu_extended(void) |
| 162 | { |
| 163 | __u8 cpu = hard_smp_processor_id(); |
| 164 | |
| 165 | return(voyager_extended_vic_processors & (1<<cpu)); |
| 166 | } |
| 167 | |
| 168 | static inline int |
| 169 | is_cpu_vic_boot(void) |
| 170 | { |
| 171 | __u8 cpu = hard_smp_processor_id(); |
| 172 | |
| 173 | return(voyager_extended_vic_processors |
| 174 | & voyager_allowed_boot_processors & (1<<cpu)); |
| 175 | } |
| 176 | |
| 177 | |
| 178 | static inline void |
| 179 | ack_CPI(__u8 cpi) |
| 180 | { |
| 181 | switch(cpi) { |
| 182 | case VIC_CPU_BOOT_CPI: |
| 183 | if(is_cpu_quad() && !is_cpu_vic_boot()) |
| 184 | ack_QIC_CPI(cpi); |
| 185 | else |
| 186 | ack_VIC_CPI(cpi); |
| 187 | break; |
| 188 | case VIC_SYS_INT: |
| 189 | case VIC_CMN_INT: |
| 190 | /* These are slightly strange. Even on the Quad card, |
| 191 | * They are vectored as VIC CPIs */ |
| 192 | if(is_cpu_quad()) |
| 193 | ack_special_QIC_CPI(cpi); |
| 194 | else |
| 195 | ack_VIC_CPI(cpi); |
| 196 | break; |
| 197 | default: |
| 198 | printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi); |
| 199 | break; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | /* local variables */ |
| 204 | |
| 205 | /* The VIC IRQ descriptors -- these look almost identical to the |
| 206 | * 8259 IRQs except that masks and things must be kept per processor |
| 207 | */ |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 208 | static struct irq_chip vic_chip = { |
| 209 | .name = "VIC", |
| 210 | .startup = startup_vic_irq, |
| 211 | .mask = mask_vic_irq, |
| 212 | .unmask = unmask_vic_irq, |
| 213 | .set_affinity = set_vic_irq_affinity, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | /* used to count up as CPUs are brought on line (starts at 0) */ |
| 217 | static int cpucount = 0; |
| 218 | |
| 219 | /* steal a page from the bottom of memory for the trampoline and |
| 220 | * squirrel its address away here. This will be in kernel virtual |
| 221 | * space */ |
| 222 | static __u32 trampoline_base; |
| 223 | |
| 224 | /* The per cpu profile stuff - used in smp_local_timer_interrupt */ |
| 225 | static DEFINE_PER_CPU(int, prof_multiplier) = 1; |
| 226 | static DEFINE_PER_CPU(int, prof_old_multiplier) = 1; |
| 227 | static DEFINE_PER_CPU(int, prof_counter) = 1; |
| 228 | |
| 229 | /* the map used to check if a CPU has booted */ |
| 230 | static __u32 cpu_booted_map; |
| 231 | |
| 232 | /* the synchronize flag used to hold all secondary CPUs spinning in |
| 233 | * a tight loop until the boot sequence is ready for them */ |
| 234 | static cpumask_t smp_commenced_mask = CPU_MASK_NONE; |
| 235 | |
| 236 | /* This is for the new dynamic CPU boot code */ |
| 237 | cpumask_t cpu_callin_map = CPU_MASK_NONE; |
| 238 | cpumask_t cpu_callout_map = CPU_MASK_NONE; |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 239 | EXPORT_SYMBOL(cpu_callout_map); |
Andrew Morton | 7a8ef1c | 2006-02-10 01:51:08 -0800 | [diff] [blame] | 240 | cpumask_t cpu_possible_map = CPU_MASK_NONE; |
Zwane Mwaikambo | 4ad8d38 | 2005-09-03 15:56:51 -0700 | [diff] [blame] | 241 | EXPORT_SYMBOL(cpu_possible_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | |
| 243 | /* The per processor IRQ masks (these are usually kept in sync) */ |
| 244 | static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned; |
| 245 | |
| 246 | /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */ |
| 247 | static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 }; |
| 248 | |
| 249 | /* Lock for enable/disable of VIC interrupts */ |
| 250 | static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock); |
| 251 | |
| 252 | /* The boot processor is correctly set up in PC mode when it |
| 253 | * comes up, but the secondaries need their master/slave 8259 |
| 254 | * pairs initializing correctly */ |
| 255 | |
| 256 | /* Interrupt counters (per cpu) and total - used to try to |
| 257 | * even up the interrupt handling routines */ |
| 258 | static long vic_intr_total = 0; |
| 259 | static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 }; |
| 260 | static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 }; |
| 261 | |
| 262 | /* Since we can only use CPI0, we fake all the other CPIs */ |
| 263 | static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned; |
| 264 | |
| 265 | /* debugging routine to read the isr of the cpu's pic */ |
| 266 | static inline __u16 |
| 267 | vic_read_isr(void) |
| 268 | { |
| 269 | __u16 isr; |
| 270 | |
| 271 | outb(0x0b, 0xa0); |
| 272 | isr = inb(0xa0) << 8; |
| 273 | outb(0x0b, 0x20); |
| 274 | isr |= inb(0x20); |
| 275 | |
| 276 | return isr; |
| 277 | } |
| 278 | |
| 279 | static __init void |
| 280 | qic_setup(void) |
| 281 | { |
| 282 | if(!is_cpu_quad()) { |
| 283 | /* not a quad, no setup */ |
| 284 | return; |
| 285 | } |
| 286 | outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0); |
| 287 | outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1); |
| 288 | |
| 289 | if(is_cpu_extended()) { |
| 290 | /* the QIC duplicate of the VIC base register */ |
| 291 | outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER); |
| 292 | outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER); |
| 293 | |
| 294 | /* FIXME: should set up the QIC timer and memory parity |
| 295 | * error vectors here */ |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | static __init void |
| 300 | vic_setup_pic(void) |
| 301 | { |
| 302 | outb(1, VIC_REDIRECT_REGISTER_1); |
| 303 | /* clear the claim registers for dynamic routing */ |
| 304 | outb(0, VIC_CLAIM_REGISTER_0); |
| 305 | outb(0, VIC_CLAIM_REGISTER_1); |
| 306 | |
| 307 | outb(0, VIC_PRIORITY_REGISTER); |
| 308 | /* Set the Primary and Secondary Microchannel vector |
| 309 | * bases to be the same as the ordinary interrupts |
| 310 | * |
| 311 | * FIXME: This would be more efficient using separate |
| 312 | * vectors. */ |
| 313 | outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE); |
| 314 | outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE); |
| 315 | /* Now initiallise the master PIC belonging to this CPU by |
| 316 | * sending the four ICWs */ |
| 317 | |
| 318 | /* ICW1: level triggered, ICW4 needed */ |
| 319 | outb(0x19, 0x20); |
| 320 | |
| 321 | /* ICW2: vector base */ |
| 322 | outb(FIRST_EXTERNAL_VECTOR, 0x21); |
| 323 | |
| 324 | /* ICW3: slave at line 2 */ |
| 325 | outb(0x04, 0x21); |
| 326 | |
| 327 | /* ICW4: 8086 mode */ |
| 328 | outb(0x01, 0x21); |
| 329 | |
| 330 | /* now the same for the slave PIC */ |
| 331 | |
| 332 | /* ICW1: level trigger, ICW4 needed */ |
| 333 | outb(0x19, 0xA0); |
| 334 | |
| 335 | /* ICW2: slave vector base */ |
| 336 | outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1); |
| 337 | |
| 338 | /* ICW3: slave ID */ |
| 339 | outb(0x02, 0xA1); |
| 340 | |
| 341 | /* ICW4: 8086 mode */ |
| 342 | outb(0x01, 0xA1); |
| 343 | } |
| 344 | |
| 345 | static void |
| 346 | do_quad_bootstrap(void) |
| 347 | { |
| 348 | if(is_cpu_quad() && is_cpu_vic_boot()) { |
| 349 | int i; |
| 350 | unsigned long flags; |
| 351 | __u8 cpuid = hard_smp_processor_id(); |
| 352 | |
| 353 | local_irq_save(flags); |
| 354 | |
| 355 | for(i = 0; i<4; i++) { |
| 356 | /* FIXME: this would be >>3 &0x7 on the 32 way */ |
| 357 | if(((cpuid >> 2) & 0x03) == i) |
| 358 | /* don't lower our own mask! */ |
| 359 | continue; |
| 360 | |
| 361 | /* masquerade as local Quad CPU */ |
| 362 | outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID); |
| 363 | /* enable the startup CPI */ |
| 364 | outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1); |
| 365 | /* restore cpu id */ |
| 366 | outb(0, QIC_PROCESSOR_ID); |
| 367 | } |
| 368 | local_irq_restore(flags); |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | |
| 373 | /* Set up all the basic stuff: read the SMP config and make all the |
| 374 | * SMP information reflect only the boot cpu. All others will be |
| 375 | * brought on-line later. */ |
| 376 | void __init |
| 377 | find_smp_config(void) |
| 378 | { |
| 379 | int i; |
| 380 | |
| 381 | boot_cpu_id = hard_smp_processor_id(); |
| 382 | |
| 383 | printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id); |
| 384 | |
| 385 | /* initialize the CPU structures (moved from smp_boot_cpus) */ |
| 386 | for(i=0; i<NR_CPUS; i++) { |
| 387 | cpu_irq_affinity[i] = ~0; |
| 388 | } |
| 389 | cpu_online_map = cpumask_of_cpu(boot_cpu_id); |
| 390 | |
| 391 | /* The boot CPU must be extended */ |
| 392 | voyager_extended_vic_processors = 1<<boot_cpu_id; |
| 393 | /* initially, all of the first 8 cpu's can boot */ |
| 394 | voyager_allowed_boot_processors = 0xff; |
| 395 | /* set up everything for just this CPU, we can alter |
| 396 | * this as we start the other CPUs later */ |
| 397 | /* now get the CPU disposition from the extended CMOS */ |
| 398 | cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK); |
| 399 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8; |
| 400 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16; |
| 401 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24; |
James Bottomley | f68a106 | 2006-02-24 13:04:11 -0800 | [diff] [blame] | 402 | cpu_possible_map = phys_cpu_present_map; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]); |
| 404 | /* Here we set up the VIC to enable SMP */ |
| 405 | /* enable the CPIs by writing the base vector to their register */ |
| 406 | outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER); |
| 407 | outb(1, VIC_REDIRECT_REGISTER_1); |
| 408 | /* set the claim registers for static routing --- Boot CPU gets |
| 409 | * all interrupts untill all other CPUs started */ |
| 410 | outb(0xff, VIC_CLAIM_REGISTER_0); |
| 411 | outb(0xff, VIC_CLAIM_REGISTER_1); |
| 412 | /* Set the Primary and Secondary Microchannel vector |
| 413 | * bases to be the same as the ordinary interrupts |
| 414 | * |
| 415 | * FIXME: This would be more efficient using separate |
| 416 | * vectors. */ |
| 417 | outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE); |
| 418 | outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE); |
| 419 | |
| 420 | /* Finally tell the firmware that we're driving */ |
| 421 | outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG, |
| 422 | VOYAGER_SUS_IN_CONTROL_PORT); |
| 423 | |
| 424 | current_thread_info()->cpu = boot_cpu_id; |
| 425 | } |
| 426 | |
| 427 | /* |
| 428 | * The bootstrap kernel entry code has set these up. Save them |
| 429 | * for a given CPU, id is physical */ |
| 430 | void __init |
| 431 | smp_store_cpu_info(int id) |
| 432 | { |
| 433 | struct cpuinfo_x86 *c=&cpu_data[id]; |
| 434 | |
| 435 | *c = boot_cpu_data; |
| 436 | |
| 437 | identify_cpu(c); |
| 438 | } |
| 439 | |
| 440 | /* set up the trampoline and return the physical address of the code */ |
| 441 | static __u32 __init |
| 442 | setup_trampoline(void) |
| 443 | { |
| 444 | /* these two are global symbols in trampoline.S */ |
| 445 | extern __u8 trampoline_end[]; |
| 446 | extern __u8 trampoline_data[]; |
| 447 | |
| 448 | memcpy((__u8 *)trampoline_base, trampoline_data, |
| 449 | trampoline_end - trampoline_data); |
| 450 | return virt_to_phys((__u8 *)trampoline_base); |
| 451 | } |
| 452 | |
| 453 | /* Routine initially called when a non-boot CPU is brought online */ |
| 454 | static void __init |
| 455 | start_secondary(void *unused) |
| 456 | { |
| 457 | __u8 cpuid = hard_smp_processor_id(); |
| 458 | /* external functions not defined in the headers */ |
| 459 | extern void calibrate_delay(void); |
| 460 | |
| 461 | cpu_init(); |
| 462 | |
| 463 | /* OK, we're in the routine */ |
| 464 | ack_CPI(VIC_CPU_BOOT_CPI); |
| 465 | |
| 466 | /* setup the 8259 master slave pair belonging to this CPU --- |
| 467 | * we won't actually receive any until the boot CPU |
| 468 | * relinquishes it's static routing mask */ |
| 469 | vic_setup_pic(); |
| 470 | |
| 471 | qic_setup(); |
| 472 | |
| 473 | if(is_cpu_quad() && !is_cpu_vic_boot()) { |
| 474 | /* clear the boot CPI */ |
| 475 | __u8 dummy; |
| 476 | |
| 477 | dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi; |
| 478 | printk("read dummy %d\n", dummy); |
| 479 | } |
| 480 | |
| 481 | /* lower the mask to receive CPIs */ |
| 482 | vic_enable_cpi(); |
| 483 | |
| 484 | VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid)); |
| 485 | |
| 486 | /* enable interrupts */ |
| 487 | local_irq_enable(); |
| 488 | |
| 489 | /* get our bogomips */ |
| 490 | calibrate_delay(); |
| 491 | |
| 492 | /* save our processor parameters */ |
| 493 | smp_store_cpu_info(cpuid); |
| 494 | |
| 495 | /* if we're a quad, we may need to bootstrap other CPUs */ |
| 496 | do_quad_bootstrap(); |
| 497 | |
| 498 | /* FIXME: this is rather a poor hack to prevent the CPU |
| 499 | * activating softirqs while it's supposed to be waiting for |
| 500 | * permission to proceed. Without this, the new per CPU stuff |
| 501 | * in the softirqs will fail */ |
| 502 | local_irq_disable(); |
| 503 | cpu_set(cpuid, cpu_callin_map); |
| 504 | |
| 505 | /* signal that we're done */ |
| 506 | cpu_booted_map = 1; |
| 507 | |
| 508 | while (!cpu_isset(cpuid, smp_commenced_mask)) |
| 509 | rep_nop(); |
| 510 | local_irq_enable(); |
| 511 | |
| 512 | local_flush_tlb(); |
| 513 | |
| 514 | cpu_set(cpuid, cpu_online_map); |
| 515 | wmb(); |
| 516 | cpu_idle(); |
| 517 | } |
| 518 | |
| 519 | |
| 520 | /* Routine to kick start the given CPU and wait for it to report ready |
| 521 | * (or timeout in startup). When this routine returns, the requested |
| 522 | * CPU is either fully running and configured or known to be dead. |
| 523 | * |
| 524 | * We call this routine sequentially 1 CPU at a time, so no need for |
| 525 | * locking */ |
| 526 | |
| 527 | static void __init |
| 528 | do_boot_cpu(__u8 cpu) |
| 529 | { |
| 530 | struct task_struct *idle; |
| 531 | int timeout; |
| 532 | unsigned long flags; |
| 533 | int quad_boot = (1<<cpu) & voyager_quad_processors |
| 534 | & ~( voyager_extended_vic_processors |
| 535 | & voyager_allowed_boot_processors); |
| 536 | |
| 537 | /* For the 486, we can't use the 4Mb page table trick, so |
| 538 | * must map a region of memory */ |
| 539 | #ifdef CONFIG_M486 |
| 540 | int i; |
| 541 | unsigned long *page_table_copies = (unsigned long *) |
| 542 | __get_free_page(GFP_KERNEL); |
| 543 | #endif |
| 544 | pgd_t orig_swapper_pg_dir0; |
| 545 | |
| 546 | /* This is an area in head.S which was used to set up the |
| 547 | * initial kernel stack. We need to alter this to give the |
| 548 | * booting CPU a new stack (taken from its idle process) */ |
| 549 | extern struct { |
| 550 | __u8 *esp; |
| 551 | unsigned short ss; |
| 552 | } stack_start; |
| 553 | /* This is the format of the CPI IDT gate (in real mode) which |
| 554 | * we're hijacking to boot the CPU */ |
| 555 | union IDTFormat { |
| 556 | struct seg { |
| 557 | __u16 Offset; |
| 558 | __u16 Segment; |
| 559 | } idt; |
| 560 | __u32 val; |
| 561 | } hijack_source; |
| 562 | |
| 563 | __u32 *hijack_vector; |
| 564 | __u32 start_phys_address = setup_trampoline(); |
| 565 | |
| 566 | /* There's a clever trick to this: The linux trampoline is |
| 567 | * compiled to begin at absolute location zero, so make the |
| 568 | * address zero but have the data segment selector compensate |
| 569 | * for the actual address */ |
| 570 | hijack_source.idt.Offset = start_phys_address & 0x000F; |
| 571 | hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF; |
| 572 | |
| 573 | cpucount++; |
| 574 | idle = fork_idle(cpu); |
| 575 | if(IS_ERR(idle)) |
| 576 | panic("failed fork for CPU%d", cpu); |
| 577 | idle->thread.eip = (unsigned long) start_secondary; |
| 578 | /* init_tasks (in sched.c) is indexed logically */ |
| 579 | stack_start.esp = (void *) idle->thread.esp; |
| 580 | |
| 581 | irq_ctx_init(cpu); |
| 582 | |
| 583 | /* Note: Don't modify initial ss override */ |
| 584 | VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu, |
| 585 | (unsigned long)hijack_source.val, hijack_source.idt.Segment, |
| 586 | hijack_source.idt.Offset, stack_start.esp)); |
| 587 | /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently |
| 588 | * (so that the booting CPU can find start_32 */ |
| 589 | orig_swapper_pg_dir0 = swapper_pg_dir[0]; |
| 590 | #ifdef CONFIG_M486 |
| 591 | if(page_table_copies == NULL) |
| 592 | panic("No free memory for 486 page tables\n"); |
| 593 | for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++) |
| 594 | page_table_copies[i] = (i * PAGE_SIZE) |
| 595 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; |
| 596 | |
| 597 | ((unsigned long *)swapper_pg_dir)[0] = |
| 598 | ((virt_to_phys(page_table_copies)) & PAGE_MASK) |
| 599 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; |
| 600 | #else |
| 601 | ((unsigned long *)swapper_pg_dir)[0] = |
| 602 | (virt_to_phys(pg0) & PAGE_MASK) |
| 603 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; |
| 604 | #endif |
| 605 | |
| 606 | if(quad_boot) { |
| 607 | printk("CPU %d: non extended Quad boot\n", cpu); |
| 608 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4); |
| 609 | *hijack_vector = hijack_source.val; |
| 610 | } else { |
| 611 | printk("CPU%d: extended VIC boot\n", cpu); |
| 612 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4); |
| 613 | *hijack_vector = hijack_source.val; |
| 614 | /* VIC errata, may also receive interrupt at this address */ |
| 615 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4); |
| 616 | *hijack_vector = hijack_source.val; |
| 617 | } |
| 618 | /* All non-boot CPUs start with interrupts fully masked. Need |
| 619 | * to lower the mask of the CPI we're about to send. We do |
| 620 | * this in the VIC by masquerading as the processor we're |
| 621 | * about to boot and lowering its interrupt mask */ |
| 622 | local_irq_save(flags); |
| 623 | if(quad_boot) { |
| 624 | send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI); |
| 625 | } else { |
| 626 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); |
| 627 | /* here we're altering registers belonging to `cpu' */ |
| 628 | |
| 629 | outb(VIC_BOOT_INTERRUPT_MASK, 0x21); |
| 630 | /* now go back to our original identity */ |
| 631 | outb(boot_cpu_id, VIC_PROCESSOR_ID); |
| 632 | |
| 633 | /* and boot the CPU */ |
| 634 | |
| 635 | send_CPI((1<<cpu), VIC_CPU_BOOT_CPI); |
| 636 | } |
| 637 | cpu_booted_map = 0; |
| 638 | local_irq_restore(flags); |
| 639 | |
| 640 | /* now wait for it to become ready (or timeout) */ |
| 641 | for(timeout = 0; timeout < 50000; timeout++) { |
| 642 | if(cpu_booted_map) |
| 643 | break; |
| 644 | udelay(100); |
| 645 | } |
| 646 | /* reset the page table */ |
| 647 | swapper_pg_dir[0] = orig_swapper_pg_dir0; |
| 648 | local_flush_tlb(); |
| 649 | #ifdef CONFIG_M486 |
| 650 | free_page((unsigned long)page_table_copies); |
| 651 | #endif |
| 652 | |
| 653 | if (cpu_booted_map) { |
| 654 | VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n", |
| 655 | cpu, smp_processor_id())); |
| 656 | |
| 657 | printk("CPU%d: ", cpu); |
| 658 | print_cpu_info(&cpu_data[cpu]); |
| 659 | wmb(); |
| 660 | cpu_set(cpu, cpu_callout_map); |
James Bottomley | 3c101cf | 2006-06-26 21:33:09 -0500 | [diff] [blame] | 661 | cpu_set(cpu, cpu_present_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | } |
| 663 | else { |
| 664 | printk("CPU%d FAILED TO BOOT: ", cpu); |
| 665 | if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5) |
| 666 | printk("Stuck.\n"); |
| 667 | else |
| 668 | printk("Not responding.\n"); |
| 669 | |
| 670 | cpucount--; |
| 671 | } |
| 672 | } |
| 673 | |
| 674 | void __init |
| 675 | smp_boot_cpus(void) |
| 676 | { |
| 677 | int i; |
| 678 | |
| 679 | /* CAT BUS initialisation must be done after the memory */ |
| 680 | /* FIXME: The L4 has a catbus too, it just needs to be |
| 681 | * accessed in a totally different way */ |
| 682 | if(voyager_level == 5) { |
| 683 | voyager_cat_init(); |
| 684 | |
| 685 | /* now that the cat has probed the Voyager System Bus, sanity |
| 686 | * check the cpu map */ |
| 687 | if( ((voyager_quad_processors | voyager_extended_vic_processors) |
| 688 | & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) { |
| 689 | /* should panic */ |
| 690 | printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n"); |
| 691 | } |
| 692 | } else if(voyager_level == 4) |
| 693 | voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0]; |
| 694 | |
| 695 | /* this sets up the idle task to run on the current cpu */ |
| 696 | voyager_extended_cpus = 1; |
| 697 | /* Remove the global_irq_holder setting, it triggers a BUG() on |
| 698 | * schedule at the moment */ |
| 699 | //global_irq_holder = boot_cpu_id; |
| 700 | |
| 701 | /* FIXME: Need to do something about this but currently only works |
| 702 | * on CPUs with a tsc which none of mine have. |
| 703 | smp_tune_scheduling(); |
| 704 | */ |
| 705 | smp_store_cpu_info(boot_cpu_id); |
| 706 | printk("CPU%d: ", boot_cpu_id); |
| 707 | print_cpu_info(&cpu_data[boot_cpu_id]); |
| 708 | |
| 709 | if(is_cpu_quad()) { |
| 710 | /* booting on a Quad CPU */ |
| 711 | printk("VOYAGER SMP: Boot CPU is Quad\n"); |
| 712 | qic_setup(); |
| 713 | do_quad_bootstrap(); |
| 714 | } |
| 715 | |
| 716 | /* enable our own CPIs */ |
| 717 | vic_enable_cpi(); |
| 718 | |
| 719 | cpu_set(boot_cpu_id, cpu_online_map); |
| 720 | cpu_set(boot_cpu_id, cpu_callout_map); |
| 721 | |
| 722 | /* loop over all the extended VIC CPUs and boot them. The |
| 723 | * Quad CPUs must be bootstrapped by their extended VIC cpu */ |
| 724 | for(i = 0; i < NR_CPUS; i++) { |
| 725 | if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map)) |
| 726 | continue; |
| 727 | do_boot_cpu(i); |
| 728 | /* This udelay seems to be needed for the Quad boots |
| 729 | * don't remove unless you know what you're doing */ |
| 730 | udelay(1000); |
| 731 | } |
| 732 | /* we could compute the total bogomips here, but why bother?, |
| 733 | * Code added from smpboot.c */ |
| 734 | { |
| 735 | unsigned long bogosum = 0; |
| 736 | for (i = 0; i < NR_CPUS; i++) |
| 737 | if (cpu_isset(i, cpu_online_map)) |
| 738 | bogosum += cpu_data[i].loops_per_jiffy; |
| 739 | printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", |
| 740 | cpucount+1, |
| 741 | bogosum/(500000/HZ), |
| 742 | (bogosum/(5000/HZ))%100); |
| 743 | } |
| 744 | voyager_extended_cpus = hweight32(voyager_extended_vic_processors); |
| 745 | printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus); |
| 746 | /* that's it, switch to symmetric mode */ |
| 747 | outb(0, VIC_PRIORITY_REGISTER); |
| 748 | outb(0, VIC_CLAIM_REGISTER_0); |
| 749 | outb(0, VIC_CLAIM_REGISTER_1); |
| 750 | |
| 751 | VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus())); |
| 752 | } |
| 753 | |
| 754 | /* Reload the secondary CPUs task structure (this function does not |
| 755 | * return ) */ |
| 756 | void __init |
| 757 | initialize_secondary(void) |
| 758 | { |
| 759 | #if 0 |
| 760 | // AC kernels only |
| 761 | set_current(hard_get_current()); |
| 762 | #endif |
| 763 | |
| 764 | /* |
| 765 | * We don't actually need to load the full TSS, |
| 766 | * basically just the stack pointer and the eip. |
| 767 | */ |
| 768 | |
| 769 | asm volatile( |
| 770 | "movl %0,%%esp\n\t" |
| 771 | "jmp *%1" |
| 772 | : |
| 773 | :"r" (current->thread.esp),"r" (current->thread.eip)); |
| 774 | } |
| 775 | |
| 776 | /* handle a Voyager SYS_INT -- If we don't, the base board will |
| 777 | * panic the system. |
| 778 | * |
| 779 | * System interrupts occur because some problem was detected on the |
| 780 | * various busses. To find out what you have to probe all the |
| 781 | * hardware via the CAT bus. FIXME: At the moment we do nothing. */ |
| 782 | fastcall void |
| 783 | smp_vic_sys_interrupt(struct pt_regs *regs) |
| 784 | { |
| 785 | ack_CPI(VIC_SYS_INT); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 786 | printk("Voyager SYSTEM INTERRUPT\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | /* Handle a voyager CMN_INT; These interrupts occur either because of |
| 790 | * a system status change or because a single bit memory error |
| 791 | * occurred. FIXME: At the moment, ignore all this. */ |
| 792 | fastcall void |
| 793 | smp_vic_cmn_interrupt(struct pt_regs *regs) |
| 794 | { |
| 795 | static __u8 in_cmn_int = 0; |
| 796 | static DEFINE_SPINLOCK(cmn_int_lock); |
| 797 | |
| 798 | /* common ints are broadcast, so make sure we only do this once */ |
| 799 | _raw_spin_lock(&cmn_int_lock); |
| 800 | if(in_cmn_int) |
| 801 | goto unlock_end; |
| 802 | |
| 803 | in_cmn_int++; |
| 804 | _raw_spin_unlock(&cmn_int_lock); |
| 805 | |
| 806 | VDEBUG(("Voyager COMMON INTERRUPT\n")); |
| 807 | |
| 808 | if(voyager_level == 5) |
| 809 | voyager_cat_do_common_interrupt(); |
| 810 | |
| 811 | _raw_spin_lock(&cmn_int_lock); |
| 812 | in_cmn_int = 0; |
| 813 | unlock_end: |
| 814 | _raw_spin_unlock(&cmn_int_lock); |
| 815 | ack_CPI(VIC_CMN_INT); |
| 816 | } |
| 817 | |
| 818 | /* |
| 819 | * Reschedule call back. Nothing to do, all the work is done |
| 820 | * automatically when we return from the interrupt. */ |
| 821 | static void |
| 822 | smp_reschedule_interrupt(void) |
| 823 | { |
| 824 | /* do nothing */ |
| 825 | } |
| 826 | |
| 827 | static struct mm_struct * flush_mm; |
| 828 | static unsigned long flush_va; |
| 829 | static DEFINE_SPINLOCK(tlbstate_lock); |
| 830 | #define FLUSH_ALL 0xffffffff |
| 831 | |
| 832 | /* |
| 833 | * We cannot call mmdrop() because we are in interrupt context, |
| 834 | * instead update mm->cpu_vm_mask. |
| 835 | * |
| 836 | * We need to reload %cr3 since the page tables may be going |
| 837 | * away from under us.. |
| 838 | */ |
| 839 | static inline void |
| 840 | leave_mm (unsigned long cpu) |
| 841 | { |
| 842 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) |
| 843 | BUG(); |
| 844 | cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask); |
| 845 | load_cr3(swapper_pg_dir); |
| 846 | } |
| 847 | |
| 848 | |
| 849 | /* |
| 850 | * Invalidate call-back |
| 851 | */ |
| 852 | static void |
| 853 | smp_invalidate_interrupt(void) |
| 854 | { |
| 855 | __u8 cpu = smp_processor_id(); |
| 856 | |
| 857 | if (!test_bit(cpu, &smp_invalidate_needed)) |
| 858 | return; |
| 859 | /* This will flood messages. Don't uncomment unless you see |
| 860 | * Problems with cross cpu invalidation |
| 861 | VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n", |
| 862 | smp_processor_id())); |
| 863 | */ |
| 864 | |
| 865 | if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) { |
| 866 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) { |
| 867 | if (flush_va == FLUSH_ALL) |
| 868 | local_flush_tlb(); |
| 869 | else |
| 870 | __flush_tlb_one(flush_va); |
| 871 | } else |
| 872 | leave_mm(cpu); |
| 873 | } |
| 874 | smp_mb__before_clear_bit(); |
| 875 | clear_bit(cpu, &smp_invalidate_needed); |
| 876 | smp_mb__after_clear_bit(); |
| 877 | } |
| 878 | |
| 879 | /* All the new flush operations for 2.4 */ |
| 880 | |
| 881 | |
| 882 | /* This routine is called with a physical cpu mask */ |
| 883 | static void |
| 884 | flush_tlb_others (unsigned long cpumask, struct mm_struct *mm, |
| 885 | unsigned long va) |
| 886 | { |
| 887 | int stuck = 50000; |
| 888 | |
| 889 | if (!cpumask) |
| 890 | BUG(); |
| 891 | if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask) |
| 892 | BUG(); |
| 893 | if (cpumask & (1 << smp_processor_id())) |
| 894 | BUG(); |
| 895 | if (!mm) |
| 896 | BUG(); |
| 897 | |
| 898 | spin_lock(&tlbstate_lock); |
| 899 | |
| 900 | flush_mm = mm; |
| 901 | flush_va = va; |
| 902 | atomic_set_mask(cpumask, &smp_invalidate_needed); |
| 903 | /* |
| 904 | * We have to send the CPI only to |
| 905 | * CPUs affected. |
| 906 | */ |
| 907 | send_CPI(cpumask, VIC_INVALIDATE_CPI); |
| 908 | |
| 909 | while (smp_invalidate_needed) { |
| 910 | mb(); |
| 911 | if(--stuck == 0) { |
| 912 | printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id()); |
| 913 | break; |
| 914 | } |
| 915 | } |
| 916 | |
| 917 | /* Uncomment only to debug invalidation problems |
| 918 | VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu)); |
| 919 | */ |
| 920 | |
| 921 | flush_mm = NULL; |
| 922 | flush_va = 0; |
| 923 | spin_unlock(&tlbstate_lock); |
| 924 | } |
| 925 | |
| 926 | void |
| 927 | flush_tlb_current_task(void) |
| 928 | { |
| 929 | struct mm_struct *mm = current->mm; |
| 930 | unsigned long cpu_mask; |
| 931 | |
| 932 | preempt_disable(); |
| 933 | |
| 934 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); |
| 935 | local_flush_tlb(); |
| 936 | if (cpu_mask) |
| 937 | flush_tlb_others(cpu_mask, mm, FLUSH_ALL); |
| 938 | |
| 939 | preempt_enable(); |
| 940 | } |
| 941 | |
| 942 | |
| 943 | void |
| 944 | flush_tlb_mm (struct mm_struct * mm) |
| 945 | { |
| 946 | unsigned long cpu_mask; |
| 947 | |
| 948 | preempt_disable(); |
| 949 | |
| 950 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); |
| 951 | |
| 952 | if (current->active_mm == mm) { |
| 953 | if (current->mm) |
| 954 | local_flush_tlb(); |
| 955 | else |
| 956 | leave_mm(smp_processor_id()); |
| 957 | } |
| 958 | if (cpu_mask) |
| 959 | flush_tlb_others(cpu_mask, mm, FLUSH_ALL); |
| 960 | |
| 961 | preempt_enable(); |
| 962 | } |
| 963 | |
| 964 | void flush_tlb_page(struct vm_area_struct * vma, unsigned long va) |
| 965 | { |
| 966 | struct mm_struct *mm = vma->vm_mm; |
| 967 | unsigned long cpu_mask; |
| 968 | |
| 969 | preempt_disable(); |
| 970 | |
| 971 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); |
| 972 | if (current->active_mm == mm) { |
| 973 | if(current->mm) |
| 974 | __flush_tlb_one(va); |
| 975 | else |
| 976 | leave_mm(smp_processor_id()); |
| 977 | } |
| 978 | |
| 979 | if (cpu_mask) |
| 980 | flush_tlb_others(cpu_mask, mm, va); |
| 981 | |
| 982 | preempt_enable(); |
| 983 | } |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 984 | EXPORT_SYMBOL(flush_tlb_page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | |
| 986 | /* enable the requested IRQs */ |
| 987 | static void |
| 988 | smp_enable_irq_interrupt(void) |
| 989 | { |
| 990 | __u8 irq; |
| 991 | __u8 cpu = get_cpu(); |
| 992 | |
| 993 | VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu, |
| 994 | vic_irq_enable_mask[cpu])); |
| 995 | |
| 996 | spin_lock(&vic_irq_lock); |
| 997 | for(irq = 0; irq < 16; irq++) { |
| 998 | if(vic_irq_enable_mask[cpu] & (1<<irq)) |
| 999 | enable_local_vic_irq(irq); |
| 1000 | } |
| 1001 | vic_irq_enable_mask[cpu] = 0; |
| 1002 | spin_unlock(&vic_irq_lock); |
| 1003 | |
| 1004 | put_cpu_no_resched(); |
| 1005 | } |
| 1006 | |
| 1007 | /* |
| 1008 | * CPU halt call-back |
| 1009 | */ |
| 1010 | static void |
| 1011 | smp_stop_cpu_function(void *dummy) |
| 1012 | { |
| 1013 | VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id())); |
| 1014 | cpu_clear(smp_processor_id(), cpu_online_map); |
| 1015 | local_irq_disable(); |
| 1016 | for(;;) |
Zachary Amsden | f2ab446 | 2005-09-03 15:56:42 -0700 | [diff] [blame] | 1017 | halt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | static DEFINE_SPINLOCK(call_lock); |
| 1021 | |
| 1022 | struct call_data_struct { |
| 1023 | void (*func) (void *info); |
| 1024 | void *info; |
| 1025 | volatile unsigned long started; |
| 1026 | volatile unsigned long finished; |
| 1027 | int wait; |
| 1028 | }; |
| 1029 | |
| 1030 | static struct call_data_struct * call_data; |
| 1031 | |
| 1032 | /* execute a thread on a new CPU. The function to be called must be |
| 1033 | * previously set up. This is used to schedule a function for |
| 1034 | * execution on all CPU's - set up the function then broadcast a |
| 1035 | * function_interrupt CPI to come here on each CPU */ |
| 1036 | static void |
| 1037 | smp_call_function_interrupt(void) |
| 1038 | { |
| 1039 | void (*func) (void *info) = call_data->func; |
| 1040 | void *info = call_data->info; |
| 1041 | /* must take copy of wait because call_data may be replaced |
| 1042 | * unless the function is waiting for us to finish */ |
| 1043 | int wait = call_data->wait; |
| 1044 | __u8 cpu = smp_processor_id(); |
| 1045 | |
| 1046 | /* |
| 1047 | * Notify initiating CPU that I've grabbed the data and am |
| 1048 | * about to execute the function |
| 1049 | */ |
| 1050 | mb(); |
| 1051 | if(!test_and_clear_bit(cpu, &call_data->started)) { |
| 1052 | /* If the bit wasn't set, this could be a replay */ |
| 1053 | printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu); |
| 1054 | return; |
| 1055 | } |
| 1056 | /* |
| 1057 | * At this point the info structure may be out of scope unless wait==1 |
| 1058 | */ |
| 1059 | irq_enter(); |
| 1060 | (*func)(info); |
| 1061 | irq_exit(); |
| 1062 | if (wait) { |
| 1063 | mb(); |
| 1064 | clear_bit(cpu, &call_data->finished); |
| 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | /* Call this function on all CPUs using the function_interrupt above |
| 1069 | <func> The function to run. This must be fast and non-blocking. |
| 1070 | <info> An arbitrary pointer to pass to the function. |
| 1071 | <retry> If true, keep retrying until ready. |
| 1072 | <wait> If true, wait until function has completed on other CPUs. |
| 1073 | [RETURNS] 0 on success, else a negative status code. Does not return until |
| 1074 | remote CPUs are nearly ready to execute <<func>> or are or have executed. |
| 1075 | */ |
| 1076 | int |
| 1077 | smp_call_function (void (*func) (void *info), void *info, int retry, |
| 1078 | int wait) |
| 1079 | { |
| 1080 | struct call_data_struct data; |
| 1081 | __u32 mask = cpus_addr(cpu_online_map)[0]; |
| 1082 | |
| 1083 | mask &= ~(1<<smp_processor_id()); |
| 1084 | |
| 1085 | if (!mask) |
| 1086 | return 0; |
| 1087 | |
| 1088 | /* Can deadlock when called with interrupts disabled */ |
| 1089 | WARN_ON(irqs_disabled()); |
| 1090 | |
| 1091 | data.func = func; |
| 1092 | data.info = info; |
| 1093 | data.started = mask; |
| 1094 | data.wait = wait; |
| 1095 | if (wait) |
| 1096 | data.finished = mask; |
| 1097 | |
| 1098 | spin_lock(&call_lock); |
| 1099 | call_data = &data; |
| 1100 | wmb(); |
| 1101 | /* Send a message to all other CPUs and wait for them to respond */ |
| 1102 | send_CPI_allbutself(VIC_CALL_FUNCTION_CPI); |
| 1103 | |
| 1104 | /* Wait for response */ |
| 1105 | while (data.started) |
| 1106 | barrier(); |
| 1107 | |
| 1108 | if (wait) |
| 1109 | while (data.finished) |
| 1110 | barrier(); |
| 1111 | |
| 1112 | spin_unlock(&call_lock); |
| 1113 | |
| 1114 | return 0; |
| 1115 | } |
James Bottomley | 153f805 | 2005-07-13 09:38:05 -0400 | [diff] [blame] | 1116 | EXPORT_SYMBOL(smp_call_function); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | |
| 1118 | /* Sorry about the name. In an APIC based system, the APICs |
| 1119 | * themselves are programmed to send a timer interrupt. This is used |
| 1120 | * by linux to reschedule the processor. Voyager doesn't have this, |
| 1121 | * so we use the system clock to interrupt one processor, which in |
| 1122 | * turn, broadcasts a timer CPI to all the others --- we receive that |
| 1123 | * CPI here. We don't use this actually for counting so losing |
| 1124 | * ticks doesn't matter |
| 1125 | * |
| 1126 | * FIXME: For those CPU's which actually have a local APIC, we could |
| 1127 | * try to use it to trigger this interrupt instead of having to |
| 1128 | * broadcast the timer tick. Unfortunately, all my pentium DYADs have |
| 1129 | * no local APIC, so I can't do this |
| 1130 | * |
| 1131 | * This function is currently a placeholder and is unused in the code */ |
| 1132 | fastcall void |
| 1133 | smp_apic_timer_interrupt(struct pt_regs *regs) |
| 1134 | { |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1135 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 1136 | wrapper_smp_local_timer_interrupt(); |
| 1137 | set_irq_regs(old_regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1138 | } |
| 1139 | |
| 1140 | /* All of the QUAD interrupt GATES */ |
| 1141 | fastcall void |
| 1142 | smp_qic_timer_interrupt(struct pt_regs *regs) |
| 1143 | { |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1144 | struct pt_regs *old_regs = set_irq_regs(regs); |
James Bottomley | 81c06b1 | 2006-10-12 22:25:03 -0500 | [diff] [blame] | 1145 | ack_QIC_CPI(QIC_TIMER_CPI); |
| 1146 | wrapper_smp_local_timer_interrupt(); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1147 | set_irq_regs(old_regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | fastcall void |
| 1151 | smp_qic_invalidate_interrupt(struct pt_regs *regs) |
| 1152 | { |
| 1153 | ack_QIC_CPI(QIC_INVALIDATE_CPI); |
| 1154 | smp_invalidate_interrupt(); |
| 1155 | } |
| 1156 | |
| 1157 | fastcall void |
| 1158 | smp_qic_reschedule_interrupt(struct pt_regs *regs) |
| 1159 | { |
| 1160 | ack_QIC_CPI(QIC_RESCHEDULE_CPI); |
| 1161 | smp_reschedule_interrupt(); |
| 1162 | } |
| 1163 | |
| 1164 | fastcall void |
| 1165 | smp_qic_enable_irq_interrupt(struct pt_regs *regs) |
| 1166 | { |
| 1167 | ack_QIC_CPI(QIC_ENABLE_IRQ_CPI); |
| 1168 | smp_enable_irq_interrupt(); |
| 1169 | } |
| 1170 | |
| 1171 | fastcall void |
| 1172 | smp_qic_call_function_interrupt(struct pt_regs *regs) |
| 1173 | { |
| 1174 | ack_QIC_CPI(QIC_CALL_FUNCTION_CPI); |
| 1175 | smp_call_function_interrupt(); |
| 1176 | } |
| 1177 | |
| 1178 | fastcall void |
| 1179 | smp_vic_cpi_interrupt(struct pt_regs *regs) |
| 1180 | { |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1181 | struct pt_regs *old_regs = set_irq_regs(regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1182 | __u8 cpu = smp_processor_id(); |
| 1183 | |
| 1184 | if(is_cpu_quad()) |
| 1185 | ack_QIC_CPI(VIC_CPI_LEVEL0); |
| 1186 | else |
| 1187 | ack_VIC_CPI(VIC_CPI_LEVEL0); |
| 1188 | |
| 1189 | if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu])) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1190 | wrapper_smp_local_timer_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1191 | if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu])) |
| 1192 | smp_invalidate_interrupt(); |
| 1193 | if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu])) |
| 1194 | smp_reschedule_interrupt(); |
| 1195 | if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu])) |
| 1196 | smp_enable_irq_interrupt(); |
| 1197 | if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu])) |
| 1198 | smp_call_function_interrupt(); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1199 | set_irq_regs(old_regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
| 1202 | static void |
| 1203 | do_flush_tlb_all(void* info) |
| 1204 | { |
| 1205 | unsigned long cpu = smp_processor_id(); |
| 1206 | |
| 1207 | __flush_tlb_all(); |
| 1208 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY) |
| 1209 | leave_mm(cpu); |
| 1210 | } |
| 1211 | |
| 1212 | |
| 1213 | /* flush the TLB of every active CPU in the system */ |
| 1214 | void |
| 1215 | flush_tlb_all(void) |
| 1216 | { |
| 1217 | on_each_cpu(do_flush_tlb_all, 0, 1, 1); |
| 1218 | } |
| 1219 | |
| 1220 | /* used to set up the trampoline for other CPUs when the memory manager |
| 1221 | * is sorted out */ |
| 1222 | void __init |
| 1223 | smp_alloc_memory(void) |
| 1224 | { |
| 1225 | trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE); |
| 1226 | if(__pa(trampoline_base) >= 0x93000) |
| 1227 | BUG(); |
| 1228 | } |
| 1229 | |
| 1230 | /* send a reschedule CPI to one CPU by physical CPU number*/ |
| 1231 | void |
| 1232 | smp_send_reschedule(int cpu) |
| 1233 | { |
| 1234 | send_one_CPI(cpu, VIC_RESCHEDULE_CPI); |
| 1235 | } |
| 1236 | |
| 1237 | |
| 1238 | int |
| 1239 | hard_smp_processor_id(void) |
| 1240 | { |
| 1241 | __u8 i; |
| 1242 | __u8 cpumask = inb(VIC_PROC_WHO_AM_I); |
| 1243 | if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER) |
| 1244 | return cpumask & 0x1F; |
| 1245 | |
| 1246 | for(i = 0; i < 8; i++) { |
| 1247 | if(cpumask & (1<<i)) |
| 1248 | return i; |
| 1249 | } |
| 1250 | printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask); |
| 1251 | return 0; |
| 1252 | } |
| 1253 | |
Fernando Vazquez | 2654c08 | 2006-09-30 23:29:08 -0700 | [diff] [blame] | 1254 | int |
| 1255 | safe_smp_processor_id(void) |
| 1256 | { |
| 1257 | return hard_smp_processor_id(); |
| 1258 | } |
| 1259 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1260 | /* broadcast a halt to all other CPUs */ |
| 1261 | void |
| 1262 | smp_send_stop(void) |
| 1263 | { |
| 1264 | smp_call_function(smp_stop_cpu_function, NULL, 1, 1); |
| 1265 | } |
| 1266 | |
| 1267 | /* this function is triggered in time.c when a clock tick fires |
| 1268 | * we need to re-broadcast the tick to all CPUs */ |
| 1269 | void |
James Bottomley | 81c06b1 | 2006-10-12 22:25:03 -0500 | [diff] [blame] | 1270 | smp_vic_timer_interrupt(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | { |
| 1272 | send_CPI_allbutself(VIC_TIMER_CPI); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1273 | smp_local_timer_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | } |
| 1275 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | /* local (per CPU) timer interrupt. It does both profiling and |
| 1277 | * process statistics/rescheduling. |
| 1278 | * |
| 1279 | * We do profiling in every local tick, statistics/rescheduling |
| 1280 | * happen only every 'profiling multiplier' ticks. The default |
| 1281 | * multiplier is 1 and it can be changed by writing the new multiplier |
| 1282 | * value into /proc/profile. |
| 1283 | */ |
| 1284 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1285 | smp_local_timer_interrupt(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1286 | { |
| 1287 | int cpu = smp_processor_id(); |
| 1288 | long weight; |
| 1289 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1290 | profile_tick(CPU_PROFILING); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | if (--per_cpu(prof_counter, cpu) <= 0) { |
| 1292 | /* |
| 1293 | * The multiplier may have changed since the last time we got |
| 1294 | * to this point as a result of the user writing to |
| 1295 | * /proc/profile. In this case we need to adjust the APIC |
| 1296 | * timer accordingly. |
| 1297 | * |
| 1298 | * Interrupts are already masked off at this point. |
| 1299 | */ |
| 1300 | per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu); |
| 1301 | if (per_cpu(prof_counter, cpu) != |
| 1302 | per_cpu(prof_old_multiplier, cpu)) { |
| 1303 | /* FIXME: need to update the vic timer tick here */ |
| 1304 | per_cpu(prof_old_multiplier, cpu) = |
| 1305 | per_cpu(prof_counter, cpu); |
| 1306 | } |
| 1307 | |
James Bottomley | 81c06b1 | 2006-10-12 22:25:03 -0500 | [diff] [blame] | 1308 | update_process_times(user_mode_vm(get_irq_regs())); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | } |
| 1310 | |
| 1311 | if( ((1<<cpu) & voyager_extended_vic_processors) == 0) |
| 1312 | /* only extended VIC processors participate in |
| 1313 | * interrupt distribution */ |
| 1314 | return; |
| 1315 | |
| 1316 | /* |
| 1317 | * We take the 'long' return path, and there every subsystem |
| 1318 | * grabs the apropriate locks (kernel lock/ irq lock). |
| 1319 | * |
| 1320 | * we might want to decouple profiling from the 'long path', |
| 1321 | * and do the profiling totally in assembly. |
| 1322 | * |
| 1323 | * Currently this isn't too much of an issue (performance wise), |
| 1324 | * we can take more than 100K local irqs per second on a 100 MHz P5. |
| 1325 | */ |
| 1326 | |
| 1327 | if((++vic_tick[cpu] & 0x7) != 0) |
| 1328 | return; |
| 1329 | /* get here every 16 ticks (about every 1/6 of a second) */ |
| 1330 | |
| 1331 | /* Change our priority to give someone else a chance at getting |
| 1332 | * the IRQ. The algorithm goes like this: |
| 1333 | * |
| 1334 | * In the VIC, the dynamically routed interrupt is always |
| 1335 | * handled by the lowest priority eligible (i.e. receiving |
| 1336 | * interrupts) CPU. If >1 eligible CPUs are equal lowest, the |
| 1337 | * lowest processor number gets it. |
| 1338 | * |
| 1339 | * The priority of a CPU is controlled by a special per-CPU |
| 1340 | * VIC priority register which is 3 bits wide 0 being lowest |
| 1341 | * and 7 highest priority.. |
| 1342 | * |
| 1343 | * Therefore we subtract the average number of interrupts from |
| 1344 | * the number we've fielded. If this number is negative, we |
| 1345 | * lower the activity count and if it is positive, we raise |
| 1346 | * it. |
| 1347 | * |
| 1348 | * I'm afraid this still leads to odd looking interrupt counts: |
| 1349 | * the totals are all roughly equal, but the individual ones |
| 1350 | * look rather skewed. |
| 1351 | * |
| 1352 | * FIXME: This algorithm is total crap when mixed with SMP |
| 1353 | * affinity code since we now try to even up the interrupt |
| 1354 | * counts when an affinity binding is keeping them on a |
| 1355 | * particular CPU*/ |
| 1356 | weight = (vic_intr_count[cpu]*voyager_extended_cpus |
| 1357 | - vic_intr_total) >> 4; |
| 1358 | weight += 4; |
| 1359 | if(weight > 7) |
| 1360 | weight = 7; |
| 1361 | if(weight < 0) |
| 1362 | weight = 0; |
| 1363 | |
| 1364 | outb((__u8)weight, VIC_PRIORITY_REGISTER); |
| 1365 | |
| 1366 | #ifdef VOYAGER_DEBUG |
| 1367 | if((vic_tick[cpu] & 0xFFF) == 0) { |
| 1368 | /* print this message roughly every 25 secs */ |
| 1369 | printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n", |
| 1370 | cpu, vic_tick[cpu], weight); |
| 1371 | } |
| 1372 | #endif |
| 1373 | } |
| 1374 | |
| 1375 | /* setup the profiling timer */ |
| 1376 | int |
| 1377 | setup_profiling_timer(unsigned int multiplier) |
| 1378 | { |
| 1379 | int i; |
| 1380 | |
| 1381 | if ( (!multiplier)) |
| 1382 | return -EINVAL; |
| 1383 | |
| 1384 | /* |
| 1385 | * Set the new multiplier for each CPU. CPUs don't start using the |
| 1386 | * new values until the next timer interrupt in which they do process |
| 1387 | * accounting. |
| 1388 | */ |
| 1389 | for (i = 0; i < NR_CPUS; ++i) |
| 1390 | per_cpu(prof_multiplier, i) = multiplier; |
| 1391 | |
| 1392 | return 0; |
| 1393 | } |
| 1394 | |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1395 | /* This is a bit of a mess, but forced on us by the genirq changes |
| 1396 | * there's no genirq handler that really does what voyager wants |
| 1397 | * so hack it up with the simple IRQ handler */ |
| 1398 | static void fastcall |
| 1399 | handle_vic_irq(unsigned int irq, struct irq_desc *desc) |
| 1400 | { |
| 1401 | before_handle_vic_irq(irq); |
| 1402 | handle_simple_irq(irq, desc); |
| 1403 | after_handle_vic_irq(irq); |
| 1404 | } |
| 1405 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | |
| 1407 | /* The CPIs are handled in the per cpu 8259s, so they must be |
| 1408 | * enabled to be received: FIX: enabling the CPIs in the early |
| 1409 | * boot sequence interferes with bug checking; enable them later |
| 1410 | * on in smp_init */ |
| 1411 | #define VIC_SET_GATE(cpi, vector) \ |
| 1412 | set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector)) |
| 1413 | #define QIC_SET_GATE(cpi, vector) \ |
| 1414 | set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector)) |
| 1415 | |
| 1416 | void __init |
| 1417 | smp_intr_init(void) |
| 1418 | { |
| 1419 | int i; |
| 1420 | |
| 1421 | /* initialize the per cpu irq mask to all disabled */ |
| 1422 | for(i = 0; i < NR_CPUS; i++) |
| 1423 | vic_irq_mask[i] = 0xFFFF; |
| 1424 | |
| 1425 | VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt); |
| 1426 | |
| 1427 | VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt); |
| 1428 | VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt); |
| 1429 | |
| 1430 | QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt); |
| 1431 | QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt); |
| 1432 | QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt); |
| 1433 | QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt); |
| 1434 | QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt); |
| 1435 | |
| 1436 | |
| 1437 | /* now put the VIC descriptor into the first 48 IRQs |
| 1438 | * |
| 1439 | * This is for later: first 16 correspond to PC IRQs; next 16 |
| 1440 | * are Primary MC IRQs and final 16 are Secondary MC IRQs */ |
| 1441 | for(i = 0; i < 48; i++) |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1442 | set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1443 | } |
| 1444 | |
| 1445 | /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per |
| 1446 | * processor to receive CPI */ |
| 1447 | static void |
| 1448 | send_CPI(__u32 cpuset, __u8 cpi) |
| 1449 | { |
| 1450 | int cpu; |
| 1451 | __u32 quad_cpuset = (cpuset & voyager_quad_processors); |
| 1452 | |
| 1453 | if(cpi < VIC_START_FAKE_CPI) { |
| 1454 | /* fake CPI are only used for booting, so send to the |
| 1455 | * extended quads as well---Quads must be VIC booted */ |
| 1456 | outb((__u8)(cpuset), VIC_CPI_Registers[cpi]); |
| 1457 | return; |
| 1458 | } |
| 1459 | if(quad_cpuset) |
| 1460 | send_QIC_CPI(quad_cpuset, cpi); |
| 1461 | cpuset &= ~quad_cpuset; |
| 1462 | cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */ |
| 1463 | if(cpuset == 0) |
| 1464 | return; |
| 1465 | for_each_online_cpu(cpu) { |
| 1466 | if(cpuset & (1<<cpu)) |
| 1467 | set_bit(cpi, &vic_cpi_mailbox[cpu]); |
| 1468 | } |
| 1469 | if(cpuset) |
| 1470 | outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]); |
| 1471 | } |
| 1472 | |
| 1473 | /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and |
| 1474 | * set the cache line to shared by reading it. |
| 1475 | * |
| 1476 | * DON'T make this inline otherwise the cache line read will be |
| 1477 | * optimised away |
| 1478 | * */ |
| 1479 | static int |
| 1480 | ack_QIC_CPI(__u8 cpi) { |
| 1481 | __u8 cpu = hard_smp_processor_id(); |
| 1482 | |
| 1483 | cpi &= 7; |
| 1484 | |
| 1485 | outb(1<<cpi, QIC_INTERRUPT_CLEAR1); |
| 1486 | return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi; |
| 1487 | } |
| 1488 | |
| 1489 | static void |
| 1490 | ack_special_QIC_CPI(__u8 cpi) |
| 1491 | { |
| 1492 | switch(cpi) { |
| 1493 | case VIC_CMN_INT: |
| 1494 | outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0); |
| 1495 | break; |
| 1496 | case VIC_SYS_INT: |
| 1497 | outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0); |
| 1498 | break; |
| 1499 | } |
| 1500 | /* also clear at the VIC, just in case (nop for non-extended proc) */ |
| 1501 | ack_VIC_CPI(cpi); |
| 1502 | } |
| 1503 | |
| 1504 | /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */ |
| 1505 | static void |
| 1506 | ack_VIC_CPI(__u8 cpi) |
| 1507 | { |
| 1508 | #ifdef VOYAGER_DEBUG |
| 1509 | unsigned long flags; |
| 1510 | __u16 isr; |
| 1511 | __u8 cpu = smp_processor_id(); |
| 1512 | |
| 1513 | local_irq_save(flags); |
| 1514 | isr = vic_read_isr(); |
| 1515 | if((isr & (1<<(cpi &7))) == 0) { |
| 1516 | printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi); |
| 1517 | } |
| 1518 | #endif |
| 1519 | /* send specific EOI; the two system interrupts have |
| 1520 | * bit 4 set for a separate vector but behave as the |
| 1521 | * corresponding 3 bit intr */ |
| 1522 | outb_p(0x60|(cpi & 7),0x20); |
| 1523 | |
| 1524 | #ifdef VOYAGER_DEBUG |
| 1525 | if((vic_read_isr() & (1<<(cpi &7))) != 0) { |
| 1526 | printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi); |
| 1527 | } |
| 1528 | local_irq_restore(flags); |
| 1529 | #endif |
| 1530 | } |
| 1531 | |
| 1532 | /* cribbed with thanks from irq.c */ |
| 1533 | #define __byte(x,y) (((unsigned char *)&(y))[x]) |
| 1534 | #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu])) |
| 1535 | #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu])) |
| 1536 | |
| 1537 | static unsigned int |
| 1538 | startup_vic_irq(unsigned int irq) |
| 1539 | { |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1540 | unmask_vic_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1541 | |
| 1542 | return 0; |
| 1543 | } |
| 1544 | |
| 1545 | /* The enable and disable routines. This is where we run into |
| 1546 | * conflicting architectural philosophy. Fundamentally, the voyager |
| 1547 | * architecture does not expect to have to disable interrupts globally |
| 1548 | * (the IRQ controllers belong to each CPU). The processor masquerade |
| 1549 | * which is used to start the system shouldn't be used in a running OS |
| 1550 | * since it will cause great confusion if two separate CPUs drive to |
| 1551 | * the same IRQ controller (I know, I've tried it). |
| 1552 | * |
| 1553 | * The solution is a variant on the NCR lazy SPL design: |
| 1554 | * |
| 1555 | * 1) To disable an interrupt, do nothing (other than set the |
| 1556 | * IRQ_DISABLED flag). This dares the interrupt actually to arrive. |
| 1557 | * |
| 1558 | * 2) If the interrupt dares to come in, raise the local mask against |
| 1559 | * it (this will result in all the CPU masks being raised |
| 1560 | * eventually). |
| 1561 | * |
| 1562 | * 3) To enable the interrupt, lower the mask on the local CPU and |
| 1563 | * broadcast an Interrupt enable CPI which causes all other CPUs to |
| 1564 | * adjust their masks accordingly. */ |
| 1565 | |
| 1566 | static void |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1567 | unmask_vic_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | { |
| 1569 | /* linux doesn't to processor-irq affinity, so enable on |
| 1570 | * all CPUs we know about */ |
| 1571 | int cpu = smp_processor_id(), real_cpu; |
| 1572 | __u16 mask = (1<<irq); |
| 1573 | __u32 processorList = 0; |
| 1574 | unsigned long flags; |
| 1575 | |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1576 | VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1577 | irq, cpu, cpu_irq_affinity[cpu])); |
| 1578 | spin_lock_irqsave(&vic_irq_lock, flags); |
| 1579 | for_each_online_cpu(real_cpu) { |
| 1580 | if(!(voyager_extended_vic_processors & (1<<real_cpu))) |
| 1581 | continue; |
| 1582 | if(!(cpu_irq_affinity[real_cpu] & mask)) { |
| 1583 | /* irq has no affinity for this CPU, ignore */ |
| 1584 | continue; |
| 1585 | } |
| 1586 | if(real_cpu == cpu) { |
| 1587 | enable_local_vic_irq(irq); |
| 1588 | } |
| 1589 | else if(vic_irq_mask[real_cpu] & mask) { |
| 1590 | vic_irq_enable_mask[real_cpu] |= mask; |
| 1591 | processorList |= (1<<real_cpu); |
| 1592 | } |
| 1593 | } |
| 1594 | spin_unlock_irqrestore(&vic_irq_lock, flags); |
| 1595 | if(processorList) |
| 1596 | send_CPI(processorList, VIC_ENABLE_IRQ_CPI); |
| 1597 | } |
| 1598 | |
| 1599 | static void |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1600 | mask_vic_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1601 | { |
| 1602 | /* lazy disable, do nothing */ |
| 1603 | } |
| 1604 | |
| 1605 | static void |
| 1606 | enable_local_vic_irq(unsigned int irq) |
| 1607 | { |
| 1608 | __u8 cpu = smp_processor_id(); |
| 1609 | __u16 mask = ~(1 << irq); |
| 1610 | __u16 old_mask = vic_irq_mask[cpu]; |
| 1611 | |
| 1612 | vic_irq_mask[cpu] &= mask; |
| 1613 | if(vic_irq_mask[cpu] == old_mask) |
| 1614 | return; |
| 1615 | |
| 1616 | VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n", |
| 1617 | irq, cpu)); |
| 1618 | |
| 1619 | if (irq & 8) { |
| 1620 | outb_p(cached_A1(cpu),0xA1); |
| 1621 | (void)inb_p(0xA1); |
| 1622 | } |
| 1623 | else { |
| 1624 | outb_p(cached_21(cpu),0x21); |
| 1625 | (void)inb_p(0x21); |
| 1626 | } |
| 1627 | } |
| 1628 | |
| 1629 | static void |
| 1630 | disable_local_vic_irq(unsigned int irq) |
| 1631 | { |
| 1632 | __u8 cpu = smp_processor_id(); |
| 1633 | __u16 mask = (1 << irq); |
| 1634 | __u16 old_mask = vic_irq_mask[cpu]; |
| 1635 | |
| 1636 | if(irq == 7) |
| 1637 | return; |
| 1638 | |
| 1639 | vic_irq_mask[cpu] |= mask; |
| 1640 | if(old_mask == vic_irq_mask[cpu]) |
| 1641 | return; |
| 1642 | |
| 1643 | VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n", |
| 1644 | irq, cpu)); |
| 1645 | |
| 1646 | if (irq & 8) { |
| 1647 | outb_p(cached_A1(cpu),0xA1); |
| 1648 | (void)inb_p(0xA1); |
| 1649 | } |
| 1650 | else { |
| 1651 | outb_p(cached_21(cpu),0x21); |
| 1652 | (void)inb_p(0x21); |
| 1653 | } |
| 1654 | } |
| 1655 | |
| 1656 | /* The VIC is level triggered, so the ack can only be issued after the |
| 1657 | * interrupt completes. However, we do Voyager lazy interrupt |
| 1658 | * handling here: It is an extremely expensive operation to mask an |
| 1659 | * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If |
| 1660 | * this interrupt actually comes in, then we mask and ack here to push |
| 1661 | * the interrupt off to another CPU */ |
| 1662 | static void |
| 1663 | before_handle_vic_irq(unsigned int irq) |
| 1664 | { |
| 1665 | irq_desc_t *desc = irq_desc + irq; |
| 1666 | __u8 cpu = smp_processor_id(); |
| 1667 | |
| 1668 | _raw_spin_lock(&vic_irq_lock); |
| 1669 | vic_intr_total++; |
| 1670 | vic_intr_count[cpu]++; |
| 1671 | |
| 1672 | if(!(cpu_irq_affinity[cpu] & (1<<irq))) { |
| 1673 | /* The irq is not in our affinity mask, push it off |
| 1674 | * onto another CPU */ |
| 1675 | VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n", |
| 1676 | irq, cpu)); |
| 1677 | disable_local_vic_irq(irq); |
| 1678 | /* set IRQ_INPROGRESS to prevent the handler in irq.c from |
| 1679 | * actually calling the interrupt routine */ |
| 1680 | desc->status |= IRQ_REPLAY | IRQ_INPROGRESS; |
| 1681 | } else if(desc->status & IRQ_DISABLED) { |
| 1682 | /* Damn, the interrupt actually arrived, do the lazy |
| 1683 | * disable thing. The interrupt routine in irq.c will |
| 1684 | * not handle a IRQ_DISABLED interrupt, so nothing more |
| 1685 | * need be done here */ |
| 1686 | VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n", |
| 1687 | irq, cpu)); |
| 1688 | disable_local_vic_irq(irq); |
| 1689 | desc->status |= IRQ_REPLAY; |
| 1690 | } else { |
| 1691 | desc->status &= ~IRQ_REPLAY; |
| 1692 | } |
| 1693 | |
| 1694 | _raw_spin_unlock(&vic_irq_lock); |
| 1695 | } |
| 1696 | |
| 1697 | /* Finish the VIC interrupt: basically mask */ |
| 1698 | static void |
| 1699 | after_handle_vic_irq(unsigned int irq) |
| 1700 | { |
| 1701 | irq_desc_t *desc = irq_desc + irq; |
| 1702 | |
| 1703 | _raw_spin_lock(&vic_irq_lock); |
| 1704 | { |
| 1705 | unsigned int status = desc->status & ~IRQ_INPROGRESS; |
| 1706 | #ifdef VOYAGER_DEBUG |
| 1707 | __u16 isr; |
| 1708 | #endif |
| 1709 | |
| 1710 | desc->status = status; |
| 1711 | if ((status & IRQ_DISABLED)) |
| 1712 | disable_local_vic_irq(irq); |
| 1713 | #ifdef VOYAGER_DEBUG |
| 1714 | /* DEBUG: before we ack, check what's in progress */ |
| 1715 | isr = vic_read_isr(); |
| 1716 | if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) { |
| 1717 | int i; |
| 1718 | __u8 cpu = smp_processor_id(); |
| 1719 | __u8 real_cpu; |
| 1720 | int mask; /* Um... initialize me??? --RR */ |
| 1721 | |
| 1722 | printk("VOYAGER SMP: CPU%d lost interrupt %d\n", |
| 1723 | cpu, irq); |
KAMEZAWA Hiroyuki | c8912599 | 2006-03-28 01:56:39 -0800 | [diff] [blame] | 1724 | for_each_possible_cpu(real_cpu, mask) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1725 | |
| 1726 | outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu, |
| 1727 | VIC_PROCESSOR_ID); |
| 1728 | isr = vic_read_isr(); |
| 1729 | if(isr & (1<<irq)) { |
| 1730 | printk("VOYAGER SMP: CPU%d ack irq %d\n", |
| 1731 | real_cpu, irq); |
| 1732 | ack_vic_irq(irq); |
| 1733 | } |
| 1734 | outb(cpu, VIC_PROCESSOR_ID); |
| 1735 | } |
| 1736 | } |
| 1737 | #endif /* VOYAGER_DEBUG */ |
| 1738 | /* as soon as we ack, the interrupt is eligible for |
| 1739 | * receipt by another CPU so everything must be in |
| 1740 | * order here */ |
| 1741 | ack_vic_irq(irq); |
| 1742 | if(status & IRQ_REPLAY) { |
| 1743 | /* replay is set if we disable the interrupt |
| 1744 | * in the before_handle_vic_irq() routine, so |
| 1745 | * clear the in progress bit here to allow the |
| 1746 | * next CPU to handle this correctly */ |
| 1747 | desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS); |
| 1748 | } |
| 1749 | #ifdef VOYAGER_DEBUG |
| 1750 | isr = vic_read_isr(); |
| 1751 | if((isr & (1<<irq)) != 0) |
| 1752 | printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n", |
| 1753 | irq, isr); |
| 1754 | #endif /* VOYAGER_DEBUG */ |
| 1755 | } |
| 1756 | _raw_spin_unlock(&vic_irq_lock); |
| 1757 | |
| 1758 | /* All code after this point is out of the main path - the IRQ |
| 1759 | * may be intercepted by another CPU if reasserted */ |
| 1760 | } |
| 1761 | |
| 1762 | |
| 1763 | /* Linux processor - interrupt affinity manipulations. |
| 1764 | * |
| 1765 | * For each processor, we maintain a 32 bit irq affinity mask. |
| 1766 | * Initially it is set to all 1's so every processor accepts every |
| 1767 | * interrupt. In this call, we change the processor's affinity mask: |
| 1768 | * |
| 1769 | * Change from enable to disable: |
| 1770 | * |
| 1771 | * If the interrupt ever comes in to the processor, we will disable it |
| 1772 | * and ack it to push it off to another CPU, so just accept the mask here. |
| 1773 | * |
| 1774 | * Change from disable to enable: |
| 1775 | * |
| 1776 | * change the mask and then do an interrupt enable CPI to re-enable on |
| 1777 | * the selected processors */ |
| 1778 | |
| 1779 | void |
| 1780 | set_vic_irq_affinity(unsigned int irq, cpumask_t mask) |
| 1781 | { |
| 1782 | /* Only extended processors handle interrupts */ |
| 1783 | unsigned long real_mask; |
| 1784 | unsigned long irq_mask = 1 << irq; |
| 1785 | int cpu; |
| 1786 | |
| 1787 | real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors; |
| 1788 | |
| 1789 | if(cpus_addr(mask)[0] == 0) |
| 1790 | /* can't have no cpu's to accept the interrupt -- extremely |
| 1791 | * bad things will happen */ |
| 1792 | return; |
| 1793 | |
| 1794 | if(irq == 0) |
| 1795 | /* can't change the affinity of the timer IRQ. This |
| 1796 | * is due to the constraint in the voyager |
| 1797 | * architecture that the CPI also comes in on and IRQ |
| 1798 | * line and we have chosen IRQ0 for this. If you |
| 1799 | * raise the mask on this interrupt, the processor |
| 1800 | * will no-longer be able to accept VIC CPIs */ |
| 1801 | return; |
| 1802 | |
| 1803 | if(irq >= 32) |
| 1804 | /* You can only have 32 interrupts in a voyager system |
| 1805 | * (and 32 only if you have a secondary microchannel |
| 1806 | * bus) */ |
| 1807 | return; |
| 1808 | |
| 1809 | for_each_online_cpu(cpu) { |
| 1810 | unsigned long cpu_mask = 1 << cpu; |
| 1811 | |
| 1812 | if(cpu_mask & real_mask) { |
| 1813 | /* enable the interrupt for this cpu */ |
| 1814 | cpu_irq_affinity[cpu] |= irq_mask; |
| 1815 | } else { |
| 1816 | /* disable the interrupt for this cpu */ |
| 1817 | cpu_irq_affinity[cpu] &= ~irq_mask; |
| 1818 | } |
| 1819 | } |
| 1820 | /* this is magic, we now have the correct affinity maps, so |
| 1821 | * enable the interrupt. This will send an enable CPI to |
| 1822 | * those cpu's who need to enable it in their local masks, |
| 1823 | * causing them to correct for the new affinity . If the |
| 1824 | * interrupt is currently globally disabled, it will simply be |
| 1825 | * disabled again as it comes in (voyager lazy disable). If |
| 1826 | * the affinity map is tightened to disable the interrupt on a |
| 1827 | * cpu, it will be pushed off when it comes in */ |
James Bottomley | c771746 | 2006-10-12 22:21:16 -0500 | [diff] [blame] | 1828 | unmask_vic_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1829 | } |
| 1830 | |
| 1831 | static void |
| 1832 | ack_vic_irq(unsigned int irq) |
| 1833 | { |
| 1834 | if (irq & 8) { |
| 1835 | outb(0x62,0x20); /* Specific EOI to cascade */ |
| 1836 | outb(0x60|(irq & 7),0xA0); |
| 1837 | } else { |
| 1838 | outb(0x60 | (irq & 7),0x20); |
| 1839 | } |
| 1840 | } |
| 1841 | |
| 1842 | /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259 |
| 1843 | * but are not vectored by it. This means that the 8259 mask must be |
| 1844 | * lowered to receive them */ |
| 1845 | static __init void |
| 1846 | vic_enable_cpi(void) |
| 1847 | { |
| 1848 | __u8 cpu = smp_processor_id(); |
| 1849 | |
| 1850 | /* just take a copy of the current mask (nop for boot cpu) */ |
| 1851 | vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id]; |
| 1852 | |
| 1853 | enable_local_vic_irq(VIC_CPI_LEVEL0); |
| 1854 | enable_local_vic_irq(VIC_CPI_LEVEL1); |
| 1855 | /* for sys int and cmn int */ |
| 1856 | enable_local_vic_irq(7); |
| 1857 | |
| 1858 | if(is_cpu_quad()) { |
| 1859 | outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0); |
| 1860 | outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1); |
| 1861 | VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n", |
| 1862 | cpu, QIC_CPI_ENABLE)); |
| 1863 | } |
| 1864 | |
| 1865 | VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n", |
| 1866 | cpu, vic_irq_mask[cpu])); |
| 1867 | } |
| 1868 | |
| 1869 | void |
| 1870 | voyager_smp_dump() |
| 1871 | { |
| 1872 | int old_cpu = smp_processor_id(), cpu; |
| 1873 | |
| 1874 | /* dump the interrupt masks of each processor */ |
| 1875 | for_each_online_cpu(cpu) { |
| 1876 | __u16 imr, isr, irr; |
| 1877 | unsigned long flags; |
| 1878 | |
| 1879 | local_irq_save(flags); |
| 1880 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); |
| 1881 | imr = (inb(0xa1) << 8) | inb(0x21); |
| 1882 | outb(0x0a, 0xa0); |
| 1883 | irr = inb(0xa0) << 8; |
| 1884 | outb(0x0a, 0x20); |
| 1885 | irr |= inb(0x20); |
| 1886 | outb(0x0b, 0xa0); |
| 1887 | isr = inb(0xa0) << 8; |
| 1888 | outb(0x0b, 0x20); |
| 1889 | isr |= inb(0x20); |
| 1890 | outb(old_cpu, VIC_PROCESSOR_ID); |
| 1891 | local_irq_restore(flags); |
| 1892 | printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n", |
| 1893 | cpu, vic_irq_mask[cpu], imr, irr, isr); |
| 1894 | #if 0 |
| 1895 | /* These lines are put in to try to unstick an un ack'd irq */ |
| 1896 | if(isr != 0) { |
| 1897 | int irq; |
| 1898 | for(irq=0; irq<16; irq++) { |
| 1899 | if(isr & (1<<irq)) { |
| 1900 | printk("\tCPU%d: ack irq %d\n", |
| 1901 | cpu, irq); |
| 1902 | local_irq_save(flags); |
| 1903 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, |
| 1904 | VIC_PROCESSOR_ID); |
| 1905 | ack_vic_irq(irq); |
| 1906 | outb(old_cpu, VIC_PROCESSOR_ID); |
| 1907 | local_irq_restore(flags); |
| 1908 | } |
| 1909 | } |
| 1910 | } |
| 1911 | #endif |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | void |
| 1916 | smp_voyager_power_off(void *dummy) |
| 1917 | { |
| 1918 | if(smp_processor_id() == boot_cpu_id) |
| 1919 | voyager_power_off(); |
| 1920 | else |
| 1921 | smp_stop_cpu_function(NULL); |
| 1922 | } |
| 1923 | |
| 1924 | void __init |
| 1925 | smp_prepare_cpus(unsigned int max_cpus) |
| 1926 | { |
| 1927 | /* FIXME: ignore max_cpus for now */ |
| 1928 | smp_boot_cpus(); |
| 1929 | } |
| 1930 | |
| 1931 | void __devinit smp_prepare_boot_cpu(void) |
| 1932 | { |
| 1933 | cpu_set(smp_processor_id(), cpu_online_map); |
| 1934 | cpu_set(smp_processor_id(), cpu_callout_map); |
Zwane Mwaikambo | 4ad8d38 | 2005-09-03 15:56:51 -0700 | [diff] [blame] | 1935 | cpu_set(smp_processor_id(), cpu_possible_map); |
James Bottomley | 3c101cf | 2006-06-26 21:33:09 -0500 | [diff] [blame] | 1936 | cpu_set(smp_processor_id(), cpu_present_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1937 | } |
| 1938 | |
| 1939 | int __devinit |
| 1940 | __cpu_up(unsigned int cpu) |
| 1941 | { |
| 1942 | /* This only works at boot for x86. See "rewrite" above. */ |
| 1943 | if (cpu_isset(cpu, smp_commenced_mask)) |
| 1944 | return -ENOSYS; |
| 1945 | |
| 1946 | /* In case one didn't come up */ |
| 1947 | if (!cpu_isset(cpu, cpu_callin_map)) |
| 1948 | return -EIO; |
| 1949 | /* Unleash the CPU! */ |
| 1950 | cpu_set(cpu, smp_commenced_mask); |
| 1951 | while (!cpu_isset(cpu, cpu_online_map)) |
| 1952 | mb(); |
| 1953 | return 0; |
| 1954 | } |
| 1955 | |
| 1956 | void __init |
| 1957 | smp_cpus_done(unsigned int max_cpus) |
| 1958 | { |
| 1959 | zap_low_mappings(); |
| 1960 | } |
Andrew Morton | 033ab7f | 2006-06-30 01:55:50 -0700 | [diff] [blame] | 1961 | |
| 1962 | void __init |
| 1963 | smp_setup_processor_id(void) |
| 1964 | { |
| 1965 | current_thread_info()->cpu = hard_smp_processor_id(); |
| 1966 | } |