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gerrit-public.fairphone.software / kernel / msm-4.9 / c826ed095d431c91f1d18f9b83b365569fcd977b / . / drivers / pinctrl / pinctrl-pxa3xx.h
blob: 8135744d6599baf8fbf6d04f9aee91d8219cd143 [file] [log] [blame]
Haojian Zhuangf4e66982012-01-04 10:26:33 +0800[diff] [blame]1/*
2 * linux/drivers/pinctrl/pinctrl-pxa3xx.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation.
7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 *
12 */
13
14#ifndef __PINCTRL_PXA3XX_H
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18
19#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
20
21#define PXA3xx_MUX_GPIO 0
22
23#define PXA3xx_MAX_MUX 8
24#define MFPR_FUNC_MASK 0x7
25
26enum pxa_cpu_type {
27 PINCTRL_INVALID = 0,
28 PINCTRL_PXA300,
29 PINCTRL_PXA310,
30 PINCTRL_PXA320,
31 PINCTRL_PXA168,
32 PINCTRL_PXA910,
33 PINCTRL_PXA930,
34 PINCTRL_PXA955,
35 PINCTRL_MMP2,
36 PINCTRL_MAX,
37};
38
39struct pxa3xx_mfp_pin {
40 const char *name;
41 const unsigned int pin;
42 const unsigned int mfpr; /* register offset */
43 const unsigned short func[8];
44};
45
46struct pxa3xx_pin_group {
47 const char *name;
48 const unsigned mux;
49 const unsigned *pins;
50 const unsigned npins;
51};
52
53struct pxa3xx_pmx_func {
54 const char *name;
55 const char * const * groups;
56 const unsigned num_groups;
57};
58
59struct pxa3xx_pinmux_info {
60 struct device *dev;
61 struct pinctrl_dev *pctrl;
62 enum pxa_cpu_type cputype;
63 unsigned int phy_base;
64 unsigned int phy_size;
65 void __iomem *virt_base;
66
67 struct pxa3xx_mfp_pin *mfp;
68 unsigned int num_mfp;
69 struct pxa3xx_pin_group *grps;
70 unsigned int num_grps;
71 struct pxa3xx_pmx_func *funcs;
72 unsigned int num_funcs;
73 unsigned int num_gpio;
74 struct pinctrl_desc *desc;
75 struct pinctrl_pin_desc *pads;
76 unsigned int num_pads;
77
78 unsigned ds_mask; /* drive strength mask */
79 unsigned ds_shift; /* drive strength shift */
80 unsigned slp_mask; /* sleep mask */
81 unsigned slp_input_low;
82 unsigned slp_input_high;
83 unsigned slp_output_low;
84 unsigned slp_output_high;
85 unsigned slp_float;
86};
87
88enum pxa3xx_pin_list {
89 GPIO0 = 0,
90 GPIO1,
91 GPIO2,
92 GPIO3,
93 GPIO4,
94 GPIO5,
95 GPIO6,
96 GPIO7,
97 GPIO8,
98 GPIO9,
99 GPIO10, /* 10 */
100 GPIO11,
101 GPIO12,
102 GPIO13,
103 GPIO14,
104 GPIO15,
105 GPIO16,
106 GPIO17,
107 GPIO18,
108 GPIO19,
109 GPIO20, /* 20 */
110 GPIO21,
111 GPIO22,
112 GPIO23,
113 GPIO24,
114 GPIO25,
115 GPIO26,
116 GPIO27,
117 GPIO28,
118 GPIO29,
119 GPIO30, /* 30 */
120 GPIO31,
121 GPIO32,
122 GPIO33,
123 GPIO34,
124 GPIO35,
125 GPIO36,
126 GPIO37,
127 GPIO38,
128 GPIO39,
129 GPIO40, /* 40 */
130 GPIO41,
131 GPIO42,
132 GPIO43,
133 GPIO44,
134 GPIO45,
135 GPIO46,
136 GPIO47,
137 GPIO48,
138 GPIO49,
139 GPIO50, /* 50 */
140 GPIO51,
141 GPIO52,
142 GPIO53,
143 GPIO54,
144 GPIO55,
145 GPIO56,
146 GPIO57,
147 GPIO58,
148 GPIO59,
149 GPIO60, /* 60 */
150 GPIO61,
151 GPIO62,
152 GPIO63,
153 GPIO64,
154 GPIO65,
155 GPIO66,
156 GPIO67,
157 GPIO68,
158 GPIO69,
159 GPIO70, /* 70 */
160 GPIO71,
161 GPIO72,
162 GPIO73,
163 GPIO74,
164 GPIO75,
165 GPIO76,
166 GPIO77,
167 GPIO78,
168 GPIO79,
169 GPIO80, /* 80 */
170 GPIO81,
171 GPIO82,
172 GPIO83,
173 GPIO84,
174 GPIO85,
175 GPIO86,
176 GPIO87,
177 GPIO88,
178 GPIO89,
179 GPIO90, /* 90 */
180 GPIO91,
181 GPIO92,
182 GPIO93,
183 GPIO94,
184 GPIO95,
185 GPIO96,
186 GPIO97,
187 GPIO98,
188 GPIO99,
189 GPIO100, /* 100 */
190 GPIO101,
191 GPIO102,
192 GPIO103,
193 GPIO104,
194 GPIO105,
195 GPIO106,
196 GPIO107,
197 GPIO108,
198 GPIO109,
199 GPIO110, /* 110 */
200 GPIO111,
201 GPIO112,
202 GPIO113,
203 GPIO114,
204 GPIO115,
205 GPIO116,
206 GPIO117,
207 GPIO118,
208 GPIO119,
209 GPIO120, /* 120 */
210 GPIO121,
211 GPIO122,
212 GPIO123,
213 GPIO124,
214 GPIO125,
215 GPIO126,
216 GPIO127,
217 GPIO128,
218 GPIO129,
219 GPIO130, /* 130 */
220 GPIO131,
221 GPIO132,
222 GPIO133,
223 GPIO134,
224 GPIO135,
225 GPIO136,
226 GPIO137,
227 GPIO138,
228 GPIO139,
229 GPIO140, /* 140 */
230 GPIO141,
231 GPIO142,
232 GPIO143,
233 GPIO144,
234 GPIO145,
235 GPIO146,
236 GPIO147,
237 GPIO148,
238 GPIO149,
239 GPIO150, /* 150 */
240 GPIO151,
241 GPIO152,
242 GPIO153,
243 GPIO154,
244 GPIO155,
245 GPIO156,
246 GPIO157,
247 GPIO158,
248 GPIO159,
249 GPIO160, /* 160 */
250 GPIO161,
251 GPIO162,
252 GPIO163,
253 GPIO164,
254 GPIO165,
255 GPIO166,
256 GPIO167,
257 GPIO168,
258 GPIO169,
259};
260
261extern int pxa3xx_pinctrl_register(struct platform_device *pdev,
262 struct pxa3xx_pinmux_info *info);
263extern int pxa3xx_pinctrl_unregister(struct platform_device *pdev);
264#endif /* __PINCTRL_PXA3XX_H */