| Rafał Miłecki | 8369ae3 | 2011-05-09 18:56:46 +0200 | [diff] [blame] | 1 | #ifndef LINUX_BCMA_REGS_H_ |
| 2 | #define LINUX_BCMA_REGS_H_ |
| 3 | |
| Rafał Miłecki | bb932ad | 2011-07-16 18:43:36 +0200 | [diff] [blame] | 4 | /* Some single registers are shared between many cores */ |
| 5 | /* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */ |
| 6 | #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */ |
| 7 | #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */ |
| 8 | #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */ |
| 9 | #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */ |
| 10 | #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ |
| 11 | #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ |
| 12 | #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ |
| 13 | #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */ |
| 14 | #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
| 15 | #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */ |
| 16 | #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */ |
| 17 | #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */ |
| 18 | #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */ |
| 19 | /* Is there any BCM4328 on BCMA bus? */ |
| 20 | #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ |
| 21 | #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ |
| 22 | |
| Rafał Miłecki | 8369ae3 | 2011-05-09 18:56:46 +0200 | [diff] [blame] | 23 | /* Agent registers (common for every core) */ |
| Rafał Miłecki | 2b5e332 | 2011-07-18 02:01:28 +0200 | [diff] [blame] | 24 | #define BCMA_IOCTL 0x0408 /* IO control */ |
| Rafał Miłecki | 8369ae3 | 2011-05-09 18:56:46 +0200 | [diff] [blame] | 25 | #define BCMA_IOCTL_CLK 0x0001 |
| 26 | #define BCMA_IOCTL_FGC 0x0002 |
| 27 | #define BCMA_IOCTL_CORE_BITS 0x3FFC |
| 28 | #define BCMA_IOCTL_PME_EN 0x4000 |
| 29 | #define BCMA_IOCTL_BIST_EN 0x8000 |
| Rafał Miłecki | 2b5e332 | 2011-07-18 02:01:28 +0200 | [diff] [blame] | 30 | #define BCMA_IOST 0x0500 /* IO status */ |
| 31 | #define BCMA_IOST_CORE_BITS 0x0FFF |
| 32 | #define BCMA_IOST_DMA64 0x1000 |
| 33 | #define BCMA_IOST_GATED_CLK 0x2000 |
| 34 | #define BCMA_IOST_BIST_ERROR 0x4000 |
| 35 | #define BCMA_IOST_BIST_DONE 0x8000 |
| Rafał Miłecki | 8369ae3 | 2011-05-09 18:56:46 +0200 | [diff] [blame] | 36 | #define BCMA_RESET_CTL 0x0800 |
| 37 | #define BCMA_RESET_CTL_RESET 0x0001 |
| 38 | |
| 39 | /* BCMA PCI config space registers. */ |
| 40 | #define BCMA_PCI_PMCSR 0x44 |
| 41 | #define BCMA_PCI_PE 0x100 |
| 42 | #define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */ |
| 43 | #define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */ |
| 44 | #define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */ |
| 45 | #define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */ |
| 46 | #define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */ |
| 47 | #define BCMA_PCI_IRQS 0x90 /* PCI interrupts */ |
| 48 | #define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */ |
| 49 | #define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */ |
| 50 | #define BCMA_PCI_BAR0_WIN2 0xAC |
| 51 | #define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */ |
| 52 | #define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */ |
| 53 | #define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */ |
| 54 | #define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ |
| 55 | #define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ |
| 56 | #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ |
| 57 | #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ |
| 58 | |
| Hauke Mehrtens | 49dc957 | 2012-01-31 00:03:35 +0100 | [diff] [blame] | 59 | /* SiliconBackplane Address Map. |
| 60 | * All regions may not exist on all chips. |
| 61 | */ |
| 62 | #define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */ |
| 63 | #define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ |
| 64 | #define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024) |
| 65 | #define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ |
| 66 | #define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ |
| 67 | #define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */ |
| 68 | |
| 69 | |
| 70 | #define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ |
| 71 | #define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */ |
| 72 | #define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ |
| 73 | #define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 |
| 74 | * (2 ZettaBytes), low 32 bits |
| 75 | */ |
| 76 | #define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 |
| 77 | * (2 ZettaBytes), high 32 bits |
| 78 | */ |
| 79 | |
| 80 | #define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */ |
| 81 | #define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */ |
| 82 | #define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2 |
| 83 | * (2 ZettaBytes), high 32 bits |
| 84 | */ |
| 85 | |
| Rafał Miłecki | 8369ae3 | 2011-05-09 18:56:46 +0200 | [diff] [blame] | 86 | #endif /* LINUX_BCMA_REGS_H_ */ |