Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $ |
| 2 | * |
| 3 | * isar.c ISAR (Siemens PSB 7110) specific routines |
| 4 | * |
| 5 | * Author Karsten Keil (keil@isdn4linux.de) |
| 6 | * |
| 7 | * This file is (c) under GNU General Public License |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include "hisax.h" |
| 13 | #include "isar.h" |
| 14 | #include "isdnl1.h" |
| 15 | #include <linux/interrupt.h> |
| 16 | |
| 17 | #define DBG_LOADFIRM 0 |
| 18 | #define DUMP_MBOXFRAME 2 |
| 19 | |
| 20 | #define DLE 0x10 |
| 21 | #define ETX 0x03 |
| 22 | |
| 23 | #define FAXMODCNT 13 |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 24 | static const u_char faxmodulation[] = {3,24,48,72,73,74,96,97,98,121,122,145,146}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | static u_int modmask = 0x1fff; |
| 26 | static int frm_extra_delay = 2; |
| 27 | static int para_TOA = 6; |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 28 | static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL" }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 30 | static void isar_setup(struct IsdnCardState *cs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para); |
| 32 | static void ll_deliver_faxstat(struct BCState *bcs, u_char status); |
| 33 | |
| 34 | static inline int |
| 35 | waitforHIA(struct IsdnCardState *cs, int timeout) |
| 36 | { |
| 37 | |
| 38 | while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) { |
| 39 | udelay(1); |
| 40 | timeout--; |
| 41 | } |
| 42 | if (!timeout) |
| 43 | printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n"); |
| 44 | return(timeout); |
| 45 | } |
| 46 | |
| 47 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 48 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, |
| 50 | u_char *msg) |
| 51 | { |
| 52 | int i; |
| 53 | |
| 54 | if (!waitforHIA(cs, 4000)) |
| 55 | return(0); |
| 56 | #if DUMP_MBOXFRAME |
| 57 | if (cs->debug & L1_DEB_HSCX) |
| 58 | debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len); |
| 59 | #endif |
| 60 | cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); |
| 61 | cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len); |
| 62 | cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0); |
| 63 | if (msg && len) { |
| 64 | cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]); |
| 65 | for (i=1; i<len; i++) |
| 66 | cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]); |
| 67 | #if DUMP_MBOXFRAME>1 |
| 68 | if (cs->debug & L1_DEB_HSCX_FIFO) { |
| 69 | char tmp[256], *t; |
| 70 | |
| 71 | i = len; |
| 72 | while (i>0) { |
| 73 | t = tmp; |
| 74 | t += sprintf(t, "sendmbox cnt %d", len); |
| 75 | QuickHex(t, &msg[len-i], (i>64) ? 64:i); |
| 76 | debugl1(cs, tmp); |
| 77 | i -= 64; |
| 78 | } |
| 79 | } |
| 80 | #endif |
| 81 | } |
| 82 | cs->BC_Write_Reg(cs, 1, ISAR_HIS, his); |
| 83 | waitforHIA(cs, 10000); |
| 84 | return(1); |
| 85 | } |
| 86 | |
| 87 | /* Call only with IRQ disabled !!! */ |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 88 | static inline void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg) |
| 90 | { |
| 91 | int i; |
| 92 | |
| 93 | cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0); |
| 94 | if (msg && ireg->clsb) { |
| 95 | msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX); |
| 96 | for (i=1; i < ireg->clsb; i++) |
| 97 | msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX); |
| 98 | #if DUMP_MBOXFRAME>1 |
| 99 | if (cs->debug & L1_DEB_HSCX_FIFO) { |
| 100 | char tmp[256], *t; |
| 101 | |
| 102 | i = ireg->clsb; |
| 103 | while (i>0) { |
| 104 | t = tmp; |
| 105 | t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb); |
| 106 | QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i); |
| 107 | debugl1(cs, tmp); |
| 108 | i -= 64; |
| 109 | } |
| 110 | } |
| 111 | #endif |
| 112 | } |
| 113 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 114 | } |
| 115 | |
| 116 | /* Call only with IRQ disabled !!! */ |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 117 | static inline void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg) |
| 119 | { |
| 120 | ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS); |
| 121 | ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H); |
| 122 | ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L); |
| 123 | #if DUMP_MBOXFRAME |
| 124 | if (cs->debug & L1_DEB_HSCX) |
| 125 | debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb, |
| 126 | ireg->clsb); |
| 127 | #endif |
| 128 | } |
| 129 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 130 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | waitrecmsg(struct IsdnCardState *cs, u_char *len, |
| 132 | u_char *msg, int maxdelay) |
| 133 | { |
| 134 | int timeout = 0; |
| 135 | struct isar_reg *ir = cs->bcs[0].hw.isar.reg; |
| 136 | |
| 137 | |
| 138 | while((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) && |
| 139 | (timeout++ < maxdelay)) |
| 140 | udelay(1); |
| 141 | if (timeout >= maxdelay) { |
| 142 | printk(KERN_WARNING"isar recmsg IRQSTA timeout\n"); |
| 143 | return(0); |
| 144 | } |
| 145 | get_irq_infos(cs, ir); |
| 146 | rcv_mbox(cs, ir, msg); |
| 147 | *len = ir->clsb; |
| 148 | return(1); |
| 149 | } |
| 150 | |
| 151 | int |
| 152 | ISARVersion(struct IsdnCardState *cs, char *s) |
| 153 | { |
| 154 | int ver; |
| 155 | u_char msg[] = ISAR_MSG_HWVER; |
| 156 | u_char tmp[64]; |
| 157 | u_char len; |
| 158 | u_long flags; |
| 159 | int debug; |
| 160 | |
| 161 | cs->cardmsg(cs, CARD_RESET, NULL); |
| 162 | spin_lock_irqsave(&cs->lock, flags); |
| 163 | /* disable ISAR IRQ */ |
| 164 | cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); |
| 165 | debug = cs->debug; |
| 166 | cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO); |
| 167 | if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) { |
| 168 | spin_unlock_irqrestore(&cs->lock, flags); |
| 169 | return(-1); |
| 170 | } |
| 171 | if (!waitrecmsg(cs, &len, tmp, 100000)) { |
| 172 | spin_unlock_irqrestore(&cs->lock, flags); |
| 173 | return(-2); |
| 174 | } |
| 175 | cs->debug = debug; |
| 176 | if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) { |
| 177 | if (len == 1) { |
| 178 | ver = tmp[0] & 0xf; |
| 179 | printk(KERN_INFO "%s ISAR version %d\n", s, ver); |
| 180 | } else |
| 181 | ver = -3; |
| 182 | } else |
| 183 | ver = -4; |
| 184 | spin_unlock_irqrestore(&cs->lock, flags); |
| 185 | return(ver); |
| 186 | } |
| 187 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 188 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf) |
| 190 | { |
| 191 | int ret, size, cnt, debug; |
| 192 | u_char len, nom, noc; |
| 193 | u_short sadr, left, *sp; |
| 194 | u_char __user *p = buf; |
| 195 | u_char *msg, *tmpmsg, *mp, tmp[64]; |
| 196 | u_long flags; |
| 197 | struct isar_reg *ireg = cs->bcs[0].hw.isar.reg; |
| 198 | |
| 199 | struct {u_short sadr; |
| 200 | u_short len; |
| 201 | u_short d_key; |
| 202 | } blk_head; |
| 203 | |
| 204 | #define BLK_HEAD_SIZE 6 |
| 205 | if (1 != (ret = ISARVersion(cs, "Testing"))) { |
| 206 | printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret); |
| 207 | return(1); |
| 208 | } |
| 209 | debug = cs->debug; |
| 210 | #if DBG_LOADFIRM<2 |
| 211 | cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO); |
| 212 | #endif |
| 213 | |
| 214 | if ((ret = copy_from_user(&size, p, sizeof(int)))) { |
| 215 | printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret); |
| 216 | return ret; |
| 217 | } |
| 218 | p += sizeof(int); |
| 219 | printk(KERN_DEBUG"isar_load_firmware size: %d\n", size); |
| 220 | cnt = 0; |
| 221 | /* disable ISAR IRQ */ |
| 222 | cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); |
| 223 | if (!(msg = kmalloc(256, GFP_KERNEL))) { |
| 224 | printk(KERN_ERR"isar_load_firmware no buffer\n"); |
| 225 | return (1); |
| 226 | } |
| 227 | if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) { |
| 228 | printk(KERN_ERR"isar_load_firmware no tmp buffer\n"); |
| 229 | kfree(msg); |
| 230 | return (1); |
| 231 | } |
| 232 | spin_lock_irqsave(&cs->lock, flags); |
| 233 | /* disable ISAR IRQ */ |
| 234 | cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); |
| 235 | spin_unlock_irqrestore(&cs->lock, flags); |
| 236 | while (cnt < size) { |
| 237 | if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) { |
| 238 | printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret); |
| 239 | goto reterror; |
| 240 | } |
| 241 | #ifdef __BIG_ENDIAN |
| 242 | sadr = (blk_head.sadr & 0xff)*256 + blk_head.sadr/256; |
| 243 | blk_head.sadr = sadr; |
| 244 | sadr = (blk_head.len & 0xff)*256 + blk_head.len/256; |
| 245 | blk_head.len = sadr; |
| 246 | sadr = (blk_head.d_key & 0xff)*256 + blk_head.d_key/256; |
| 247 | blk_head.d_key = sadr; |
| 248 | #endif /* __BIG_ENDIAN */ |
| 249 | cnt += BLK_HEAD_SIZE; |
| 250 | p += BLK_HEAD_SIZE; |
| 251 | printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n", |
| 252 | blk_head.sadr, blk_head.len, blk_head.d_key & 0xff); |
| 253 | sadr = blk_head.sadr; |
| 254 | left = blk_head.len; |
| 255 | spin_lock_irqsave(&cs->lock, flags); |
| 256 | if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) { |
| 257 | printk(KERN_ERR"isar sendmsg dkey failed\n"); |
| 258 | ret = 1;goto reterr_unlock; |
| 259 | } |
| 260 | if (!waitrecmsg(cs, &len, tmp, 100000)) { |
| 261 | printk(KERN_ERR"isar waitrecmsg dkey failed\n"); |
| 262 | ret = 1;goto reterr_unlock; |
| 263 | } |
| 264 | if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) { |
| 265 | printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n", |
| 266 | ireg->iis, ireg->cmsb, len); |
| 267 | ret = 1;goto reterr_unlock; |
| 268 | } |
| 269 | spin_unlock_irqrestore(&cs->lock, flags); |
| 270 | while (left>0) { |
| 271 | if (left > 126) |
| 272 | noc = 126; |
| 273 | else |
| 274 | noc = left; |
| 275 | nom = 2*noc; |
| 276 | mp = msg; |
| 277 | *mp++ = sadr / 256; |
| 278 | *mp++ = sadr % 256; |
| 279 | left -= noc; |
| 280 | *mp++ = noc; |
| 281 | if ((ret = copy_from_user(tmpmsg, p, nom))) { |
| 282 | printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret); |
| 283 | goto reterror; |
| 284 | } |
| 285 | p += nom; |
| 286 | cnt += nom; |
| 287 | nom += 3; |
| 288 | sp = (u_short *)tmpmsg; |
| 289 | #if DBG_LOADFIRM |
| 290 | printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n", |
| 291 | noc, sadr, left); |
| 292 | #endif |
| 293 | sadr += noc; |
| 294 | while(noc) { |
| 295 | #ifdef __BIG_ENDIAN |
| 296 | *mp++ = *sp % 256; |
| 297 | *mp++ = *sp / 256; |
| 298 | #else |
| 299 | *mp++ = *sp / 256; |
| 300 | *mp++ = *sp % 256; |
| 301 | #endif /* __BIG_ENDIAN */ |
| 302 | sp++; |
| 303 | noc--; |
| 304 | } |
| 305 | spin_lock_irqsave(&cs->lock, flags); |
| 306 | if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) { |
| 307 | printk(KERN_ERR"isar sendmsg prog failed\n"); |
| 308 | ret = 1;goto reterr_unlock; |
| 309 | } |
| 310 | if (!waitrecmsg(cs, &len, tmp, 100000)) { |
| 311 | printk(KERN_ERR"isar waitrecmsg prog failed\n"); |
| 312 | ret = 1;goto reterr_unlock; |
| 313 | } |
| 314 | if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) { |
| 315 | printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n", |
| 316 | ireg->iis, ireg->cmsb, len); |
| 317 | ret = 1;goto reterr_unlock; |
| 318 | } |
| 319 | spin_unlock_irqrestore(&cs->lock, flags); |
| 320 | } |
| 321 | printk(KERN_DEBUG"isar firmware block %5d words loaded\n", |
| 322 | blk_head.len); |
| 323 | } |
| 324 | /* 10ms delay */ |
| 325 | cnt = 10; |
| 326 | while (cnt--) |
| 327 | udelay(1000); |
| 328 | msg[0] = 0xff; |
| 329 | msg[1] = 0xfe; |
| 330 | ireg->bstat = 0; |
| 331 | spin_lock_irqsave(&cs->lock, flags); |
| 332 | if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) { |
| 333 | printk(KERN_ERR"isar sendmsg start dsp failed\n"); |
| 334 | ret = 1;goto reterr_unlock; |
| 335 | } |
| 336 | if (!waitrecmsg(cs, &len, tmp, 100000)) { |
| 337 | printk(KERN_ERR"isar waitrecmsg start dsp failed\n"); |
| 338 | ret = 1;goto reterr_unlock; |
| 339 | } |
| 340 | if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) { |
| 341 | printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n", |
| 342 | ireg->iis, ireg->cmsb, len); |
| 343 | ret = 1;goto reterr_unlock; |
| 344 | } else |
| 345 | printk(KERN_DEBUG"isar start dsp success\n"); |
| 346 | /* NORMAL mode entered */ |
| 347 | /* Enable IRQs of ISAR */ |
| 348 | cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA); |
| 349 | spin_unlock_irqrestore(&cs->lock, flags); |
| 350 | cnt = 1000; /* max 1s */ |
| 351 | while ((!ireg->bstat) && cnt) { |
| 352 | udelay(1000); |
| 353 | cnt--; |
| 354 | } |
| 355 | if (!cnt) { |
| 356 | printk(KERN_ERR"isar no general status event received\n"); |
| 357 | ret = 1;goto reterror; |
| 358 | } else { |
| 359 | printk(KERN_DEBUG"isar general status event %x\n", |
| 360 | ireg->bstat); |
| 361 | } |
| 362 | /* 10ms delay */ |
| 363 | cnt = 10; |
| 364 | while (cnt--) |
| 365 | udelay(1000); |
| 366 | spin_lock_irqsave(&cs->lock, flags); |
| 367 | ireg->iis = 0; |
| 368 | if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) { |
| 369 | printk(KERN_ERR"isar sendmsg self tst failed\n"); |
| 370 | ret = 1;goto reterr_unlock; |
| 371 | } |
| 372 | cnt = 10000; /* max 100 ms */ |
| 373 | spin_unlock_irqrestore(&cs->lock, flags); |
| 374 | while ((ireg->iis != ISAR_IIS_DIAG) && cnt) { |
| 375 | udelay(10); |
| 376 | cnt--; |
| 377 | } |
| 378 | udelay(1000); |
| 379 | if (!cnt) { |
| 380 | printk(KERN_ERR"isar no self tst response\n"); |
| 381 | ret = 1;goto reterror; |
| 382 | } |
| 383 | if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1) |
| 384 | && (ireg->par[0] == 0)) { |
| 385 | printk(KERN_DEBUG"isar selftest OK\n"); |
| 386 | } else { |
| 387 | printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n", |
| 388 | ireg->cmsb, ireg->clsb, ireg->par[0]); |
| 389 | ret = 1;goto reterror; |
| 390 | } |
| 391 | spin_lock_irqsave(&cs->lock, flags); |
| 392 | ireg->iis = 0; |
| 393 | if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) { |
| 394 | printk(KERN_ERR"isar RQST SVN failed\n"); |
| 395 | ret = 1;goto reterr_unlock; |
| 396 | } |
| 397 | spin_unlock_irqrestore(&cs->lock, flags); |
| 398 | cnt = 30000; /* max 300 ms */ |
| 399 | while ((ireg->iis != ISAR_IIS_DIAG) && cnt) { |
| 400 | udelay(10); |
| 401 | cnt--; |
| 402 | } |
| 403 | udelay(1000); |
| 404 | if (!cnt) { |
| 405 | printk(KERN_ERR"isar no SVN response\n"); |
| 406 | ret = 1;goto reterror; |
| 407 | } else { |
| 408 | if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1)) |
| 409 | printk(KERN_DEBUG"isar software version %#x\n", |
| 410 | ireg->par[0]); |
| 411 | else { |
| 412 | printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n", |
| 413 | ireg->cmsb, ireg->clsb, cnt); |
| 414 | ret = 1;goto reterror; |
| 415 | } |
| 416 | } |
| 417 | spin_lock_irqsave(&cs->lock, flags); |
| 418 | cs->debug = debug; |
| 419 | isar_setup(cs); |
| 420 | |
| 421 | ret = 0; |
| 422 | reterr_unlock: |
| 423 | spin_unlock_irqrestore(&cs->lock, flags); |
| 424 | reterror: |
| 425 | cs->debug = debug; |
| 426 | if (ret) |
| 427 | /* disable ISAR IRQ */ |
| 428 | cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); |
| 429 | kfree(msg); |
| 430 | kfree(tmpmsg); |
| 431 | return(ret); |
| 432 | } |
| 433 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | #define B_LL_NOCARRIER 8 |
| 435 | #define B_LL_CONNECT 9 |
| 436 | #define B_LL_OK 10 |
| 437 | |
| 438 | static void |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 439 | isar_bh(struct work_struct *work) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | { |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 441 | struct BCState *bcs = container_of(work, struct BCState, tqueue); |
| 442 | |
Jiri Kosina | 3899210 | 2007-03-26 21:32:19 -0800 | [diff] [blame] | 443 | BChannel_bh(work); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event)) |
| 445 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR); |
| 446 | if (test_and_clear_bit(B_LL_CONNECT, &bcs->event)) |
| 447 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT); |
| 448 | if (test_and_clear_bit(B_LL_OK, &bcs->event)) |
| 449 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK); |
| 450 | } |
| 451 | |
| 452 | static void |
| 453 | send_DLE_ETX(struct BCState *bcs) |
| 454 | { |
| 455 | u_char dleetx[2] = {DLE,ETX}; |
| 456 | struct sk_buff *skb; |
| 457 | |
| 458 | if ((skb = dev_alloc_skb(2))) { |
| 459 | memcpy(skb_put(skb, 2), dleetx, 2); |
| 460 | skb_queue_tail(&bcs->rqueue, skb); |
| 461 | schedule_event(bcs, B_RCVBUFREADY); |
| 462 | } else { |
| 463 | printk(KERN_WARNING "HiSax: skb out of memory\n"); |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | static inline int |
| 468 | dle_count(unsigned char *buf, int len) |
| 469 | { |
| 470 | int count = 0; |
| 471 | |
| 472 | while (len--) |
| 473 | if (*buf++ == DLE) |
| 474 | count++; |
| 475 | return count; |
| 476 | } |
| 477 | |
| 478 | static inline void |
| 479 | insert_dle(unsigned char *dest, unsigned char *src, int count) { |
| 480 | /* <DLE> in input stream have to be flagged as <DLE><DLE> */ |
| 481 | while (count--) { |
| 482 | *dest++ = *src; |
| 483 | if (*src++ == DLE) |
| 484 | *dest++ = DLE; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | static void |
| 489 | isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs) |
| 490 | { |
| 491 | u_char *ptr; |
| 492 | struct sk_buff *skb; |
| 493 | struct isar_reg *ireg = bcs->hw.isar.reg; |
| 494 | |
| 495 | if (!ireg->clsb) { |
| 496 | debugl1(cs, "isar zero len frame"); |
| 497 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 498 | return; |
| 499 | } |
| 500 | switch (bcs->mode) { |
| 501 | case L1_MODE_NULL: |
| 502 | debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x", |
| 503 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 504 | printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n", |
| 505 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 506 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 507 | break; |
| 508 | case L1_MODE_TRANS: |
| 509 | case L1_MODE_V32: |
| 510 | if ((skb = dev_alloc_skb(ireg->clsb))) { |
| 511 | rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb)); |
| 512 | skb_queue_tail(&bcs->rqueue, skb); |
| 513 | schedule_event(bcs, B_RCVBUFREADY); |
| 514 | } else { |
| 515 | printk(KERN_WARNING "HiSax: skb out of memory\n"); |
| 516 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 517 | } |
| 518 | break; |
| 519 | case L1_MODE_HDLC: |
| 520 | if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) { |
| 521 | if (cs->debug & L1_DEB_WARN) |
| 522 | debugl1(cs, "isar_rcv_frame: incoming packet too large"); |
| 523 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 524 | bcs->hw.isar.rcvidx = 0; |
| 525 | } else if (ireg->cmsb & HDLC_ERROR) { |
| 526 | if (cs->debug & L1_DEB_WARN) |
| 527 | debugl1(cs, "isar frame error %x len %d", |
| 528 | ireg->cmsb, ireg->clsb); |
| 529 | #ifdef ERROR_STATISTIC |
| 530 | if (ireg->cmsb & HDLC_ERR_RER) |
| 531 | bcs->err_inv++; |
| 532 | if (ireg->cmsb & HDLC_ERR_CER) |
| 533 | bcs->err_crc++; |
| 534 | #endif |
| 535 | bcs->hw.isar.rcvidx = 0; |
| 536 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 537 | } else { |
| 538 | if (ireg->cmsb & HDLC_FSD) |
| 539 | bcs->hw.isar.rcvidx = 0; |
| 540 | ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx; |
| 541 | bcs->hw.isar.rcvidx += ireg->clsb; |
| 542 | rcv_mbox(cs, ireg, ptr); |
| 543 | if (ireg->cmsb & HDLC_FED) { |
| 544 | if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */ |
| 545 | if (cs->debug & L1_DEB_WARN) |
| 546 | debugl1(cs, "isar frame to short %d", |
| 547 | bcs->hw.isar.rcvidx); |
| 548 | } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) { |
| 549 | printk(KERN_WARNING "ISAR: receive out of memory\n"); |
| 550 | } else { |
| 551 | memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2), |
| 552 | bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2); |
| 553 | skb_queue_tail(&bcs->rqueue, skb); |
| 554 | schedule_event(bcs, B_RCVBUFREADY); |
| 555 | } |
| 556 | bcs->hw.isar.rcvidx = 0; |
| 557 | } |
| 558 | } |
| 559 | break; |
| 560 | case L1_MODE_FAX: |
| 561 | if (bcs->hw.isar.state != STFAX_ACTIV) { |
| 562 | if (cs->debug & L1_DEB_WARN) |
| 563 | debugl1(cs, "isar_rcv_frame: not ACTIV"); |
| 564 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 565 | bcs->hw.isar.rcvidx = 0; |
| 566 | break; |
| 567 | } |
| 568 | if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) { |
| 569 | rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf); |
| 570 | bcs->hw.isar.rcvidx = ireg->clsb + |
| 571 | dle_count(bcs->hw.isar.rcvbuf, ireg->clsb); |
| 572 | if (cs->debug & L1_DEB_HSCX) |
| 573 | debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)", |
| 574 | ireg->clsb, bcs->hw.isar.rcvidx); |
| 575 | if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) { |
| 576 | insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx), |
| 577 | bcs->hw.isar.rcvbuf, ireg->clsb); |
| 578 | skb_queue_tail(&bcs->rqueue, skb); |
| 579 | schedule_event(bcs, B_RCVBUFREADY); |
| 580 | if (ireg->cmsb & SART_NMD) { /* ABORT */ |
| 581 | if (cs->debug & L1_DEB_WARN) |
| 582 | debugl1(cs, "isar_rcv_frame: no more data"); |
| 583 | bcs->hw.isar.rcvidx = 0; |
| 584 | send_DLE_ETX(bcs); |
| 585 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | |
| 586 | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, |
| 587 | 0, NULL); |
| 588 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 589 | schedule_event(bcs, B_LL_NOCARRIER); |
| 590 | } |
| 591 | } else { |
| 592 | printk(KERN_WARNING "HiSax: skb out of memory\n"); |
| 593 | } |
| 594 | break; |
| 595 | } |
| 596 | if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) { |
| 597 | if (cs->debug & L1_DEB_WARN) |
| 598 | debugl1(cs, "isar_rcv_frame: unknown fax mode %x", |
| 599 | bcs->hw.isar.cmd); |
| 600 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 601 | bcs->hw.isar.rcvidx = 0; |
| 602 | break; |
| 603 | } |
| 604 | /* PCTRL_CMD_FRH */ |
| 605 | if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) { |
| 606 | if (cs->debug & L1_DEB_WARN) |
| 607 | debugl1(cs, "isar_rcv_frame: incoming packet too large"); |
| 608 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 609 | bcs->hw.isar.rcvidx = 0; |
| 610 | } else if (ireg->cmsb & HDLC_ERROR) { |
| 611 | if (cs->debug & L1_DEB_WARN) |
| 612 | debugl1(cs, "isar frame error %x len %d", |
| 613 | ireg->cmsb, ireg->clsb); |
| 614 | bcs->hw.isar.rcvidx = 0; |
| 615 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 616 | } else { |
| 617 | if (ireg->cmsb & HDLC_FSD) { |
| 618 | bcs->hw.isar.rcvidx = 0; |
| 619 | } |
| 620 | ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx; |
| 621 | bcs->hw.isar.rcvidx += ireg->clsb; |
| 622 | rcv_mbox(cs, ireg, ptr); |
| 623 | if (ireg->cmsb & HDLC_FED) { |
| 624 | int len = bcs->hw.isar.rcvidx + |
| 625 | dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx); |
| 626 | if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */ |
| 627 | if (cs->debug & L1_DEB_WARN) |
| 628 | debugl1(cs, "isar frame to short %d", |
| 629 | bcs->hw.isar.rcvidx); |
| 630 | printk(KERN_WARNING "ISAR: frame to short %d\n", |
| 631 | bcs->hw.isar.rcvidx); |
| 632 | } else if (!(skb = dev_alloc_skb(len))) { |
| 633 | printk(KERN_WARNING "ISAR: receive out of memory\n"); |
| 634 | } else { |
| 635 | insert_dle((u_char *)skb_put(skb, len), |
| 636 | bcs->hw.isar.rcvbuf, |
| 637 | bcs->hw.isar.rcvidx); |
| 638 | skb_queue_tail(&bcs->rqueue, skb); |
| 639 | schedule_event(bcs, B_RCVBUFREADY); |
| 640 | send_DLE_ETX(bcs); |
| 641 | schedule_event(bcs, B_LL_OK); |
| 642 | test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag); |
| 643 | } |
| 644 | bcs->hw.isar.rcvidx = 0; |
| 645 | } |
| 646 | } |
| 647 | if (ireg->cmsb & SART_NMD) { /* ABORT */ |
| 648 | if (cs->debug & L1_DEB_WARN) |
| 649 | debugl1(cs, "isar_rcv_frame: no more data"); |
| 650 | bcs->hw.isar.rcvidx = 0; |
| 651 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | |
| 652 | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL); |
| 653 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 654 | if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) { |
| 655 | send_DLE_ETX(bcs); |
| 656 | schedule_event(bcs, B_LL_NOCARRIER); |
| 657 | } |
| 658 | } |
| 659 | break; |
| 660 | default: |
| 661 | printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode); |
| 662 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 663 | break; |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | void |
| 668 | isar_fill_fifo(struct BCState *bcs) |
| 669 | { |
| 670 | struct IsdnCardState *cs = bcs->cs; |
| 671 | int count; |
| 672 | u_char msb; |
| 673 | u_char *ptr; |
| 674 | |
| 675 | if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) |
| 676 | debugl1(cs, "isar_fill_fifo"); |
| 677 | if (!bcs->tx_skb) |
| 678 | return; |
| 679 | if (bcs->tx_skb->len <= 0) |
| 680 | return; |
| 681 | if (!(bcs->hw.isar.reg->bstat & |
| 682 | (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2))) |
| 683 | return; |
| 684 | if (bcs->tx_skb->len > bcs->hw.isar.mml) { |
| 685 | msb = 0; |
| 686 | count = bcs->hw.isar.mml; |
| 687 | } else { |
| 688 | count = bcs->tx_skb->len; |
| 689 | msb = HDLC_FED; |
| 690 | } |
| 691 | ptr = bcs->tx_skb->data; |
| 692 | if (!bcs->hw.isar.txcnt) { |
| 693 | msb |= HDLC_FST; |
| 694 | if ((bcs->mode == L1_MODE_FAX) && |
| 695 | (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) { |
| 696 | if (bcs->tx_skb->len > 1) { |
| 697 | if ((ptr[0]== 0xff) && (ptr[1] == 0x13)) |
| 698 | /* last frame */ |
| 699 | test_and_set_bit(BC_FLG_LASTDATA, |
| 700 | &bcs->Flag); |
| 701 | } |
| 702 | } |
| 703 | } |
| 704 | skb_pull(bcs->tx_skb, count); |
| 705 | bcs->tx_cnt -= count; |
| 706 | bcs->hw.isar.txcnt += count; |
| 707 | switch (bcs->mode) { |
| 708 | case L1_MODE_NULL: |
| 709 | printk(KERN_ERR"isar_fill_fifo wrong mode 0\n"); |
| 710 | break; |
| 711 | case L1_MODE_TRANS: |
| 712 | case L1_MODE_V32: |
| 713 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, |
| 714 | 0, count, ptr); |
| 715 | break; |
| 716 | case L1_MODE_HDLC: |
| 717 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, |
| 718 | msb, count, ptr); |
| 719 | break; |
| 720 | case L1_MODE_FAX: |
| 721 | if (bcs->hw.isar.state != STFAX_ACTIV) { |
| 722 | if (cs->debug & L1_DEB_WARN) |
| 723 | debugl1(cs, "isar_fill_fifo: not ACTIV"); |
| 724 | } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) { |
| 725 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, |
| 726 | msb, count, ptr); |
| 727 | } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) { |
| 728 | sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, |
| 729 | 0, count, ptr); |
| 730 | } else { |
| 731 | if (cs->debug & L1_DEB_WARN) |
| 732 | debugl1(cs, "isar_fill_fifo: not FTH/FTM"); |
| 733 | } |
| 734 | break; |
| 735 | default: |
| 736 | if (cs->debug) |
| 737 | debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode); |
| 738 | printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode); |
| 739 | break; |
| 740 | } |
| 741 | } |
| 742 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 743 | static inline |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath) |
| 745 | { |
| 746 | if ((!dpath) || (dpath == 3)) |
| 747 | return(NULL); |
| 748 | if (cs->bcs[0].hw.isar.dpath == dpath) |
| 749 | return(&cs->bcs[0]); |
| 750 | if (cs->bcs[1].hw.isar.dpath == dpath) |
| 751 | return(&cs->bcs[1]); |
| 752 | return(NULL); |
| 753 | } |
| 754 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 755 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | send_frames(struct BCState *bcs) |
| 757 | { |
| 758 | if (bcs->tx_skb) { |
| 759 | if (bcs->tx_skb->len) { |
| 760 | isar_fill_fifo(bcs); |
| 761 | return; |
| 762 | } else { |
| 763 | if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) && |
| 764 | (PACKET_NOACK != bcs->tx_skb->pkt_type)) { |
| 765 | u_long flags; |
| 766 | spin_lock_irqsave(&bcs->aclock, flags); |
| 767 | bcs->ackcnt += bcs->hw.isar.txcnt; |
| 768 | spin_unlock_irqrestore(&bcs->aclock, flags); |
| 769 | schedule_event(bcs, B_ACKPENDING); |
| 770 | } |
| 771 | if (bcs->mode == L1_MODE_FAX) { |
| 772 | if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) { |
| 773 | if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) { |
| 774 | test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag); |
| 775 | } |
| 776 | } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) { |
| 777 | if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) { |
| 778 | test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag); |
| 779 | test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag); |
| 780 | } |
| 781 | } |
| 782 | } |
| 783 | dev_kfree_skb_any(bcs->tx_skb); |
| 784 | bcs->hw.isar.txcnt = 0; |
| 785 | bcs->tx_skb = NULL; |
| 786 | } |
| 787 | } |
| 788 | if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { |
| 789 | bcs->hw.isar.txcnt = 0; |
| 790 | test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); |
| 791 | isar_fill_fifo(bcs); |
| 792 | } else { |
| 793 | if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) { |
| 794 | if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) { |
| 795 | if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) { |
| 796 | u_char dummy = 0; |
| 797 | sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) | |
| 798 | ISAR_HIS_SDATA, 0x01, 1, &dummy); |
| 799 | } |
| 800 | test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag); |
| 801 | } else { |
| 802 | schedule_event(bcs, B_LL_CONNECT); |
| 803 | } |
| 804 | } |
| 805 | test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); |
| 806 | schedule_event(bcs, B_XMTBUFREADY); |
| 807 | } |
| 808 | } |
| 809 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 810 | static inline void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | check_send(struct IsdnCardState *cs, u_char rdm) |
| 812 | { |
| 813 | struct BCState *bcs; |
| 814 | |
| 815 | if (rdm & BSTAT_RDM1) { |
| 816 | if ((bcs = sel_bcs_isar(cs, 1))) { |
| 817 | if (bcs->mode) { |
| 818 | send_frames(bcs); |
| 819 | } |
| 820 | } |
| 821 | } |
| 822 | if (rdm & BSTAT_RDM2) { |
| 823 | if ((bcs = sel_bcs_isar(cs, 2))) { |
| 824 | if (bcs->mode) { |
| 825 | send_frames(bcs); |
| 826 | } |
| 827 | } |
| 828 | } |
| 829 | |
| 830 | } |
| 831 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 832 | static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", |
| 833 | "NODEF4", "300", "600", "1200", "2400", |
| 834 | "4800", "7200", "9600nt", "9600t", "12000", |
| 835 | "14400", "WRONG"}; |
| 836 | static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21", |
| 837 | "Bell103", "V23", "Bell202", "V17", "V29", |
| 838 | "V27ter"}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | |
| 840 | static void |
| 841 | isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) { |
| 842 | struct IsdnCardState *cs = bcs->cs; |
| 843 | u_char ril = ireg->par[0]; |
| 844 | u_char rim; |
| 845 | |
| 846 | if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags)) |
| 847 | return; |
| 848 | if (ril > 14) { |
| 849 | if (cs->debug & L1_DEB_WARN) |
| 850 | debugl1(cs, "wrong pstrsp ril=%d",ril); |
| 851 | ril = 15; |
| 852 | } |
| 853 | switch(ireg->par[1]) { |
| 854 | case 0: |
| 855 | rim = 0; |
| 856 | break; |
| 857 | case 0x20: |
| 858 | rim = 2; |
| 859 | break; |
| 860 | case 0x40: |
| 861 | rim = 3; |
| 862 | break; |
| 863 | case 0x41: |
| 864 | rim = 4; |
| 865 | break; |
| 866 | case 0x51: |
| 867 | rim = 5; |
| 868 | break; |
| 869 | case 0x61: |
| 870 | rim = 6; |
| 871 | break; |
| 872 | case 0x71: |
| 873 | rim = 7; |
| 874 | break; |
| 875 | case 0x82: |
| 876 | rim = 8; |
| 877 | break; |
| 878 | case 0x92: |
| 879 | rim = 9; |
| 880 | break; |
| 881 | case 0xa2: |
| 882 | rim = 10; |
| 883 | break; |
| 884 | default: |
| 885 | rim = 1; |
| 886 | break; |
| 887 | } |
| 888 | sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]); |
| 889 | bcs->conmsg = bcs->hw.isar.conmsg; |
| 890 | if (cs->debug & L1_DEB_HSCX) |
| 891 | debugl1(cs, "pump strsp %s", bcs->conmsg); |
| 892 | } |
| 893 | |
| 894 | static void |
| 895 | isar_pump_statev_modem(struct BCState *bcs, u_char devt) { |
| 896 | struct IsdnCardState *cs = bcs->cs; |
| 897 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 898 | |
| 899 | switch(devt) { |
| 900 | case PSEV_10MS_TIMER: |
| 901 | if (cs->debug & L1_DEB_HSCX) |
| 902 | debugl1(cs, "pump stev TIMER"); |
| 903 | break; |
| 904 | case PSEV_CON_ON: |
| 905 | if (cs->debug & L1_DEB_HSCX) |
| 906 | debugl1(cs, "pump stev CONNECT"); |
| 907 | l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL); |
| 908 | break; |
| 909 | case PSEV_CON_OFF: |
| 910 | if (cs->debug & L1_DEB_HSCX) |
| 911 | debugl1(cs, "pump stev NO CONNECT"); |
| 912 | sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); |
| 913 | l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL); |
| 914 | break; |
| 915 | case PSEV_V24_OFF: |
| 916 | if (cs->debug & L1_DEB_HSCX) |
| 917 | debugl1(cs, "pump stev V24 OFF"); |
| 918 | break; |
| 919 | case PSEV_CTS_ON: |
| 920 | if (cs->debug & L1_DEB_HSCX) |
| 921 | debugl1(cs, "pump stev CTS ON"); |
| 922 | break; |
| 923 | case PSEV_CTS_OFF: |
| 924 | if (cs->debug & L1_DEB_HSCX) |
| 925 | debugl1(cs, "pump stev CTS OFF"); |
| 926 | break; |
| 927 | case PSEV_DCD_ON: |
| 928 | if (cs->debug & L1_DEB_HSCX) |
| 929 | debugl1(cs, "pump stev CARRIER ON"); |
| 930 | test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags); |
| 931 | sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); |
| 932 | break; |
| 933 | case PSEV_DCD_OFF: |
| 934 | if (cs->debug & L1_DEB_HSCX) |
| 935 | debugl1(cs, "pump stev CARRIER OFF"); |
| 936 | break; |
| 937 | case PSEV_DSR_ON: |
| 938 | if (cs->debug & L1_DEB_HSCX) |
| 939 | debugl1(cs, "pump stev DSR ON"); |
| 940 | break; |
| 941 | case PSEV_DSR_OFF: |
| 942 | if (cs->debug & L1_DEB_HSCX) |
| 943 | debugl1(cs, "pump stev DSR_OFF"); |
| 944 | break; |
| 945 | case PSEV_REM_RET: |
| 946 | if (cs->debug & L1_DEB_HSCX) |
| 947 | debugl1(cs, "pump stev REMOTE RETRAIN"); |
| 948 | break; |
| 949 | case PSEV_REM_REN: |
| 950 | if (cs->debug & L1_DEB_HSCX) |
| 951 | debugl1(cs, "pump stev REMOTE RENEGOTIATE"); |
| 952 | break; |
| 953 | case PSEV_GSTN_CLR: |
| 954 | if (cs->debug & L1_DEB_HSCX) |
| 955 | debugl1(cs, "pump stev GSTN CLEAR", devt); |
| 956 | break; |
| 957 | default: |
| 958 | if (cs->debug & L1_DEB_HSCX) |
| 959 | debugl1(cs, "unknown pump stev %x", devt); |
| 960 | break; |
| 961 | } |
| 962 | } |
| 963 | |
| 964 | static void |
| 965 | ll_deliver_faxstat(struct BCState *bcs, u_char status) |
| 966 | { |
| 967 | isdn_ctrl ic; |
| 968 | struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata; |
| 969 | |
| 970 | if (bcs->cs->debug & L1_DEB_HSCX) |
| 971 | debugl1(bcs->cs, "HL->LL FAXIND %x", status); |
| 972 | ic.driver = bcs->cs->myid; |
| 973 | ic.command = ISDN_STAT_FAXIND; |
| 974 | ic.arg = chanp->chan; |
| 975 | ic.parm.aux.cmd = status; |
| 976 | bcs->cs->iif.statcallb(&ic); |
| 977 | } |
| 978 | |
| 979 | static void |
| 980 | isar_pump_statev_fax(struct BCState *bcs, u_char devt) { |
| 981 | struct IsdnCardState *cs = bcs->cs; |
| 982 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 983 | u_char p1; |
| 984 | |
| 985 | switch(devt) { |
| 986 | case PSEV_10MS_TIMER: |
| 987 | if (cs->debug & L1_DEB_HSCX) |
| 988 | debugl1(cs, "pump stev TIMER"); |
| 989 | break; |
| 990 | case PSEV_RSP_READY: |
| 991 | if (cs->debug & L1_DEB_HSCX) |
| 992 | debugl1(cs, "pump stev RSP_READY"); |
| 993 | bcs->hw.isar.state = STFAX_READY; |
| 994 | l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL); |
| 995 | if (test_bit(BC_FLG_ORIG, &bcs->Flag)) { |
| 996 | isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3); |
| 997 | } else { |
| 998 | isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3); |
| 999 | } |
| 1000 | break; |
| 1001 | case PSEV_LINE_TX_H: |
| 1002 | if (bcs->hw.isar.state == STFAX_LINE) { |
| 1003 | if (cs->debug & L1_DEB_HSCX) |
| 1004 | debugl1(cs, "pump stev LINE_TX_H"); |
| 1005 | bcs->hw.isar.state = STFAX_CONT; |
| 1006 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); |
| 1007 | } else { |
| 1008 | if (cs->debug & L1_DEB_WARN) |
| 1009 | debugl1(cs, "pump stev LINE_TX_H wrong st %x", |
| 1010 | bcs->hw.isar.state); |
| 1011 | } |
| 1012 | break; |
| 1013 | case PSEV_LINE_RX_H: |
| 1014 | if (bcs->hw.isar.state == STFAX_LINE) { |
| 1015 | if (cs->debug & L1_DEB_HSCX) |
| 1016 | debugl1(cs, "pump stev LINE_RX_H"); |
| 1017 | bcs->hw.isar.state = STFAX_CONT; |
| 1018 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); |
| 1019 | } else { |
| 1020 | if (cs->debug & L1_DEB_WARN) |
| 1021 | debugl1(cs, "pump stev LINE_RX_H wrong st %x", |
| 1022 | bcs->hw.isar.state); |
| 1023 | } |
| 1024 | break; |
| 1025 | case PSEV_LINE_TX_B: |
| 1026 | if (bcs->hw.isar.state == STFAX_LINE) { |
| 1027 | if (cs->debug & L1_DEB_HSCX) |
| 1028 | debugl1(cs, "pump stev LINE_TX_B"); |
| 1029 | bcs->hw.isar.state = STFAX_CONT; |
| 1030 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); |
| 1031 | } else { |
| 1032 | if (cs->debug & L1_DEB_WARN) |
| 1033 | debugl1(cs, "pump stev LINE_TX_B wrong st %x", |
| 1034 | bcs->hw.isar.state); |
| 1035 | } |
| 1036 | break; |
| 1037 | case PSEV_LINE_RX_B: |
| 1038 | if (bcs->hw.isar.state == STFAX_LINE) { |
| 1039 | if (cs->debug & L1_DEB_HSCX) |
| 1040 | debugl1(cs, "pump stev LINE_RX_B"); |
| 1041 | bcs->hw.isar.state = STFAX_CONT; |
| 1042 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); |
| 1043 | } else { |
| 1044 | if (cs->debug & L1_DEB_WARN) |
| 1045 | debugl1(cs, "pump stev LINE_RX_B wrong st %x", |
| 1046 | bcs->hw.isar.state); |
| 1047 | } |
| 1048 | break; |
| 1049 | case PSEV_RSP_CONN: |
| 1050 | if (bcs->hw.isar.state == STFAX_CONT) { |
| 1051 | if (cs->debug & L1_DEB_HSCX) |
| 1052 | debugl1(cs, "pump stev RSP_CONN"); |
| 1053 | bcs->hw.isar.state = STFAX_ACTIV; |
| 1054 | test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags); |
| 1055 | sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); |
| 1056 | if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) { |
| 1057 | /* 1s Flags before data */ |
| 1058 | if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) |
| 1059 | del_timer(&bcs->hw.isar.ftimer); |
| 1060 | /* 1000 ms */ |
| 1061 | bcs->hw.isar.ftimer.expires = |
| 1062 | jiffies + ((1000 * HZ)/1000); |
| 1063 | test_and_set_bit(BC_FLG_LL_CONN, |
| 1064 | &bcs->Flag); |
| 1065 | add_timer(&bcs->hw.isar.ftimer); |
| 1066 | } else { |
| 1067 | schedule_event(bcs, B_LL_CONNECT); |
| 1068 | } |
| 1069 | } else { |
| 1070 | if (cs->debug & L1_DEB_WARN) |
| 1071 | debugl1(cs, "pump stev RSP_CONN wrong st %x", |
| 1072 | bcs->hw.isar.state); |
| 1073 | } |
| 1074 | break; |
| 1075 | case PSEV_FLAGS_DET: |
| 1076 | if (cs->debug & L1_DEB_HSCX) |
| 1077 | debugl1(cs, "pump stev FLAGS_DET"); |
| 1078 | break; |
| 1079 | case PSEV_RSP_DISC: |
| 1080 | if (cs->debug & L1_DEB_HSCX) |
| 1081 | debugl1(cs, "pump stev RSP_DISC"); |
| 1082 | if (bcs->hw.isar.state == STFAX_ESCAPE) { |
| 1083 | p1 = 5; |
| 1084 | switch(bcs->hw.isar.newcmd) { |
| 1085 | case 0: |
| 1086 | bcs->hw.isar.state = STFAX_READY; |
| 1087 | break; |
| 1088 | case PCTRL_CMD_FTM: |
| 1089 | p1 = 2; |
| 1090 | case PCTRL_CMD_FTH: |
| 1091 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, |
| 1092 | PCTRL_CMD_SILON, 1, &p1); |
| 1093 | bcs->hw.isar.state = STFAX_SILDET; |
| 1094 | break; |
| 1095 | case PCTRL_CMD_FRM: |
| 1096 | if (frm_extra_delay) |
| 1097 | mdelay(frm_extra_delay); |
| 1098 | case PCTRL_CMD_FRH: |
| 1099 | p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod; |
| 1100 | bcs->hw.isar.newmod = 0; |
| 1101 | bcs->hw.isar.cmd = bcs->hw.isar.newcmd; |
| 1102 | bcs->hw.isar.newcmd = 0; |
| 1103 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, |
| 1104 | bcs->hw.isar.cmd, 1, &p1); |
| 1105 | bcs->hw.isar.state = STFAX_LINE; |
| 1106 | bcs->hw.isar.try_mod = 3; |
| 1107 | break; |
| 1108 | default: |
| 1109 | if (cs->debug & L1_DEB_HSCX) |
| 1110 | debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd); |
| 1111 | break; |
| 1112 | } |
| 1113 | } else if (bcs->hw.isar.state == STFAX_ACTIV) { |
| 1114 | if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) { |
| 1115 | schedule_event(bcs, B_LL_OK); |
| 1116 | } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) { |
| 1117 | send_DLE_ETX(bcs); |
| 1118 | schedule_event(bcs, B_LL_NOCARRIER); |
| 1119 | } else { |
| 1120 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR); |
| 1121 | } |
| 1122 | bcs->hw.isar.state = STFAX_READY; |
| 1123 | } else { |
| 1124 | bcs->hw.isar.state = STFAX_READY; |
| 1125 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR); |
| 1126 | } |
| 1127 | break; |
| 1128 | case PSEV_RSP_SILDET: |
| 1129 | if (cs->debug & L1_DEB_HSCX) |
| 1130 | debugl1(cs, "pump stev RSP_SILDET"); |
| 1131 | if (bcs->hw.isar.state == STFAX_SILDET) { |
| 1132 | p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod; |
| 1133 | bcs->hw.isar.newmod = 0; |
| 1134 | bcs->hw.isar.cmd = bcs->hw.isar.newcmd; |
| 1135 | bcs->hw.isar.newcmd = 0; |
| 1136 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, |
| 1137 | bcs->hw.isar.cmd, 1, &p1); |
| 1138 | bcs->hw.isar.state = STFAX_LINE; |
| 1139 | bcs->hw.isar.try_mod = 3; |
| 1140 | } |
| 1141 | break; |
| 1142 | case PSEV_RSP_SILOFF: |
| 1143 | if (cs->debug & L1_DEB_HSCX) |
| 1144 | debugl1(cs, "pump stev RSP_SILOFF"); |
| 1145 | break; |
| 1146 | case PSEV_RSP_FCERR: |
| 1147 | if (bcs->hw.isar.state == STFAX_LINE) { |
| 1148 | if (cs->debug & L1_DEB_HSCX) |
| 1149 | debugl1(cs, "pump stev RSP_FCERR try %d", |
| 1150 | bcs->hw.isar.try_mod); |
| 1151 | if (bcs->hw.isar.try_mod--) { |
| 1152 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, |
| 1153 | bcs->hw.isar.cmd, 1, |
| 1154 | &bcs->hw.isar.mod); |
| 1155 | break; |
| 1156 | } |
| 1157 | } |
| 1158 | if (cs->debug & L1_DEB_HSCX) |
| 1159 | debugl1(cs, "pump stev RSP_FCERR"); |
| 1160 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 1161 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL); |
| 1162 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR); |
| 1163 | break; |
| 1164 | default: |
| 1165 | break; |
| 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | static char debbuf[128]; |
| 1170 | |
| 1171 | void |
| 1172 | isar_int_main(struct IsdnCardState *cs) |
| 1173 | { |
| 1174 | struct isar_reg *ireg = cs->bcs[0].hw.isar.reg; |
| 1175 | struct BCState *bcs; |
| 1176 | |
| 1177 | get_irq_infos(cs, ireg); |
| 1178 | switch (ireg->iis & ISAR_IIS_MSCMSD) { |
| 1179 | case ISAR_IIS_RDATA: |
| 1180 | if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { |
| 1181 | isar_rcv_frame(cs, bcs); |
| 1182 | } else { |
| 1183 | debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x", |
| 1184 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 1185 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 1186 | } |
| 1187 | break; |
| 1188 | case ISAR_IIS_GSTEV: |
| 1189 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 1190 | ireg->bstat |= ireg->cmsb; |
| 1191 | check_send(cs, ireg->cmsb); |
| 1192 | break; |
| 1193 | case ISAR_IIS_BSTEV: |
| 1194 | #ifdef ERROR_STATISTIC |
| 1195 | if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { |
| 1196 | if (ireg->cmsb == BSTEV_TBO) |
| 1197 | bcs->err_tx++; |
| 1198 | if (ireg->cmsb == BSTEV_RBO) |
| 1199 | bcs->err_rdo++; |
| 1200 | } |
| 1201 | #endif |
| 1202 | if (cs->debug & L1_DEB_WARN) |
| 1203 | debugl1(cs, "Buffer STEV dpath%d msb(%x)", |
| 1204 | ireg->iis>>6, ireg->cmsb); |
| 1205 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 1206 | break; |
| 1207 | case ISAR_IIS_PSTEV: |
| 1208 | if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { |
| 1209 | rcv_mbox(cs, ireg, (u_char *)ireg->par); |
| 1210 | if (bcs->mode == L1_MODE_V32) { |
| 1211 | isar_pump_statev_modem(bcs, ireg->cmsb); |
| 1212 | } else if (bcs->mode == L1_MODE_FAX) { |
| 1213 | isar_pump_statev_fax(bcs, ireg->cmsb); |
| 1214 | } else if (ireg->cmsb == PSEV_10MS_TIMER) { |
| 1215 | if (cs->debug & L1_DEB_HSCX) |
| 1216 | debugl1(cs, "pump stev TIMER"); |
| 1217 | } else { |
| 1218 | if (cs->debug & L1_DEB_WARN) |
| 1219 | debugl1(cs, "isar IIS_PSTEV pmode %d stat %x", |
| 1220 | bcs->mode, ireg->cmsb); |
| 1221 | } |
| 1222 | } else { |
| 1223 | debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x", |
| 1224 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 1225 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 1226 | } |
| 1227 | break; |
| 1228 | case ISAR_IIS_PSTRSP: |
| 1229 | if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { |
| 1230 | rcv_mbox(cs, ireg, (u_char *)ireg->par); |
| 1231 | isar_pump_status_rsp(bcs, ireg); |
| 1232 | } else { |
| 1233 | debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x", |
| 1234 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 1235 | cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); |
| 1236 | } |
| 1237 | break; |
| 1238 | case ISAR_IIS_DIAG: |
| 1239 | case ISAR_IIS_BSTRSP: |
| 1240 | case ISAR_IIS_IOM2RSP: |
| 1241 | rcv_mbox(cs, ireg, (u_char *)ireg->par); |
| 1242 | if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO)) |
| 1243 | == L1_DEB_HSCX) { |
| 1244 | u_char *tp=debbuf; |
| 1245 | |
| 1246 | tp += sprintf(debbuf, "msg iis(%x) msb(%x)", |
| 1247 | ireg->iis, ireg->cmsb); |
| 1248 | QuickHex(tp, (u_char *)ireg->par, ireg->clsb); |
| 1249 | debugl1(cs, debbuf); |
| 1250 | } |
| 1251 | break; |
| 1252 | case ISAR_IIS_INVMSG: |
| 1253 | rcv_mbox(cs, ireg, debbuf); |
| 1254 | if (cs->debug & L1_DEB_WARN) |
| 1255 | debugl1(cs, "invalid msg his:%x", |
| 1256 | ireg->cmsb); |
| 1257 | break; |
| 1258 | default: |
| 1259 | rcv_mbox(cs, ireg, debbuf); |
| 1260 | if (cs->debug & L1_DEB_WARN) |
| 1261 | debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)", |
| 1262 | ireg->iis, ireg->cmsb, ireg->clsb); |
| 1263 | break; |
| 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | static void |
| 1268 | ftimer_handler(struct BCState *bcs) { |
| 1269 | if (bcs->cs->debug) |
| 1270 | debugl1(bcs->cs, "ftimer flags %04x", |
| 1271 | bcs->Flag); |
| 1272 | test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag); |
| 1273 | if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) { |
| 1274 | schedule_event(bcs, B_LL_CONNECT); |
| 1275 | } |
| 1276 | if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) { |
| 1277 | schedule_event(bcs, B_LL_OK); |
| 1278 | } |
| 1279 | } |
| 1280 | |
| 1281 | static void |
| 1282 | setup_pump(struct BCState *bcs) { |
| 1283 | struct IsdnCardState *cs = bcs->cs; |
| 1284 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 1285 | u_char ctrl, param[6]; |
| 1286 | |
| 1287 | switch (bcs->mode) { |
| 1288 | case L1_MODE_NULL: |
| 1289 | case L1_MODE_TRANS: |
| 1290 | case L1_MODE_HDLC: |
| 1291 | sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL); |
| 1292 | break; |
| 1293 | case L1_MODE_V32: |
| 1294 | ctrl = PMOD_DATAMODEM; |
| 1295 | if (test_bit(BC_FLG_ORIG, &bcs->Flag)) { |
| 1296 | ctrl |= PCTRL_ORIG; |
| 1297 | param[5] = PV32P6_CTN; |
| 1298 | } else { |
| 1299 | param[5] = PV32P6_ATN; |
| 1300 | } |
| 1301 | param[0] = para_TOA; /* 6 db */ |
| 1302 | param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B | |
| 1303 | PV32P2_V22C | PV32P2_V21 | PV32P2_BEL; |
| 1304 | param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B; |
| 1305 | param[3] = PV32P4_UT144; |
| 1306 | param[4] = PV32P5_UT144; |
| 1307 | sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param); |
| 1308 | break; |
| 1309 | case L1_MODE_FAX: |
| 1310 | ctrl = PMOD_FAX; |
| 1311 | if (test_bit(BC_FLG_ORIG, &bcs->Flag)) { |
| 1312 | ctrl |= PCTRL_ORIG; |
| 1313 | param[1] = PFAXP2_CTN; |
| 1314 | } else { |
| 1315 | param[1] = PFAXP2_ATN; |
| 1316 | } |
| 1317 | param[0] = para_TOA; /* 6 db */ |
| 1318 | sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param); |
| 1319 | bcs->hw.isar.state = STFAX_NULL; |
| 1320 | bcs->hw.isar.newcmd = 0; |
| 1321 | bcs->hw.isar.newmod = 0; |
| 1322 | test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag); |
| 1323 | break; |
| 1324 | } |
| 1325 | udelay(1000); |
| 1326 | sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); |
| 1327 | udelay(1000); |
| 1328 | } |
| 1329 | |
| 1330 | static void |
| 1331 | setup_sart(struct BCState *bcs) { |
| 1332 | struct IsdnCardState *cs = bcs->cs; |
| 1333 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 1334 | u_char ctrl, param[2]; |
| 1335 | |
| 1336 | switch (bcs->mode) { |
| 1337 | case L1_MODE_NULL: |
| 1338 | sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0, |
| 1339 | NULL); |
| 1340 | break; |
| 1341 | case L1_MODE_TRANS: |
| 1342 | sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2, |
| 1343 | "\0\0"); |
| 1344 | break; |
| 1345 | case L1_MODE_HDLC: |
| 1346 | param[0] = 0; |
| 1347 | sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1, |
| 1348 | param); |
| 1349 | break; |
| 1350 | case L1_MODE_V32: |
| 1351 | ctrl = SMODE_V14 | SCTRL_HDMC_BOTH; |
| 1352 | param[0] = S_P1_CHS_8; |
| 1353 | param[1] = S_P2_BFT_DEF; |
| 1354 | sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2, |
| 1355 | param); |
| 1356 | break; |
| 1357 | case L1_MODE_FAX: |
| 1358 | /* SART must not configured with FAX */ |
| 1359 | break; |
| 1360 | } |
| 1361 | udelay(1000); |
| 1362 | sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL); |
| 1363 | udelay(1000); |
| 1364 | } |
| 1365 | |
| 1366 | static void |
| 1367 | setup_iom2(struct BCState *bcs) { |
| 1368 | struct IsdnCardState *cs = bcs->cs; |
| 1369 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 1370 | u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0}; |
| 1371 | |
| 1372 | if (bcs->channel) |
| 1373 | msg[1] = msg[3] = 1; |
| 1374 | switch (bcs->mode) { |
| 1375 | case L1_MODE_NULL: |
| 1376 | cmsb = 0; |
| 1377 | /* dummy slot */ |
| 1378 | msg[1] = msg[3] = bcs->hw.isar.dpath + 2; |
| 1379 | break; |
| 1380 | case L1_MODE_TRANS: |
| 1381 | case L1_MODE_HDLC: |
| 1382 | break; |
| 1383 | case L1_MODE_V32: |
| 1384 | case L1_MODE_FAX: |
| 1385 | cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV; |
| 1386 | break; |
| 1387 | } |
| 1388 | sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg); |
| 1389 | udelay(1000); |
| 1390 | sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL); |
| 1391 | udelay(1000); |
| 1392 | } |
| 1393 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1394 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1395 | modeisar(struct BCState *bcs, int mode, int bc) |
| 1396 | { |
| 1397 | struct IsdnCardState *cs = bcs->cs; |
| 1398 | |
| 1399 | /* Here we are selecting the best datapath for requested mode */ |
| 1400 | if(bcs->mode == L1_MODE_NULL) { /* New Setup */ |
| 1401 | bcs->channel = bc; |
| 1402 | switch (mode) { |
| 1403 | case L1_MODE_NULL: /* init */ |
| 1404 | if (!bcs->hw.isar.dpath) |
| 1405 | /* no init for dpath 0 */ |
| 1406 | return(0); |
| 1407 | break; |
| 1408 | case L1_MODE_TRANS: |
| 1409 | case L1_MODE_HDLC: |
| 1410 | /* best is datapath 2 */ |
| 1411 | if (!test_and_set_bit(ISAR_DP2_USE, |
| 1412 | &bcs->hw.isar.reg->Flags)) |
| 1413 | bcs->hw.isar.dpath = 2; |
| 1414 | else if (!test_and_set_bit(ISAR_DP1_USE, |
| 1415 | &bcs->hw.isar.reg->Flags)) |
| 1416 | bcs->hw.isar.dpath = 1; |
| 1417 | else { |
| 1418 | printk(KERN_WARNING"isar modeisar both pathes in use\n"); |
| 1419 | return(1); |
| 1420 | } |
| 1421 | break; |
| 1422 | case L1_MODE_V32: |
| 1423 | case L1_MODE_FAX: |
| 1424 | /* only datapath 1 */ |
| 1425 | if (!test_and_set_bit(ISAR_DP1_USE, |
| 1426 | &bcs->hw.isar.reg->Flags)) |
| 1427 | bcs->hw.isar.dpath = 1; |
| 1428 | else { |
| 1429 | printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n"); |
| 1430 | debugl1(cs, "isar modeisar analog funktions only with DP1"); |
| 1431 | return(1); |
| 1432 | } |
| 1433 | break; |
| 1434 | } |
| 1435 | } |
| 1436 | if (cs->debug & L1_DEB_HSCX) |
| 1437 | debugl1(cs, "isar dp%d mode %d->%d ichan %d", |
| 1438 | bcs->hw.isar.dpath, bcs->mode, mode, bc); |
| 1439 | bcs->mode = mode; |
| 1440 | setup_pump(bcs); |
| 1441 | setup_iom2(bcs); |
| 1442 | setup_sart(bcs); |
| 1443 | if (bcs->mode == L1_MODE_NULL) { |
| 1444 | /* Clear resources */ |
| 1445 | if (bcs->hw.isar.dpath == 1) |
| 1446 | test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags); |
| 1447 | else if (bcs->hw.isar.dpath == 2) |
| 1448 | test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags); |
| 1449 | bcs->hw.isar.dpath = 0; |
| 1450 | } |
| 1451 | return(0); |
| 1452 | } |
| 1453 | |
| 1454 | static void |
| 1455 | isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para) |
| 1456 | { |
| 1457 | struct IsdnCardState *cs = bcs->cs; |
| 1458 | u_char dps = SET_DPS(bcs->hw.isar.dpath); |
| 1459 | u_char ctrl = 0, nom = 0, p1 = 0; |
| 1460 | |
| 1461 | switch(cmd) { |
| 1462 | case ISDN_FAX_CLASS1_FTM: |
| 1463 | test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag); |
| 1464 | if (bcs->hw.isar.state == STFAX_READY) { |
| 1465 | p1 = para; |
| 1466 | ctrl = PCTRL_CMD_FTM; |
| 1467 | nom = 1; |
| 1468 | bcs->hw.isar.state = STFAX_LINE; |
| 1469 | bcs->hw.isar.cmd = ctrl; |
| 1470 | bcs->hw.isar.mod = para; |
| 1471 | bcs->hw.isar.newmod = 0; |
| 1472 | bcs->hw.isar.newcmd = 0; |
| 1473 | bcs->hw.isar.try_mod = 3; |
| 1474 | } else if ((bcs->hw.isar.state == STFAX_ACTIV) && |
| 1475 | (bcs->hw.isar.cmd == PCTRL_CMD_FTM) && |
| 1476 | (bcs->hw.isar.mod == para)) { |
| 1477 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT); |
| 1478 | } else { |
| 1479 | bcs->hw.isar.newmod = para; |
| 1480 | bcs->hw.isar.newcmd = PCTRL_CMD_FTM; |
| 1481 | nom = 0; |
| 1482 | ctrl = PCTRL_CMD_ESC; |
| 1483 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 1484 | } |
| 1485 | break; |
| 1486 | case ISDN_FAX_CLASS1_FTH: |
| 1487 | test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag); |
| 1488 | if (bcs->hw.isar.state == STFAX_READY) { |
| 1489 | p1 = para; |
| 1490 | ctrl = PCTRL_CMD_FTH; |
| 1491 | nom = 1; |
| 1492 | bcs->hw.isar.state = STFAX_LINE; |
| 1493 | bcs->hw.isar.cmd = ctrl; |
| 1494 | bcs->hw.isar.mod = para; |
| 1495 | bcs->hw.isar.newmod = 0; |
| 1496 | bcs->hw.isar.newcmd = 0; |
| 1497 | bcs->hw.isar.try_mod = 3; |
| 1498 | } else if ((bcs->hw.isar.state == STFAX_ACTIV) && |
| 1499 | (bcs->hw.isar.cmd == PCTRL_CMD_FTH) && |
| 1500 | (bcs->hw.isar.mod == para)) { |
| 1501 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT); |
| 1502 | } else { |
| 1503 | bcs->hw.isar.newmod = para; |
| 1504 | bcs->hw.isar.newcmd = PCTRL_CMD_FTH; |
| 1505 | nom = 0; |
| 1506 | ctrl = PCTRL_CMD_ESC; |
| 1507 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 1508 | } |
| 1509 | break; |
| 1510 | case ISDN_FAX_CLASS1_FRM: |
| 1511 | test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag); |
| 1512 | if (bcs->hw.isar.state == STFAX_READY) { |
| 1513 | p1 = para; |
| 1514 | ctrl = PCTRL_CMD_FRM; |
| 1515 | nom = 1; |
| 1516 | bcs->hw.isar.state = STFAX_LINE; |
| 1517 | bcs->hw.isar.cmd = ctrl; |
| 1518 | bcs->hw.isar.mod = para; |
| 1519 | bcs->hw.isar.newmod = 0; |
| 1520 | bcs->hw.isar.newcmd = 0; |
| 1521 | bcs->hw.isar.try_mod = 3; |
| 1522 | } else if ((bcs->hw.isar.state == STFAX_ACTIV) && |
| 1523 | (bcs->hw.isar.cmd == PCTRL_CMD_FRM) && |
| 1524 | (bcs->hw.isar.mod == para)) { |
| 1525 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT); |
| 1526 | } else { |
| 1527 | bcs->hw.isar.newmod = para; |
| 1528 | bcs->hw.isar.newcmd = PCTRL_CMD_FRM; |
| 1529 | nom = 0; |
| 1530 | ctrl = PCTRL_CMD_ESC; |
| 1531 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 1532 | } |
| 1533 | break; |
| 1534 | case ISDN_FAX_CLASS1_FRH: |
| 1535 | test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag); |
| 1536 | if (bcs->hw.isar.state == STFAX_READY) { |
| 1537 | p1 = para; |
| 1538 | ctrl = PCTRL_CMD_FRH; |
| 1539 | nom = 1; |
| 1540 | bcs->hw.isar.state = STFAX_LINE; |
| 1541 | bcs->hw.isar.cmd = ctrl; |
| 1542 | bcs->hw.isar.mod = para; |
| 1543 | bcs->hw.isar.newmod = 0; |
| 1544 | bcs->hw.isar.newcmd = 0; |
| 1545 | bcs->hw.isar.try_mod = 3; |
| 1546 | } else if ((bcs->hw.isar.state == STFAX_ACTIV) && |
| 1547 | (bcs->hw.isar.cmd == PCTRL_CMD_FRH) && |
| 1548 | (bcs->hw.isar.mod == para)) { |
| 1549 | ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT); |
| 1550 | } else { |
| 1551 | bcs->hw.isar.newmod = para; |
| 1552 | bcs->hw.isar.newcmd = PCTRL_CMD_FRH; |
| 1553 | nom = 0; |
| 1554 | ctrl = PCTRL_CMD_ESC; |
| 1555 | bcs->hw.isar.state = STFAX_ESCAPE; |
| 1556 | } |
| 1557 | break; |
| 1558 | case ISDN_FAXPUMP_HALT: |
| 1559 | bcs->hw.isar.state = STFAX_NULL; |
| 1560 | nom = 0; |
| 1561 | ctrl = PCTRL_CMD_HALT; |
| 1562 | break; |
| 1563 | } |
| 1564 | if (ctrl) |
| 1565 | sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1); |
| 1566 | } |
| 1567 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1568 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1569 | isar_setup(struct IsdnCardState *cs) |
| 1570 | { |
| 1571 | u_char msg; |
| 1572 | int i; |
| 1573 | |
| 1574 | /* Dpath 1, 2 */ |
| 1575 | msg = 61; |
| 1576 | for (i=0; i<2; i++) { |
| 1577 | /* Buffer Config */ |
| 1578 | sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) | |
| 1579 | ISAR_HIS_P12CFG, 4, 1, &msg); |
| 1580 | cs->bcs[i].hw.isar.mml = msg; |
| 1581 | cs->bcs[i].mode = 0; |
| 1582 | cs->bcs[i].hw.isar.dpath = i + 1; |
| 1583 | modeisar(&cs->bcs[i], 0, 0); |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 1584 | INIT_WORK(&cs->bcs[i].tqueue, isar_bh); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1585 | } |
| 1586 | } |
| 1587 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1588 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | isar_l2l1(struct PStack *st, int pr, void *arg) |
| 1590 | { |
| 1591 | struct BCState *bcs = st->l1.bcs; |
| 1592 | struct sk_buff *skb = arg; |
| 1593 | int ret; |
| 1594 | u_long flags; |
| 1595 | |
| 1596 | switch (pr) { |
| 1597 | case (PH_DATA | REQUEST): |
| 1598 | spin_lock_irqsave(&bcs->cs->lock, flags); |
| 1599 | if (bcs->tx_skb) { |
| 1600 | skb_queue_tail(&bcs->squeue, skb); |
| 1601 | } else { |
| 1602 | bcs->tx_skb = skb; |
| 1603 | test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); |
| 1604 | if (bcs->cs->debug & L1_DEB_HSCX) |
| 1605 | debugl1(bcs->cs, "DRQ set BC_FLG_BUSY"); |
| 1606 | bcs->hw.isar.txcnt = 0; |
| 1607 | bcs->cs->BC_Send_Data(bcs); |
| 1608 | } |
| 1609 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1610 | break; |
| 1611 | case (PH_PULL | INDICATION): |
| 1612 | spin_lock_irqsave(&bcs->cs->lock, flags); |
| 1613 | if (bcs->tx_skb) { |
| 1614 | printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n"); |
| 1615 | } else { |
| 1616 | test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); |
| 1617 | if (bcs->cs->debug & L1_DEB_HSCX) |
| 1618 | debugl1(bcs->cs, "PUI set BC_FLG_BUSY"); |
| 1619 | bcs->tx_skb = skb; |
| 1620 | bcs->hw.isar.txcnt = 0; |
| 1621 | bcs->cs->BC_Send_Data(bcs); |
| 1622 | } |
| 1623 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1624 | break; |
| 1625 | case (PH_PULL | REQUEST): |
| 1626 | if (!bcs->tx_skb) { |
| 1627 | test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); |
| 1628 | st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); |
| 1629 | } else |
| 1630 | test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); |
| 1631 | break; |
| 1632 | case (PH_ACTIVATE | REQUEST): |
| 1633 | spin_lock_irqsave(&bcs->cs->lock, flags); |
| 1634 | test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag); |
| 1635 | bcs->hw.isar.conmsg[0] = 0; |
| 1636 | if (test_bit(FLG_ORIG, &st->l2.flag)) |
| 1637 | test_and_set_bit(BC_FLG_ORIG, &bcs->Flag); |
| 1638 | else |
| 1639 | test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag); |
| 1640 | switch(st->l1.mode) { |
| 1641 | case L1_MODE_TRANS: |
| 1642 | case L1_MODE_HDLC: |
| 1643 | ret = modeisar(bcs, st->l1.mode, st->l1.bc); |
| 1644 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1645 | if (ret) |
| 1646 | l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg); |
| 1647 | else |
| 1648 | l1_msg_b(st, PH_ACTIVATE | REQUEST, arg); |
| 1649 | break; |
| 1650 | case L1_MODE_V32: |
| 1651 | case L1_MODE_FAX: |
| 1652 | ret = modeisar(bcs, st->l1.mode, st->l1.bc); |
| 1653 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1654 | if (ret) |
| 1655 | l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg); |
| 1656 | break; |
| 1657 | default: |
| 1658 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1659 | break; |
| 1660 | } |
| 1661 | break; |
| 1662 | case (PH_DEACTIVATE | REQUEST): |
| 1663 | l1_msg_b(st, pr, arg); |
| 1664 | break; |
| 1665 | case (PH_DEACTIVATE | CONFIRM): |
| 1666 | spin_lock_irqsave(&bcs->cs->lock, flags); |
| 1667 | switch(st->l1.mode) { |
| 1668 | case L1_MODE_TRANS: |
| 1669 | case L1_MODE_HDLC: |
| 1670 | case L1_MODE_V32: |
| 1671 | break; |
| 1672 | case L1_MODE_FAX: |
| 1673 | isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0); |
| 1674 | break; |
| 1675 | } |
| 1676 | test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag); |
| 1677 | test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); |
| 1678 | if (bcs->cs->debug & L1_DEB_HSCX) |
| 1679 | debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY"); |
| 1680 | modeisar(bcs, 0, st->l1.bc); |
| 1681 | spin_unlock_irqrestore(&bcs->cs->lock, flags); |
| 1682 | st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); |
| 1683 | break; |
| 1684 | } |
| 1685 | } |
| 1686 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1687 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1688 | close_isarstate(struct BCState *bcs) |
| 1689 | { |
| 1690 | modeisar(bcs, 0, bcs->channel); |
| 1691 | if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) { |
Jesper Juhl | 3c7208f | 2005-11-07 01:01:29 -0800 | [diff] [blame] | 1692 | kfree(bcs->hw.isar.rcvbuf); |
| 1693 | bcs->hw.isar.rcvbuf = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1694 | skb_queue_purge(&bcs->rqueue); |
| 1695 | skb_queue_purge(&bcs->squeue); |
| 1696 | if (bcs->tx_skb) { |
| 1697 | dev_kfree_skb_any(bcs->tx_skb); |
| 1698 | bcs->tx_skb = NULL; |
| 1699 | test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); |
| 1700 | if (bcs->cs->debug & L1_DEB_HSCX) |
| 1701 | debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY"); |
| 1702 | } |
| 1703 | } |
| 1704 | del_timer(&bcs->hw.isar.ftimer); |
| 1705 | } |
| 1706 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1707 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1708 | open_isarstate(struct IsdnCardState *cs, struct BCState *bcs) |
| 1709 | { |
| 1710 | if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { |
| 1711 | if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { |
| 1712 | printk(KERN_WARNING |
| 1713 | "HiSax: No memory for isar.rcvbuf\n"); |
| 1714 | return (1); |
| 1715 | } |
| 1716 | skb_queue_head_init(&bcs->rqueue); |
| 1717 | skb_queue_head_init(&bcs->squeue); |
| 1718 | } |
| 1719 | bcs->tx_skb = NULL; |
| 1720 | test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); |
| 1721 | if (cs->debug & L1_DEB_HSCX) |
| 1722 | debugl1(cs, "openisar clear BC_FLG_BUSY"); |
| 1723 | bcs->event = 0; |
| 1724 | bcs->hw.isar.rcvidx = 0; |
| 1725 | bcs->tx_cnt = 0; |
| 1726 | return (0); |
| 1727 | } |
| 1728 | |
Adrian Bunk | 672c3fd | 2005-06-25 14:59:18 -0700 | [diff] [blame] | 1729 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1730 | setstack_isar(struct PStack *st, struct BCState *bcs) |
| 1731 | { |
| 1732 | bcs->channel = st->l1.bc; |
| 1733 | if (open_isarstate(st->l1.hardware, bcs)) |
| 1734 | return (-1); |
| 1735 | st->l1.bcs = bcs; |
| 1736 | st->l2.l2l1 = isar_l2l1; |
| 1737 | setstack_manager(st); |
| 1738 | bcs->st = st; |
| 1739 | setstack_l1_B(st); |
| 1740 | return (0); |
| 1741 | } |
| 1742 | |
| 1743 | int |
| 1744 | isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) { |
| 1745 | u_long adr; |
| 1746 | int features, i; |
| 1747 | struct BCState *bcs; |
| 1748 | |
| 1749 | if (cs->debug & L1_DEB_HSCX) |
| 1750 | debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg); |
| 1751 | switch (ic->command) { |
| 1752 | case (ISDN_CMD_FAXCMD): |
| 1753 | bcs = cs->channel[ic->arg].bcs; |
| 1754 | if (cs->debug & L1_DEB_HSCX) |
| 1755 | debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d", |
| 1756 | ic->parm.aux.cmd, ic->parm.aux.subcmd); |
| 1757 | switch(ic->parm.aux.cmd) { |
| 1758 | case ISDN_FAX_CLASS1_CTRL: |
| 1759 | if (ic->parm.aux.subcmd == ETX) |
| 1760 | test_and_set_bit(BC_FLG_DLEETX, |
| 1761 | &bcs->Flag); |
| 1762 | break; |
| 1763 | case ISDN_FAX_CLASS1_FTS: |
| 1764 | if (ic->parm.aux.subcmd == AT_QUERY) { |
| 1765 | ic->command = ISDN_STAT_FAXIND; |
| 1766 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK; |
| 1767 | cs->iif.statcallb(ic); |
| 1768 | return(0); |
| 1769 | } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) { |
| 1770 | strcpy(ic->parm.aux.para, "0-255"); |
| 1771 | ic->command = ISDN_STAT_FAXIND; |
| 1772 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY; |
| 1773 | cs->iif.statcallb(ic); |
| 1774 | return(0); |
| 1775 | } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) { |
| 1776 | if (cs->debug & L1_DEB_HSCX) |
| 1777 | debugl1(cs, "isar_auxcmd %s=%d", |
| 1778 | FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]); |
| 1779 | if (bcs->hw.isar.state == STFAX_READY) { |
| 1780 | if (! ic->parm.aux.para[0]) { |
| 1781 | ic->command = ISDN_STAT_FAXIND; |
| 1782 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK; |
| 1783 | cs->iif.statcallb(ic); |
| 1784 | return(0); |
| 1785 | } |
| 1786 | if (! test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) { |
| 1787 | /* n*10 ms */ |
| 1788 | bcs->hw.isar.ftimer.expires = |
| 1789 | jiffies + ((ic->parm.aux.para[0] * 10 * HZ)/1000); |
| 1790 | test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag); |
| 1791 | add_timer(&bcs->hw.isar.ftimer); |
| 1792 | return(0); |
| 1793 | } else { |
| 1794 | if (cs->debug) |
| 1795 | debugl1(cs, "isar FTS=%d and FTI busy", |
| 1796 | ic->parm.aux.para[0]); |
| 1797 | } |
| 1798 | } else { |
| 1799 | if (cs->debug) |
| 1800 | debugl1(cs, "isar FTS=%d and isar.state not ready(%x)", |
| 1801 | ic->parm.aux.para[0],bcs->hw.isar.state); |
| 1802 | } |
| 1803 | ic->command = ISDN_STAT_FAXIND; |
| 1804 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR; |
| 1805 | cs->iif.statcallb(ic); |
| 1806 | } |
| 1807 | break; |
| 1808 | case ISDN_FAX_CLASS1_FRM: |
| 1809 | case ISDN_FAX_CLASS1_FRH: |
| 1810 | case ISDN_FAX_CLASS1_FTM: |
| 1811 | case ISDN_FAX_CLASS1_FTH: |
| 1812 | if (ic->parm.aux.subcmd == AT_QUERY) { |
| 1813 | sprintf(ic->parm.aux.para, |
| 1814 | "%d", bcs->hw.isar.mod); |
| 1815 | ic->command = ISDN_STAT_FAXIND; |
| 1816 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY; |
| 1817 | cs->iif.statcallb(ic); |
| 1818 | return(0); |
| 1819 | } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) { |
| 1820 | char *p = ic->parm.aux.para; |
| 1821 | for(i=0;i<FAXMODCNT;i++) |
| 1822 | if ((1<<i) & modmask) |
| 1823 | p += sprintf(p, "%d,", faxmodulation[i]); |
| 1824 | p--; |
| 1825 | *p=0; |
| 1826 | ic->command = ISDN_STAT_FAXIND; |
| 1827 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY; |
| 1828 | cs->iif.statcallb(ic); |
| 1829 | return(0); |
| 1830 | } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) { |
| 1831 | if (cs->debug & L1_DEB_HSCX) |
| 1832 | debugl1(cs, "isar_auxcmd %s=%d", |
| 1833 | FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]); |
| 1834 | for(i=0;i<FAXMODCNT;i++) |
| 1835 | if (faxmodulation[i]==ic->parm.aux.para[0]) |
| 1836 | break; |
| 1837 | if ((i < FAXMODCNT) && ((1<<i) & modmask) && |
| 1838 | test_bit(BC_FLG_INIT, &bcs->Flag)) { |
| 1839 | isar_pump_cmd(bcs, |
| 1840 | ic->parm.aux.cmd, |
| 1841 | ic->parm.aux.para[0]); |
| 1842 | return(0); |
| 1843 | } |
| 1844 | } |
| 1845 | /* wrong modulation or not activ */ |
| 1846 | /* fall through */ |
| 1847 | default: |
| 1848 | ic->command = ISDN_STAT_FAXIND; |
| 1849 | ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR; |
| 1850 | cs->iif.statcallb(ic); |
| 1851 | } |
| 1852 | break; |
| 1853 | case (ISDN_CMD_IOCTL): |
| 1854 | switch (ic->arg) { |
| 1855 | case 9: /* load firmware */ |
| 1856 | features = ISDN_FEATURE_L2_MODEM | |
| 1857 | ISDN_FEATURE_L2_FAX | |
| 1858 | ISDN_FEATURE_L3_FCLASS1; |
| 1859 | memcpy(&adr, ic->parm.num, sizeof(ulong)); |
| 1860 | if (isar_load_firmware(cs, (u_char __user *)adr)) |
| 1861 | return(1); |
| 1862 | else |
| 1863 | ll_run(cs, features); |
| 1864 | break; |
| 1865 | case 20: |
| 1866 | features = *(unsigned int *) ic->parm.num; |
| 1867 | printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n", |
| 1868 | modmask, features); |
| 1869 | modmask = features; |
| 1870 | break; |
| 1871 | case 21: |
| 1872 | features = *(unsigned int *) ic->parm.num; |
| 1873 | printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n", |
| 1874 | frm_extra_delay, features); |
| 1875 | if (features >= 0) |
| 1876 | frm_extra_delay = features; |
| 1877 | break; |
| 1878 | case 22: |
| 1879 | features = *(unsigned int *) ic->parm.num; |
| 1880 | printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n", |
| 1881 | para_TOA, features); |
| 1882 | if (features >= 0 && features < 32) |
| 1883 | para_TOA = features; |
| 1884 | break; |
| 1885 | default: |
| 1886 | printk(KERN_DEBUG "HiSax: invalid ioctl %d\n", |
| 1887 | (int) ic->arg); |
| 1888 | return(-EINVAL); |
| 1889 | } |
| 1890 | break; |
| 1891 | default: |
| 1892 | return(-EINVAL); |
| 1893 | } |
| 1894 | return(0); |
| 1895 | } |
| 1896 | |
Sam Ravnborg | d348c2a | 2008-02-09 23:28:12 -0800 | [diff] [blame] | 1897 | void initisar(struct IsdnCardState *cs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1898 | { |
| 1899 | cs->bcs[0].BC_SetStack = setstack_isar; |
| 1900 | cs->bcs[1].BC_SetStack = setstack_isar; |
| 1901 | cs->bcs[0].BC_Close = close_isarstate; |
| 1902 | cs->bcs[1].BC_Close = close_isarstate; |
| 1903 | cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler; |
| 1904 | cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0]; |
| 1905 | init_timer(&cs->bcs[0].hw.isar.ftimer); |
| 1906 | cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler; |
| 1907 | cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1]; |
| 1908 | init_timer(&cs->bcs[1].hw.isar.ftimer); |
| 1909 | } |