Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Macintosh interrupts |
| 3 | * |
| 4 | * General design: |
| 5 | * In contrary to the Amiga and Atari platforms, the Mac hardware seems to |
| 6 | * exclusively use the autovector interrupts (the 'generic level0-level7' |
| 7 | * interrupts with exception vectors 0x19-0x1f). The following interrupt levels |
| 8 | * are used: |
| 9 | * 1 - VIA1 |
| 10 | * - slot 0: one second interrupt (CA2) |
| 11 | * - slot 1: VBlank (CA1) |
| 12 | * - slot 2: ADB data ready (SR full) |
| 13 | * - slot 3: ADB data (CB2) |
| 14 | * - slot 4: ADB clock (CB1) |
| 15 | * - slot 5: timer 2 |
| 16 | * - slot 6: timer 1 |
| 17 | * - slot 7: status of IRQ; signals 'any enabled int.' |
| 18 | * |
| 19 | * 2 - VIA2 or RBV |
| 20 | * - slot 0: SCSI DRQ (CA2) |
| 21 | * - slot 1: NUBUS IRQ (CA1) need to read port A to find which |
| 22 | * - slot 2: /EXP IRQ (only on IIci) |
| 23 | * - slot 3: SCSI IRQ (CB2) |
| 24 | * - slot 4: ASC IRQ (CB1) |
| 25 | * - slot 5: timer 2 (not on IIci) |
| 26 | * - slot 6: timer 1 (not on IIci) |
| 27 | * - slot 7: status of IRQ; signals 'any enabled int.' |
| 28 | * |
| 29 | * 2 - OSS (IIfx only?) |
| 30 | * - slot 0: SCSI interrupt |
| 31 | * - slot 1: Sound interrupt |
| 32 | * |
| 33 | * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes: |
| 34 | * |
| 35 | * 3 - unused (?) |
| 36 | * |
| 37 | * 4 - SCC (slot number determined by reading RR3 on the SSC itself) |
| 38 | * - slot 1: SCC channel A |
| 39 | * - slot 2: SCC channel B |
| 40 | * |
| 41 | * 5 - unused (?) |
| 42 | * [serial errors or special conditions seem to raise level 6 |
| 43 | * interrupts on some models (LC4xx?)] |
| 44 | * |
| 45 | * 6 - off switch (?) |
| 46 | * |
| 47 | * For OSS Macintoshes (IIfx only at this point): |
| 48 | * |
| 49 | * 3 - Nubus interrupt |
| 50 | * - slot 0: Slot $9 |
| 51 | * - slot 1: Slot $A |
| 52 | * - slot 2: Slot $B |
| 53 | * - slot 3: Slot $C |
| 54 | * - slot 4: Slot $D |
| 55 | * - slot 5: Slot $E |
| 56 | * |
| 57 | * 4 - SCC IOP |
| 58 | * - slot 1: SCC channel A |
| 59 | * - slot 2: SCC channel B |
| 60 | * |
| 61 | * 5 - ISM IOP (ADB?) |
| 62 | * |
| 63 | * 6 - unused |
| 64 | * |
| 65 | * For PSC Macintoshes (660AV, 840AV): |
| 66 | * |
| 67 | * 3 - PSC level 3 |
| 68 | * - slot 0: MACE |
| 69 | * |
| 70 | * 4 - PSC level 4 |
| 71 | * - slot 1: SCC channel A interrupt |
| 72 | * - slot 2: SCC channel B interrupt |
| 73 | * - slot 3: MACE DMA |
| 74 | * |
| 75 | * 5 - PSC level 5 |
| 76 | * |
| 77 | * 6 - PSC level 6 |
| 78 | * |
| 79 | * Finally we have good 'ole level 7, the non-maskable interrupt: |
| 80 | * |
| 81 | * 7 - NMI (programmer's switch on the back of some Macs) |
| 82 | * Also RAM parity error on models which support it (IIc, IIfx?) |
| 83 | * |
| 84 | * The current interrupt logic looks something like this: |
| 85 | * |
| 86 | * - We install dispatchers for the autovector interrupts (1-7). These |
| 87 | * dispatchers are responsible for querying the hardware (the |
| 88 | * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using |
| 89 | * this information a machspec interrupt number is generated by placing the |
| 90 | * index of the interrupt hardware into the low three bits and the original |
| 91 | * autovector interrupt number in the upper 5 bits. The handlers for the |
| 92 | * resulting machspec interrupt are then called. |
| 93 | * |
| 94 | * - Nubus is a special case because its interrupts are hidden behind two |
| 95 | * layers of hardware. Nubus interrupts come in as index 1 on VIA #2, |
| 96 | * which translates to IRQ number 17. In this spot we install _another_ |
| 97 | * dispatcher. This dispatcher finds the interrupting slot number (9-F) and |
| 98 | * then forms a new machspec interrupt number as above with the slot number |
| 99 | * minus 9 in the low three bits and the pseudo-level 7 in the upper five |
| 100 | * bits. The handlers for this new machspec interrupt number are then |
| 101 | * called. This puts Nubus interrupts into the range 56-62. |
| 102 | * |
| 103 | * - The Baboon interrupts (used on some PowerBooks) are an even more special |
| 104 | * case. They're hidden behind the Nubus slot $C interrupt thus adding a |
| 105 | * third layer of indirection. Why oh why did the Apple engineers do that? |
| 106 | * |
| 107 | * - We support "fast" and "slow" handlers, just like the Amiga port. The |
| 108 | * fast handlers are called first and with all interrupts disabled. They |
| 109 | * are expected to execute quickly (hence the name). The slow handlers are |
| 110 | * called last with interrupts enabled and the interrupt level restored. |
| 111 | * They must therefore be reentrant. |
| 112 | * |
| 113 | * TODO: |
| 114 | * |
| 115 | */ |
| 116 | |
Al Viro | 66a3f82 | 2007-07-20 04:33:28 +0100 | [diff] [blame] | 117 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | #include <linux/types.h> |
| 119 | #include <linux/kernel.h> |
| 120 | #include <linux/sched.h> |
| 121 | #include <linux/kernel_stat.h> |
| 122 | #include <linux/interrupt.h> /* for intr_count */ |
| 123 | #include <linux/delay.h> |
| 124 | #include <linux/seq_file.h> |
| 125 | |
| 126 | #include <asm/system.h> |
| 127 | #include <asm/irq.h> |
| 128 | #include <asm/traps.h> |
| 129 | #include <asm/bootinfo.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | #include <asm/macintosh.h> |
| 131 | #include <asm/mac_via.h> |
| 132 | #include <asm/mac_psc.h> |
| 133 | #include <asm/hwtest.h> |
| 134 | #include <asm/errno.h> |
| 135 | #include <asm/macints.h> |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 136 | #include <asm/irq_regs.h> |
Geert Uytterhoeven | c85627f | 2008-12-21 12:03:37 +0100 | [diff] [blame^] | 137 | #include <asm/mac_oss.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | |
| 139 | #define DEBUG_SPURIOUS |
| 140 | #define SHUTUP_SONIC |
| 141 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | /* SCC interrupt mask */ |
| 143 | |
| 144 | static int scc_mask; |
| 145 | |
| 146 | /* |
| 147 | * VIA/RBV hooks |
| 148 | */ |
| 149 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | extern void via_register_interrupts(void); |
| 151 | extern void via_irq_enable(int); |
| 152 | extern void via_irq_disable(int); |
| 153 | extern void via_irq_clear(int); |
| 154 | extern int via_irq_pending(int); |
| 155 | |
| 156 | /* |
| 157 | * OSS hooks |
| 158 | */ |
| 159 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | extern void oss_register_interrupts(void); |
| 161 | extern void oss_irq_enable(int); |
| 162 | extern void oss_irq_disable(int); |
| 163 | extern void oss_irq_clear(int); |
| 164 | extern int oss_irq_pending(int); |
| 165 | |
| 166 | /* |
| 167 | * PSC hooks |
| 168 | */ |
| 169 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | extern void psc_register_interrupts(void); |
| 171 | extern void psc_irq_enable(int); |
| 172 | extern void psc_irq_disable(int); |
| 173 | extern void psc_irq_clear(int); |
| 174 | extern int psc_irq_pending(int); |
| 175 | |
| 176 | /* |
| 177 | * IOP hooks |
| 178 | */ |
| 179 | |
| 180 | extern void iop_register_interrupts(void); |
| 181 | |
| 182 | /* |
| 183 | * Baboon hooks |
| 184 | */ |
| 185 | |
| 186 | extern int baboon_present; |
| 187 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | extern void baboon_register_interrupts(void); |
| 189 | extern void baboon_irq_enable(int); |
| 190 | extern void baboon_irq_disable(int); |
| 191 | extern void baboon_irq_clear(int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | |
| 193 | /* |
| 194 | * SCC interrupt routines |
| 195 | */ |
| 196 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 197 | static void scc_irq_enable(unsigned int); |
| 198 | static void scc_irq_disable(unsigned int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | |
| 200 | /* |
| 201 | * console_loglevel determines NMI handler function |
| 202 | */ |
| 203 | |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 204 | irqreturn_t mac_nmi_handler(int, void *); |
| 205 | irqreturn_t mac_debug_handler(int, void *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | |
| 207 | /* #define DEBUG_MACINTS */ |
| 208 | |
Finn Thain | 746e8d3 | 2008-11-18 20:45:21 +0100 | [diff] [blame] | 209 | void mac_enable_irq(unsigned int irq); |
| 210 | void mac_disable_irq(unsigned int irq); |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 211 | |
| 212 | static struct irq_controller mac_irq_controller = { |
| 213 | .name = "mac", |
Milind Arun Choudhary | 241258d | 2007-05-06 14:50:54 -0700 | [diff] [blame] | 214 | .lock = __SPIN_LOCK_UNLOCKED(mac_irq_controller.lock), |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 215 | .enable = mac_enable_irq, |
| 216 | .disable = mac_disable_irq, |
| 217 | }; |
| 218 | |
Al Viro | 66a3f82 | 2007-07-20 04:33:28 +0100 | [diff] [blame] | 219 | void __init mac_init_IRQ(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | #ifdef DEBUG_MACINTS |
| 222 | printk("mac_init_IRQ(): Setting things up...\n"); |
| 223 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | scc_mask = 0; |
| 225 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 226 | m68k_setup_irq_controller(&mac_irq_controller, IRQ_USER, |
| 227 | NUM_MAC_SOURCES - IRQ_USER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | /* Make sure the SONIC interrupt is cleared or things get ugly */ |
| 229 | #ifdef SHUTUP_SONIC |
| 230 | printk("Killing onboard sonic... "); |
| 231 | /* This address should hopefully be mapped already */ |
| 232 | if (hwreg_present((void*)(0x50f0a000))) { |
| 233 | *(long *)(0x50f0a014) = 0x7fffL; |
| 234 | *(long *)(0x50f0a010) = 0L; |
| 235 | } |
| 236 | printk("Done.\n"); |
| 237 | #endif /* SHUTUP_SONIC */ |
| 238 | |
| 239 | /* |
| 240 | * Now register the handlers for the master IRQ handlers |
| 241 | * at levels 1-7. Most of the work is done elsewhere. |
| 242 | */ |
| 243 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 244 | if (oss_present) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | oss_register_interrupts(); |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 246 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | via_register_interrupts(); |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 248 | if (psc_present) |
| 249 | psc_register_interrupts(); |
| 250 | if (baboon_present) |
| 251 | baboon_register_interrupts(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | iop_register_interrupts(); |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 253 | request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | mac_nmi_handler); |
| 255 | #ifdef DEBUG_MACINTS |
| 256 | printk("mac_init_IRQ(): Done!\n"); |
| 257 | #endif |
| 258 | } |
| 259 | |
| 260 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | * mac_enable_irq - enable an interrupt source |
| 262 | * mac_disable_irq - disable an interrupt source |
| 263 | * mac_clear_irq - clears a pending interrupt |
| 264 | * mac_pending_irq - Returns the pending status of an IRQ (nonzero = pending) |
| 265 | * |
| 266 | * These routines are just dispatchers to the VIA/OSS/PSC routines. |
| 267 | */ |
| 268 | |
Finn Thain | 746e8d3 | 2008-11-18 20:45:21 +0100 | [diff] [blame] | 269 | void mac_enable_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 271 | int irq_src = IRQ_SRC(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | |
| 273 | switch(irq_src) { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 274 | case 1: |
| 275 | via_irq_enable(irq); |
| 276 | break; |
| 277 | case 2: |
| 278 | case 7: |
| 279 | if (oss_present) |
| 280 | oss_irq_enable(irq); |
| 281 | else |
| 282 | via_irq_enable(irq); |
| 283 | break; |
| 284 | case 3: |
| 285 | case 4: |
| 286 | case 5: |
| 287 | case 6: |
| 288 | if (psc_present) |
| 289 | psc_irq_enable(irq); |
| 290 | else if (oss_present) |
| 291 | oss_irq_enable(irq); |
| 292 | else if (irq_src == 4) |
| 293 | scc_irq_enable(irq); |
| 294 | break; |
| 295 | case 8: |
| 296 | if (baboon_present) |
| 297 | baboon_irq_enable(irq); |
| 298 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | } |
| 300 | } |
| 301 | |
Finn Thain | 746e8d3 | 2008-11-18 20:45:21 +0100 | [diff] [blame] | 302 | void mac_disable_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 304 | int irq_src = IRQ_SRC(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | |
| 306 | switch(irq_src) { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 307 | case 1: |
| 308 | via_irq_disable(irq); |
| 309 | break; |
| 310 | case 2: |
| 311 | case 7: |
| 312 | if (oss_present) |
| 313 | oss_irq_disable(irq); |
| 314 | else |
| 315 | via_irq_disable(irq); |
| 316 | break; |
| 317 | case 3: |
| 318 | case 4: |
| 319 | case 5: |
| 320 | case 6: |
| 321 | if (psc_present) |
| 322 | psc_irq_disable(irq); |
| 323 | else if (oss_present) |
| 324 | oss_irq_disable(irq); |
| 325 | else if (irq_src == 4) |
| 326 | scc_irq_disable(irq); |
| 327 | break; |
| 328 | case 8: |
| 329 | if (baboon_present) |
| 330 | baboon_irq_disable(irq); |
| 331 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | } |
| 333 | } |
| 334 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 335 | void mac_clear_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | { |
| 337 | switch(IRQ_SRC(irq)) { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 338 | case 1: |
| 339 | via_irq_clear(irq); |
| 340 | break; |
| 341 | case 2: |
| 342 | case 7: |
| 343 | if (oss_present) |
| 344 | oss_irq_clear(irq); |
| 345 | else |
| 346 | via_irq_clear(irq); |
| 347 | break; |
| 348 | case 3: |
| 349 | case 4: |
| 350 | case 5: |
| 351 | case 6: |
| 352 | if (psc_present) |
| 353 | psc_irq_clear(irq); |
| 354 | else if (oss_present) |
| 355 | oss_irq_clear(irq); |
| 356 | break; |
| 357 | case 8: |
| 358 | if (baboon_present) |
| 359 | baboon_irq_clear(irq); |
| 360 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | } |
| 362 | } |
| 363 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 364 | int mac_irq_pending(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | { |
| 366 | switch(IRQ_SRC(irq)) { |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 367 | case 1: |
| 368 | return via_irq_pending(irq); |
| 369 | case 2: |
| 370 | case 7: |
| 371 | if (oss_present) |
| 372 | return oss_irq_pending(irq); |
| 373 | else |
| 374 | return via_irq_pending(irq); |
| 375 | case 3: |
| 376 | case 4: |
| 377 | case 5: |
| 378 | case 6: |
| 379 | if (psc_present) |
| 380 | return psc_irq_pending(irq); |
| 381 | else if (oss_present) |
| 382 | return oss_irq_pending(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | } |
| 384 | return 0; |
| 385 | } |
Al Viro | 66a3f82 | 2007-07-20 04:33:28 +0100 | [diff] [blame] | 386 | EXPORT_SYMBOL(mac_irq_pending); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | static int num_debug[8]; |
| 389 | |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 390 | irqreturn_t mac_debug_handler(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 391 | { |
| 392 | if (num_debug[irq] < 10) { |
| 393 | printk("DEBUG: Unexpected IRQ %d\n", irq); |
| 394 | num_debug[irq]++; |
| 395 | } |
| 396 | return IRQ_HANDLED; |
| 397 | } |
| 398 | |
| 399 | static int in_nmi; |
| 400 | static volatile int nmi_hold; |
| 401 | |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 402 | irqreturn_t mac_nmi_handler(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | { |
| 404 | int i; |
| 405 | /* |
| 406 | * generate debug output on NMI switch if 'debug' kernel option given |
| 407 | * (only works with Penguin!) |
| 408 | */ |
| 409 | |
| 410 | in_nmi++; |
| 411 | for (i=0; i<100; i++) |
| 412 | udelay(1000); |
| 413 | |
| 414 | if (in_nmi == 1) { |
| 415 | nmi_hold = 1; |
| 416 | printk("... pausing, press NMI to resume ..."); |
| 417 | } else { |
| 418 | printk(" ok!\n"); |
| 419 | nmi_hold = 0; |
| 420 | } |
| 421 | |
| 422 | barrier(); |
| 423 | |
| 424 | while (nmi_hold == 1) |
| 425 | udelay(1000); |
| 426 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 427 | if (console_loglevel >= 8) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | #if 0 |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 429 | struct pt_regs *fp = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | show_state(); |
| 431 | printk("PC: %08lx\nSR: %04x SP: %p\n", fp->pc, fp->sr, fp); |
| 432 | printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", |
| 433 | fp->d0, fp->d1, fp->d2, fp->d3); |
| 434 | printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n", |
| 435 | fp->d4, fp->d5, fp->a0, fp->a1); |
| 436 | |
| 437 | if (STACK_MAGIC != *(unsigned long *)current->kernel_stack_page) |
| 438 | printk("Corrupted stack page\n"); |
| 439 | printk("Process %s (pid: %d, stackpage=%08lx)\n", |
| 440 | current->comm, current->pid, current->kernel_stack_page); |
| 441 | if (intr_count == 1) |
| 442 | dump_stack((struct frame *)fp); |
| 443 | #else |
| 444 | /* printk("NMI "); */ |
| 445 | #endif |
| 446 | } |
| 447 | in_nmi--; |
| 448 | return IRQ_HANDLED; |
| 449 | } |
| 450 | |
| 451 | /* |
| 452 | * Simple routines for masking and unmasking |
| 453 | * SCC interrupts in cases where this can't be |
| 454 | * done in hardware (only the PSC can do that.) |
| 455 | */ |
| 456 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 457 | static void scc_irq_enable(unsigned int irq) |
| 458 | { |
| 459 | int irq_idx = IRQ_IDX(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | |
| 461 | scc_mask |= (1 << irq_idx); |
| 462 | } |
| 463 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 464 | static void scc_irq_disable(unsigned int irq) |
| 465 | { |
| 466 | int irq_idx = IRQ_IDX(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | |
| 468 | scc_mask &= ~(1 << irq_idx); |
| 469 | } |
| 470 | |
| 471 | /* |
| 472 | * SCC master interrupt handler. We have to do a bit of magic here |
| 473 | * to figure out what channel gave us the interrupt; putting this |
| 474 | * here is cleaner than hacking it into drivers/char/macserial.c. |
| 475 | */ |
| 476 | |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 477 | void mac_scc_dispatch(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | { |
| 479 | volatile unsigned char *scc = (unsigned char *) mac_bi_data.sccbase + 2; |
| 480 | unsigned char reg; |
| 481 | unsigned long flags; |
| 482 | |
| 483 | /* Read RR3 from the chip. Always do this on channel A */ |
| 484 | /* This must be an atomic operation so disable irqs. */ |
| 485 | |
| 486 | local_irq_save(flags); |
| 487 | *scc = 3; |
| 488 | reg = *scc; |
| 489 | local_irq_restore(flags); |
| 490 | |
| 491 | /* Now dispatch. Bits 0-2 are for channel B and */ |
| 492 | /* bits 3-5 are for channel A. We can safely */ |
| 493 | /* ignore the remaining bits here. */ |
| 494 | /* */ |
| 495 | /* Note that we're ignoring scc_mask for now. */ |
| 496 | /* If we actually mask the ints then we tend to */ |
| 497 | /* get hammered by very persistent SCC irqs, */ |
| 498 | /* and since they're autovector interrupts they */ |
| 499 | /* pretty much kill the system. */ |
| 500 | |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 501 | if (reg & 0x38) |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 502 | m68k_handle_int(IRQ_SCCA); |
Roman Zippel | 9c5f4af | 2006-06-25 05:47:04 -0700 | [diff] [blame] | 503 | if (reg & 0x07) |
Al Viro | 2850bc2 | 2006-10-07 14:16:45 +0100 | [diff] [blame] | 504 | m68k_handle_int(IRQ_SCCB); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | } |