Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 1 | /************************************* |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 2 | * Macros.h |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 3 | **************************************/ |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 4 | #ifndef __MACROS_H__ |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 5 | #define __MACROS_H__ |
| 6 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 7 | #define TX_TIMER_PERIOD 10 /*10 msec*/ |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 8 | #define MAX_CLASSIFIERS 100 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 9 | /* #define MAX_CLASSIFIERS_PER_SF 20 */ |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 10 | #define MAX_TARGET_DSX_BUFFERS 24 |
| 11 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 12 | #define MAX_CNTRL_PKTS 100 |
| 13 | #define MAX_DATA_PKTS 200 |
| 14 | #define MAX_ETH_SIZE 1536 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 15 | #define MAX_CNTL_PKT_SIZE 2048 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 16 | |
| 17 | #define MTU_SIZE 1400 |
Stephen Hemminger | d7affd0 | 2010-10-29 17:15:06 -0700 | [diff] [blame] | 18 | #define TX_QLEN 5 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 19 | |
| 20 | #define MAC_ADDR_REGISTER 0xbf60d000 |
| 21 | |
| 22 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 23 | /* Quality of Service */ |
| 24 | #define NO_OF_QUEUES 17 |
| 25 | #define HiPriority (NO_OF_QUEUES-1) |
| 26 | #define LowPriority 0 |
| 27 | #define BE 2 |
| 28 | #define rtPS 4 |
| 29 | #define ERTPS 5 |
| 30 | #define UGS 6 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 31 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 32 | #define BE_BUCKET_SIZE (1024*1024*100) /* 32kb */ |
| 33 | #define rtPS_BUCKET_SIZE (1024*1024*100) /* 8kb */ |
| 34 | #define MAX_ALLOWED_RATE (1024*1024*100) |
| 35 | #define TX_PACKET_THRESHOLD 10 |
| 36 | #define XSECONDS (1*HZ) |
| 37 | #define DSC_ACTIVATE_REQUEST 248 |
| 38 | #define QUEUE_DEPTH_OFFSET 0x1fc01000 |
| 39 | #define MAX_DEVICE_DESC_SIZE 2040 |
| 40 | #define MAX_CTRL_QUEUE_LEN 100 |
| 41 | #define MAX_APP_QUEUE_LEN 200 |
| 42 | #define MAX_LATENCY_ALLOWED 0xFFFFFFFF |
| 43 | #define DEFAULT_UG_INTERVAL 250 |
| 44 | #define DEFAULT_UGI_FACTOR 4 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 45 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 46 | #define DEFAULT_PERSFCOUNT 60 |
| 47 | #define MAX_CONNECTIONS 10 |
| 48 | #define MAX_CLASS_NAME_LENGTH 32 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 49 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 50 | #define ETH_LENGTH_OF_ADDRESS 6 |
| 51 | #define MAX_MULTICAST_ADDRESSES 32 |
| 52 | #define IP_LENGTH_OF_ADDRESS 4 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 53 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 54 | #define IP_PACKET_ONLY_MODE 0 |
| 55 | #define ETH_PACKET_TUNNELING_MODE 1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 56 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 57 | /* Link Request */ |
| 58 | #define SET_MAC_ADDRESS_REQUEST 0 |
| 59 | #define SYNC_UP_REQUEST 1 |
| 60 | #define SYNCED_UP 2 |
| 61 | #define LINK_UP_REQUEST 3 |
| 62 | #define LINK_CONNECTED 4 |
| 63 | #define SYNC_UP_NOTIFICATION 2 |
| 64 | #define LINK_UP_NOTIFICATION 4 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 65 | |
| 66 | |
| 67 | #define LINK_NET_ENTRY 0x0002 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 68 | #define HMC_STATUS 0x0004 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 69 | #define LINK_UP_CONTROL_REQ 0x83 |
| 70 | |
| 71 | #define STATS_POINTER_REQ_STATUS 0x86 |
| 72 | #define NETWORK_ENTRY_REQ_PAYLOAD 198 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 73 | #define LINK_DOWN_REQ_PAYLOAD 226 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 74 | #define SYNC_UP_REQ_PAYLOAD 228 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 75 | #define STATISTICS_POINTER_REQ 237 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 76 | #define LINK_UP_REQ_PAYLOAD 245 |
| 77 | #define LINK_UP_ACK 246 |
| 78 | |
| 79 | #define STATS_MSG_SIZE 4 |
| 80 | #define INDEX_TO_DATA 4 |
| 81 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 82 | #define GO_TO_IDLE_MODE_PAYLOAD 210 |
| 83 | #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 |
| 84 | #define IDLE_MODE_SF_UPDATE_MSG 187 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 85 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 86 | #define SKB_RESERVE_ETHERNET_HEADER 16 |
| 87 | #define SKB_RESERVE_PHS_BYTES 32 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 88 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 89 | #define IP_PACKET_ONLY_MODE 0 |
| 90 | #define ETH_PACKET_TUNNELING_MODE 1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 91 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 92 | #define ETH_CS_802_3 1 |
| 93 | #define ETH_CS_802_1Q_VLAN 3 |
| 94 | #define IPV4_CS 1 |
| 95 | #define IPV6_CS 2 |
| 96 | #define ETH_CS_MASK 0x3f |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 97 | |
| 98 | /** \brief Validity bit maps for TLVs in packet classification rule */ |
| 99 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 100 | #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 |
| 101 | #define PKT_CLASSIFICATION_VLANID_VALID 1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 102 | |
| 103 | #ifndef MIN |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 104 | #define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b)) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 105 | #endif |
| 106 | |
| 107 | |
| 108 | /*Leader related terms */ |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 109 | #define LEADER_STATUS 0x00 |
| 110 | #define LEADER_STATUS_TCP_ACK 0x1 |
| 111 | #define LEADER_SIZE sizeof(LEADER) |
| 112 | #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) |
| 113 | #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) |
| 114 | #define CM_REQUEST_SIZE (LEADER_SIZE + sizeof(stLocalSFChangeRequest)) |
| 115 | #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 116 | |
| 117 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 118 | #define MAX_TRANSFER_CTRL_BYTE_USB (2*1024) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 119 | |
| 120 | #define GET_MAILBOX1_REG_REQUEST 0x87 |
| 121 | #define GET_MAILBOX1_REG_RESPONSE 0x67 |
| 122 | #define VCID_CONTROL_PACKET 0x00 |
| 123 | |
| 124 | #define TRANSMIT_NETWORK_DATA 0x00 |
| 125 | #define RECEIVED_NETWORK_DATA 0x20 |
| 126 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 127 | #define CM_RESPONSES 0xA0 |
| 128 | #define STATUS_RSP 0xA1 |
| 129 | #define LINK_CONTROL_RESP 0xA2 |
| 130 | #define IDLE_MODE_STATUS 0xA3 |
| 131 | #define STATS_POINTER_RESP 0xA6 |
| 132 | #define MGMT_MSG_INFO_SW_STATUS 0xA7 |
| 133 | #define AUTH_SS_HOST_MSG 0xA8 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 134 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 135 | #define CM_DSA_ACK_PAYLOAD 247 |
| 136 | #define CM_DSC_ACK_PAYLOAD 248 |
| 137 | #define CM_DSD_ACK_PAYLOAD 249 |
| 138 | #define CM_DSDEACTVATE 250 |
| 139 | #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 140 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 141 | #define MAC_REQ 0 |
| 142 | #define LINK_RESP 1 |
| 143 | #define RSSI_INDICATION 2 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 144 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 145 | #define SS_INFO 4 |
| 146 | #define STATISTICS_INFO 5 |
| 147 | #define CM_INDICATION 6 |
| 148 | #define PARAM_RESP 7 |
| 149 | #define BUFFER_1K 1024 |
| 150 | #define BUFFER_2K (BUFFER_1K*2) |
| 151 | #define BUFFER_4K (BUFFER_2K*2) |
| 152 | #define BUFFER_8K (BUFFER_4K*2) |
| 153 | #define BUFFER_16K (BUFFER_8K*2) |
| 154 | #define DOWNLINK_DIR 0 |
| 155 | #define UPLINK_DIR 1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 156 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 157 | #define BCM_SIGNATURE "BECEEM" |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 158 | |
| 159 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 160 | #define GPIO_OUTPUT_REGISTER 0x0F00003C |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 161 | #define BCM_GPIO_OUTPUT_SET_REG 0x0F000040 |
| 162 | #define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044 |
| 163 | #define GPIO_MODE_REGISTER 0x0F000034 |
| 164 | #define GPIO_PIN_STATE_REGISTER 0x0F000038 |
| 165 | |
| 166 | |
| 167 | typedef struct _LINK_STATE { |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 168 | UCHAR ucLinkStatus; |
| 169 | UCHAR bIdleMode; |
| 170 | UCHAR bShutdownMode; |
| 171 | } LINK_STATE, *PLINK_STATE; |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 172 | |
| 173 | |
| 174 | enum enLinkStatus { |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 175 | WAIT_FOR_SYNC = 1, |
| 176 | PHY_SYNC_ACHIVED = 2, |
| 177 | LINKUP_IN_PROGRESS = 3, |
| 178 | LINKUP_DONE = 4, |
| 179 | DREG_RECEIVED = 5, |
| 180 | LINK_STATUS_RESET_RECEIVED = 6, |
| 181 | PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, |
| 182 | LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, |
| 183 | COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW = 9 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 184 | }; |
| 185 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 186 | typedef enum _E_PHS_DSC_ACTION { |
| 187 | eAddPHSRule = 0, |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 188 | eSetPHSRule, |
| 189 | eDeletePHSRule, |
| 190 | eDeleteAllPHSRules |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 191 | } E_PHS_DSC_ACTION; |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 192 | |
| 193 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 194 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 /* Host to Mac */ |
| 195 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 /* Mac to Host */ |
| 196 | #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 /* 0b000010000 */ |
| 197 | #define MINIMUM_PENDING_DESCRIPTORS 5 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 198 | |
| 199 | #define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC |
| 200 | #define SHUTDOWN_ACK_FROM_DRIVER 0x1 |
| 201 | #define SHUTDOWN_NACK_FROM_DRIVER 0x2 |
| 202 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 203 | #define LINK_SYNC_UP_SUBTYPE 0x0001 |
| 204 | #define LINK_SYNC_DOWN_SUBTYPE 0x0001 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 205 | |
| 206 | |
| 207 | |
| 208 | #define CONT_MODE 1 |
| 209 | #define SINGLE_DESCRIPTOR 1 |
| 210 | |
| 211 | |
| 212 | #define DESCRIPTOR_LENGTH 0x30 |
| 213 | #define FIRMWARE_DESCS_ADDRESS 0x1F100000 |
| 214 | |
| 215 | |
| 216 | #define CLOCK_RESET_CNTRL_REG_1 0x0F00000C |
| 217 | #define CLOCK_RESET_CNTRL_REG_2 0x0F000840 |
| 218 | |
| 219 | |
| 220 | |
| 221 | #define TX_DESCRIPTOR_HEAD_REGISTER 0x0F010034 |
| 222 | #define RX_DESCRIPTOR_HEAD_REGISTER 0x0F010094 |
| 223 | |
| 224 | #define STATISTICS_BEGIN_ADDR 0xbf60f02c |
| 225 | |
| 226 | #define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10) |
| 227 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 228 | #define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 229 | #define AUTO_LINKUP_ENABLE 0x2 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 230 | #define AUTO_SYNC_DISABLE 0x1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 231 | #define AUTO_FIRM_DOWNLOAD 0x1 |
| 232 | #define SETTLE_DOWN_TIME 50 |
| 233 | |
| 234 | #define HOST_BUS_SUSPEND_BIT 16 |
| 235 | |
| 236 | #define IDLE_MESSAGE 0x81 |
| 237 | |
| 238 | #define MIPS_CLOCK_133MHz 1 |
| 239 | |
| 240 | #define TARGET_CAN_GO_TO_IDLE_MODE 2 |
| 241 | #define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3 |
| 242 | #define IDLE_MODE_PAYLOAD_LENGTH 8 |
| 243 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 244 | #define IP_HEADER(Buffer) ((IPHeaderFormat *)(Buffer)) |
| 245 | #define IPV4 4 |
| 246 | #define IP_VERSION(byte) (((byte&0xF0)>>4)) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 247 | |
| 248 | #define SET_MAC_ADDRESS 193 |
| 249 | #define SET_MAC_ADDRESS_RESPONSE 236 |
| 250 | |
| 251 | #define IDLE_MODE_WAKEUP_PATTERN 0xd0ea1d1e |
| 252 | #define IDLE_MODE_WAKEUP_NOTIFIER_ADDRESS 0x1FC02FA8 |
| 253 | #define IDLE_MODE_MAX_RETRY_COUNT 1000 |
| 254 | |
| 255 | #ifdef REL_4_1 |
| 256 | #define CONFIG_BEGIN_ADDR 0xBF60B004 |
| 257 | #else |
| 258 | #define CONFIG_BEGIN_ADDR 0xBF60B000 |
| 259 | #endif |
| 260 | |
| 261 | #define FIRMWARE_BEGIN_ADDR 0xBFC00000 |
| 262 | |
Stephen Hemminger | 429a590 | 2010-11-01 12:27:20 -0400 | [diff] [blame] | 263 | #define INVALID_QUEUE_INDEX NO_OF_QUEUES |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 264 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 265 | #define INVALID_PID ((pid_t)-1) |
| 266 | #define DDR_80_MHZ 0 |
| 267 | #define DDR_100_MHZ 1 |
| 268 | #define DDR_120_MHZ 2 /* Additional Frequency for T3LP */ |
| 269 | #define DDR_133_MHZ 3 |
| 270 | #define DDR_140_MHZ 4 /* Not Used (Reserved for future) */ |
| 271 | #define DDR_160_MHZ 5 /* Additional Frequency for T3LP */ |
| 272 | #define DDR_180_MHZ 6 /* Not Used (Reserved for future) */ |
| 273 | #define DDR_200_MHZ 7 /* Not Used (Reserved for future) */ |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 274 | |
| 275 | #define MIPS_200_MHZ 0 |
| 276 | #define MIPS_160_MHZ 1 |
| 277 | |
| 278 | #define PLL_800_MHZ 0 |
| 279 | #define PLL_266_MHZ 1 |
| 280 | |
| 281 | #define DEVICE_POWERSAVE_MODE_AS_MANUAL_CLOCK_GATING 0 |
| 282 | #define DEVICE_POWERSAVE_MODE_AS_PMU_CLOCK_GATING 1 |
| 283 | #define DEVICE_POWERSAVE_MODE_AS_PMU_SHUTDOWN 2 |
| 284 | #define DEVICE_POWERSAVE_MODE_AS_RESERVED 3 |
| 285 | #define DEVICE_POWERSAVE_MODE_AS_PROTOCOL_IDLE_MODE 4 |
| 286 | |
| 287 | |
| 288 | #define EEPROM_REJECT_REG_1 0x0f003018 |
| 289 | #define EEPROM_REJECT_REG_2 0x0f00301c |
| 290 | #define EEPROM_REJECT_REG_3 0x0f003008 |
| 291 | #define EEPROM_REJECT_REG_4 0x0f003020 |
| 292 | #define EEPROM_REJECT_MASK 0x0fffffff |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 293 | #define VSG_MODE 0x3 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 294 | |
| 295 | /* Idle Mode Related Registers */ |
| 296 | #define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 297 | #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 298 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 299 | #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e |
| 300 | #define DEVICE_INT_OUT_EP_REG0 0x0F011870 |
| 301 | #define DEVICE_INT_OUT_EP_REG1 0x0F011874 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 302 | |
| 303 | #define BIN_FILE "/lib/firmware/macxvi200.bin" |
| 304 | #define CFG_FILE "/lib/firmware/macxvi.cfg" |
| 305 | #define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 306 | #define MIN_VAL(x, y) ((x) < (y) ? (x) : (y)) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 307 | #define MAC_ADDRESS_SIZE 6 |
| 308 | #define EEPROM_COMMAND_Q_REG 0x0F003018 |
| 309 | #define EEPROM_READ_DATA_Q_REG 0x0F003020 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 310 | #define CHIP_ID_REG 0x0F000000 |
| 311 | #define GPIO_MODE_REG 0x0F000034 |
| 312 | #define GPIO_OUTPUT_REG 0x0F00003C |
| 313 | #define WIMAX_MAX_ALLOWED_RATE (1024*1024*50) |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 314 | |
| 315 | #define T3 0xbece0300 |
| 316 | #define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400 |
| 317 | |
| 318 | #define RWM_READ 0 |
| 319 | #define RWM_WRITE 1 |
| 320 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 321 | #define T3LPB 0xbece3300 |
| 322 | #define BCS220_2 0xbece3311 |
| 323 | #define BCS220_2BC 0xBECE3310 |
| 324 | #define BCS250_BC 0xbece3301 |
| 325 | #define BCS220_3 0xbece3321 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 326 | |
| 327 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 328 | #define HPM_CONFIG_LDO145 0x0F000D54 |
| 329 | #define HPM_CONFIG_MSW 0x0F000D58 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 330 | |
| 331 | #define T3B 0xbece0310 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 332 | typedef enum eNVM_TYPE { |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 333 | NVM_AUTODETECT = 0, |
| 334 | NVM_EEPROM, |
| 335 | NVM_FLASH, |
| 336 | NVM_UNKNOWN |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 337 | } NVM_TYPE; |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 338 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 339 | typedef enum ePMU_MODES { |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 340 | HYBRID_MODE_7C = 0, |
| 341 | INTERNAL_MODE_6 = 1, |
| 342 | HYBRID_MODE_6 = 2 |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 343 | } PMU_MODE; |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 344 | |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 345 | #define MAX_RDM_WRM_RETIRES 1 |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 346 | |
| 347 | enum eAbortPattern { |
| 348 | ABORT_SHUTDOWN_MODE = 1, |
| 349 | ABORT_IDLE_REG = 1, |
| 350 | ABORT_IDLE_MODE = 2, |
| 351 | ABORT_IDLE_SYNCDOWN = 3 |
| 352 | }; |
| 353 | |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 354 | |
| 355 | /* Offsets used by driver in skb cb variable */ |
| 356 | #define SKB_CB_CLASSIFICATION_OFFSET 0 |
| 357 | #define SKB_CB_LATENCY_OFFSET 1 |
| 358 | #define SKB_CB_TCPACK_OFFSET 2 |
| 359 | |
Ben Wright | 0118885 | 2011-08-17 13:42:50 +1000 | [diff] [blame] | 360 | #endif /* __MACROS_H__ */ |