Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/include/asm/uaccess.h |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | #ifndef __ASM_UACCESS_H |
| 19 | #define __ASM_UACCESS_H |
| 20 | |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 21 | #include <asm/alternative.h> |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 22 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 23 | #include <asm/sysreg.h> |
| 24 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 25 | #ifndef __ASSEMBLY__ |
| 26 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 27 | /* |
| 28 | * User space memory access functions |
| 29 | */ |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 30 | #include <linux/bitops.h> |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 31 | #include <linux/kasan-checks.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 32 | #include <linux/string.h> |
| 33 | #include <linux/thread_info.h> |
| 34 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 35 | #include <asm/cpufeature.h> |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 36 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 37 | #include <asm/ptrace.h> |
| 38 | #include <asm/errno.h> |
| 39 | #include <asm/memory.h> |
| 40 | #include <asm/compiler.h> |
| 41 | |
| 42 | #define VERIFY_READ 0 |
| 43 | #define VERIFY_WRITE 1 |
| 44 | |
| 45 | /* |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 46 | * The exception table consists of pairs of relative offsets: the first |
| 47 | * is the relative offset to an instruction that is allowed to fault, |
| 48 | * and the second is the relative offset at which the program should |
| 49 | * continue. No registers are modified, so it is entirely up to the |
| 50 | * continuation code to figure out what to do. |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 51 | * |
| 52 | * All the routines below use bits of fixup code that are out of line |
| 53 | * with the main instruction path. This means when everything is well, |
| 54 | * we don't even have to jump over them. Further, they do not intrude |
| 55 | * on our cache or tlb entries. |
| 56 | */ |
| 57 | |
| 58 | struct exception_table_entry |
| 59 | { |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 60 | int insn, fixup; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 61 | }; |
| 62 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 63 | #define ARCH_HAS_RELATIVE_EXTABLE |
| 64 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 65 | extern int fixup_exception(struct pt_regs *regs); |
| 66 | |
| 67 | #define KERNEL_DS (-1UL) |
| 68 | #define get_ds() (KERNEL_DS) |
| 69 | |
| 70 | #define USER_DS TASK_SIZE_64 |
| 71 | #define get_fs() (current_thread_info()->addr_limit) |
| 72 | |
| 73 | static inline void set_fs(mm_segment_t fs) |
| 74 | { |
| 75 | current_thread_info()->addr_limit = fs; |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Enable/disable UAO so that copy_to_user() etc can access |
| 79 | * kernel memory with the unprivileged instructions. |
| 80 | */ |
| 81 | if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS) |
| 82 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); |
| 83 | else |
| 84 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO, |
| 85 | CONFIG_ARM64_UAO)); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 86 | } |
| 87 | |
Michael S. Tsirkin | 967f0e5 | 2015-01-06 15:11:13 +0200 | [diff] [blame] | 88 | #define segment_eq(a, b) ((a) == (b)) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 89 | |
| 90 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 91 | * Test whether a block of memory is a valid user space address. |
| 92 | * Returns 1 if the range is valid, 0 otherwise. |
| 93 | * |
| 94 | * This is equivalent to the following test: |
Christopher Covington | 31b1e94 | 2014-03-19 16:29:37 +0000 | [diff] [blame] | 95 | * (u65)addr + (u65)size <= current->addr_limit |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 96 | * |
| 97 | * This needs 65-bit arithmetic. |
| 98 | */ |
| 99 | #define __range_ok(addr, size) \ |
| 100 | ({ \ |
| 101 | unsigned long flag, roksum; \ |
| 102 | __chk_user_ptr(addr); \ |
Christopher Covington | 31b1e94 | 2014-03-19 16:29:37 +0000 | [diff] [blame] | 103 | asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 104 | : "=&r" (flag), "=&r" (roksum) \ |
| 105 | : "1" (addr), "Ir" (size), \ |
| 106 | "r" (current_thread_info()->addr_limit) \ |
| 107 | : "cc"); \ |
| 108 | flag; \ |
| 109 | }) |
| 110 | |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 111 | /* |
| 112 | * When dealing with data aborts or instruction traps we may end up with |
| 113 | * a tagged userland pointer. Clear the tag to get a sane pointer to pass |
| 114 | * on to access_ok(), for instance. |
| 115 | */ |
| 116 | #define untagged_addr(addr) sign_extend64(addr, 55) |
| 117 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 118 | #define access_ok(type, addr, size) __range_ok(addr, size) |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 119 | #define user_addr_max get_fs |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 120 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 121 | #define _ASM_EXTABLE(from, to) \ |
| 122 | " .pushsection __ex_table, \"a\"\n" \ |
| 123 | " .align 3\n" \ |
| 124 | " .long (" #from " - .), (" #to " - .)\n" \ |
| 125 | " .popsection\n" |
| 126 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 127 | /* |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 128 | * User access enabling/disabling. |
| 129 | */ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 130 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 131 | static inline void __uaccess_ttbr0_disable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 132 | { |
| 133 | unsigned long ttbr; |
| 134 | |
| 135 | /* reserved_ttbr0 placed at the end of swapper_pg_dir */ |
| 136 | ttbr = read_sysreg(ttbr1_el1) + SWAPPER_DIR_SIZE; |
| 137 | write_sysreg(ttbr, ttbr0_el1); |
| 138 | isb(); |
| 139 | } |
| 140 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 141 | static inline void __uaccess_ttbr0_enable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 142 | { |
| 143 | unsigned long flags; |
| 144 | |
| 145 | /* |
| 146 | * Disable interrupts to avoid preemption between reading the 'ttbr0' |
| 147 | * variable and the MSR. A context switch could trigger an ASID |
| 148 | * roll-over and an update of 'ttbr0'. |
| 149 | */ |
| 150 | local_irq_save(flags); |
| 151 | write_sysreg(current_thread_info()->ttbr0, ttbr0_el1); |
| 152 | isb(); |
| 153 | local_irq_restore(flags); |
| 154 | } |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 155 | |
| 156 | static inline bool uaccess_ttbr0_disable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 157 | { |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 158 | if (!system_uses_ttbr0_pan()) |
| 159 | return false; |
| 160 | __uaccess_ttbr0_disable(); |
| 161 | return true; |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 162 | } |
| 163 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 164 | static inline bool uaccess_ttbr0_enable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 165 | { |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 166 | if (!system_uses_ttbr0_pan()) |
| 167 | return false; |
| 168 | __uaccess_ttbr0_enable(); |
| 169 | return true; |
| 170 | } |
| 171 | #else |
| 172 | static inline bool uaccess_ttbr0_disable(void) |
| 173 | { |
| 174 | return false; |
| 175 | } |
| 176 | |
| 177 | static inline bool uaccess_ttbr0_enable(void) |
| 178 | { |
| 179 | return false; |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 180 | } |
| 181 | #endif |
| 182 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 183 | #define __uaccess_disable(alt) \ |
| 184 | do { \ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 185 | if (!uaccess_ttbr0_disable()) \ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 186 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ |
| 187 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 188 | } while (0) |
| 189 | |
| 190 | #define __uaccess_enable(alt) \ |
| 191 | do { \ |
Marc Zyngier | 093284e | 2016-12-12 13:50:26 +0000 | [diff] [blame] | 192 | if (!uaccess_ttbr0_enable()) \ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 193 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ |
| 194 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 195 | } while (0) |
| 196 | |
| 197 | static inline void uaccess_disable(void) |
| 198 | { |
| 199 | __uaccess_disable(ARM64_HAS_PAN); |
| 200 | } |
| 201 | |
| 202 | static inline void uaccess_enable(void) |
| 203 | { |
| 204 | __uaccess_enable(ARM64_HAS_PAN); |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * These functions are no-ops when UAO is present. |
| 209 | */ |
| 210 | static inline void uaccess_disable_not_uao(void) |
| 211 | { |
| 212 | __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); |
| 213 | } |
| 214 | |
| 215 | static inline void uaccess_enable_not_uao(void) |
| 216 | { |
| 217 | __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); |
| 218 | } |
| 219 | |
| 220 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 221 | * The "__xxx" versions of the user access functions do not verify the address |
| 222 | * space - it must have been done previously with a separate "access_ok()" |
| 223 | * call. |
| 224 | * |
| 225 | * The "__xxx_error" versions set the third argument to -EFAULT if an error |
| 226 | * occurs, and leave it unchanged on success. |
| 227 | */ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 228 | #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 229 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 230 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 231 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 232 | "2:\n" \ |
| 233 | " .section .fixup, \"ax\"\n" \ |
| 234 | " .align 2\n" \ |
| 235 | "3: mov %w0, %3\n" \ |
| 236 | " mov %1, #0\n" \ |
| 237 | " b 2b\n" \ |
| 238 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 239 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 240 | : "+r" (err), "=&r" (x) \ |
| 241 | : "r" (addr), "i" (-EFAULT)) |
| 242 | |
| 243 | #define __get_user_err(x, ptr, err) \ |
| 244 | do { \ |
| 245 | unsigned long __gu_val; \ |
| 246 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 247 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 248 | switch (sizeof(*(ptr))) { \ |
| 249 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 250 | __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \ |
| 251 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 252 | break; \ |
| 253 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 254 | __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \ |
| 255 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 256 | break; \ |
| 257 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 258 | __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \ |
| 259 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 260 | break; \ |
| 261 | case 8: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 262 | __get_user_asm("ldr", "ldtr", "%", __gu_val, (ptr), \ |
| 263 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 264 | break; \ |
| 265 | default: \ |
| 266 | BUILD_BUG(); \ |
| 267 | } \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 268 | uaccess_disable_not_uao(); \ |
Michael S. Tsirkin | 58fff51 | 2014-12-12 01:56:04 +0200 | [diff] [blame] | 269 | (x) = (__force __typeof__(*(ptr)))__gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 270 | } while (0) |
| 271 | |
| 272 | #define __get_user(x, ptr) \ |
| 273 | ({ \ |
| 274 | int __gu_err = 0; \ |
| 275 | __get_user_err((x), (ptr), __gu_err); \ |
| 276 | __gu_err; \ |
| 277 | }) |
| 278 | |
| 279 | #define __get_user_error(x, ptr, err) \ |
| 280 | ({ \ |
| 281 | __get_user_err((x), (ptr), (err)); \ |
| 282 | (void)0; \ |
| 283 | }) |
| 284 | |
| 285 | #define __get_user_unaligned __get_user |
| 286 | |
| 287 | #define get_user(x, ptr) \ |
| 288 | ({ \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 289 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
Michael S. Tsirkin | 56d2ef7 | 2013-05-26 17:30:42 +0300 | [diff] [blame] | 290 | might_fault(); \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 291 | access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ |
| 292 | __get_user((x), __p) : \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 293 | ((x) = 0, -EFAULT); \ |
| 294 | }) |
| 295 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 296 | #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 297 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 298 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 299 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 300 | "2:\n" \ |
| 301 | " .section .fixup,\"ax\"\n" \ |
| 302 | " .align 2\n" \ |
| 303 | "3: mov %w0, %3\n" \ |
| 304 | " b 2b\n" \ |
| 305 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 306 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 307 | : "+r" (err) \ |
| 308 | : "r" (x), "r" (addr), "i" (-EFAULT)) |
| 309 | |
| 310 | #define __put_user_err(x, ptr, err) \ |
| 311 | do { \ |
| 312 | __typeof__(*(ptr)) __pu_val = (x); \ |
| 313 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 314 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 315 | switch (sizeof(*(ptr))) { \ |
| 316 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 317 | __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \ |
| 318 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 319 | break; \ |
| 320 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 321 | __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \ |
| 322 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 323 | break; \ |
| 324 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 325 | __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \ |
| 326 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 327 | break; \ |
| 328 | case 8: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 329 | __put_user_asm("str", "sttr", "%", __pu_val, (ptr), \ |
| 330 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 331 | break; \ |
| 332 | default: \ |
| 333 | BUILD_BUG(); \ |
| 334 | } \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 335 | uaccess_disable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 336 | } while (0) |
| 337 | |
| 338 | #define __put_user(x, ptr) \ |
| 339 | ({ \ |
| 340 | int __pu_err = 0; \ |
| 341 | __put_user_err((x), (ptr), __pu_err); \ |
| 342 | __pu_err; \ |
| 343 | }) |
| 344 | |
| 345 | #define __put_user_error(x, ptr, err) \ |
| 346 | ({ \ |
| 347 | __put_user_err((x), (ptr), (err)); \ |
| 348 | (void)0; \ |
| 349 | }) |
| 350 | |
| 351 | #define __put_user_unaligned __put_user |
| 352 | |
| 353 | #define put_user(x, ptr) \ |
| 354 | ({ \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 355 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
Michael S. Tsirkin | 56d2ef7 | 2013-05-26 17:30:42 +0300 | [diff] [blame] | 356 | might_fault(); \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 357 | access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ |
| 358 | __put_user((x), __p) : \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 359 | -EFAULT; \ |
| 360 | }) |
| 361 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 362 | extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); |
| 363 | extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 364 | extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); |
| 365 | extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); |
| 366 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 367 | static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) |
| 368 | { |
| 369 | kasan_check_write(to, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 370 | check_object_size(to, n, false); |
| 371 | return __arch_copy_from_user(to, from, n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) |
| 375 | { |
| 376 | kasan_check_read(from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 377 | check_object_size(from, n, true); |
| 378 | return __arch_copy_to_user(to, from, n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 379 | } |
| 380 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 381 | static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) |
| 382 | { |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 383 | unsigned long res = n; |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 384 | kasan_check_write(to, n); |
| 385 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 386 | if (access_ok(VERIFY_READ, from, n)) { |
| 387 | check_object_size(to, n, false); |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 388 | res = __arch_copy_from_user(to, from, n); |
| 389 | } |
| 390 | if (unlikely(res)) |
| 391 | memset(to + (n - res), 0, res); |
| 392 | return res; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) |
| 396 | { |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 397 | kasan_check_read(from, n); |
| 398 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 399 | if (access_ok(VERIFY_WRITE, to, n)) { |
| 400 | check_object_size(from, n, true); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 401 | n = __arch_copy_to_user(to, from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 402 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 403 | return n; |
| 404 | } |
| 405 | |
| 406 | static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n) |
| 407 | { |
| 408 | if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) |
| 409 | n = __copy_in_user(to, from, n); |
| 410 | return n; |
| 411 | } |
| 412 | |
| 413 | #define __copy_to_user_inatomic __copy_to_user |
| 414 | #define __copy_from_user_inatomic __copy_from_user |
| 415 | |
| 416 | static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) |
| 417 | { |
| 418 | if (access_ok(VERIFY_WRITE, to, n)) |
| 419 | n = __clear_user(to, n); |
| 420 | return n; |
| 421 | } |
| 422 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 423 | extern long strncpy_from_user(char *dest, const char __user *src, long count); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 424 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 425 | extern __must_check long strlen_user(const char __user *str); |
| 426 | extern __must_check long strnlen_user(const char __user *str, long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 427 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 428 | #else /* __ASSEMBLY__ */ |
| 429 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 430 | #include <asm/assembler.h> |
| 431 | |
| 432 | /* |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 433 | * User access enabling/disabling macros. |
| 434 | */ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 435 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 436 | .macro __uaccess_ttbr0_disable, tmp1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 437 | mrs \tmp1, ttbr1_el1 // swapper_pg_dir |
| 438 | add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir |
| 439 | msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 |
| 440 | isb |
| 441 | .endm |
| 442 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 443 | .macro __uaccess_ttbr0_enable, tmp1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 444 | get_thread_info \tmp1 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 445 | ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 446 | msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 |
| 447 | isb |
| 448 | .endm |
| 449 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 450 | .macro uaccess_ttbr0_disable, tmp1 |
| 451 | alternative_if_not ARM64_HAS_PAN |
| 452 | __uaccess_ttbr0_disable \tmp1 |
| 453 | alternative_else_nop_endif |
| 454 | .endm |
| 455 | |
| 456 | .macro uaccess_ttbr0_enable, tmp1, tmp2 |
| 457 | alternative_if_not ARM64_HAS_PAN |
| 458 | save_and_disable_irq \tmp2 // avoid preemption |
| 459 | __uaccess_ttbr0_enable \tmp1 |
| 460 | restore_irq \tmp2 |
| 461 | alternative_else_nop_endif |
| 462 | .endm |
| 463 | #else |
| 464 | .macro uaccess_ttbr0_disable, tmp1 |
| 465 | .endm |
| 466 | |
| 467 | .macro uaccess_ttbr0_enable, tmp1, tmp2 |
| 468 | .endm |
| 469 | #endif |
| 470 | |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 471 | /* |
| 472 | * These macros are no-ops when UAO is present. |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 473 | */ |
| 474 | .macro uaccess_disable_not_uao, tmp1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 475 | uaccess_ttbr0_disable \tmp1 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 476 | alternative_if ARM64_ALT_PAN_NOT_UAO |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 477 | SET_PSTATE_PAN(1) |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 478 | alternative_else_nop_endif |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 479 | .endm |
| 480 | |
| 481 | .macro uaccess_enable_not_uao, tmp1, tmp2 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 482 | uaccess_ttbr0_enable \tmp1, \tmp2 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 483 | alternative_if ARM64_ALT_PAN_NOT_UAO |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 484 | SET_PSTATE_PAN(0) |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 485 | alternative_else_nop_endif |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 486 | .endm |
| 487 | |
| 488 | #endif /* __ASSEMBLY__ */ |
| 489 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 490 | #endif /* __ASM_UACCESS_H */ |