Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "haptics: %s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/atomic.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/hrtimer.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/log2.h> |
| 21 | #include <linux/leds.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/of_device.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/pwm.h> |
| 26 | #include <linux/regmap.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/qpnp/qpnp-misc.h> |
| 29 | #include <linux/qpnp/qpnp-revid.h> |
| 30 | |
| 31 | /* Register definitions */ |
| 32 | #define HAP_STATUS_1_REG(chip) (chip->base + 0x0A) |
| 33 | #define HAP_BUSY_BIT BIT(1) |
| 34 | #define SC_FLAG_BIT BIT(3) |
| 35 | #define AUTO_RES_ERROR_BIT BIT(4) |
| 36 | |
| 37 | #define HAP_LRA_AUTO_RES_LO_REG(chip) (chip->base + 0x0B) |
| 38 | #define HAP_LRA_AUTO_RES_HI_REG(chip) (chip->base + 0x0C) |
| 39 | |
| 40 | #define HAP_INT_RT_STS_REG(chip) (chip->base + 0x10) |
| 41 | #define SC_INT_RT_STS_BIT BIT(0) |
| 42 | #define PLAY_INT_RT_STS_BIT BIT(1) |
| 43 | |
| 44 | #define HAP_EN_CTL_REG(chip) (chip->base + 0x46) |
| 45 | #define HAP_EN_BIT BIT(7) |
| 46 | |
| 47 | #define HAP_EN_CTL2_REG(chip) (chip->base + 0x48) |
| 48 | #define BRAKE_EN_BIT BIT(0) |
| 49 | |
| 50 | #define HAP_AUTO_RES_CTRL_REG(chip) (chip->base + 0x4B) |
| 51 | #define AUTO_RES_EN_BIT BIT(7) |
| 52 | #define AUTO_RES_ERR_RECOVERY_BIT BIT(3) |
| 53 | |
| 54 | #define HAP_CFG1_REG(chip) (chip->base + 0x4C) |
| 55 | #define HAP_ACT_TYPE_MASK BIT(0) |
| 56 | #define HAP_LRA 0 |
| 57 | #define HAP_ERM 1 |
| 58 | |
| 59 | #define HAP_CFG2_REG(chip) (chip->base + 0x4D) |
| 60 | #define HAP_WAVE_SINE 0 |
| 61 | #define HAP_WAVE_SQUARE 1 |
| 62 | #define HAP_LRA_RES_TYPE_MASK BIT(0) |
| 63 | |
| 64 | #define HAP_SEL_REG(chip) (chip->base + 0x4E) |
| 65 | #define HAP_WF_SOURCE_MASK GENMASK(5, 4) |
| 66 | #define HAP_WF_SOURCE_SHIFT 4 |
| 67 | |
| 68 | #define HAP_LRA_AUTO_RES_REG(chip) (chip->base + 0x4F) |
| 69 | /* For pmi8998 */ |
| 70 | #define LRA_AUTO_RES_MODE_MASK GENMASK(6, 4) |
| 71 | #define LRA_AUTO_RES_MODE_SHIFT 4 |
| 72 | #define LRA_HIGH_Z_MASK GENMASK(3, 2) |
| 73 | #define LRA_HIGH_Z_SHIFT 2 |
| 74 | #define LRA_RES_CAL_MASK GENMASK(1, 0) |
| 75 | #define HAP_RES_CAL_PERIOD_MIN 4 |
| 76 | #define HAP_RES_CAL_PERIOD_MAX 32 |
| 77 | /* For pm660 */ |
| 78 | #define PM660_AUTO_RES_MODE_BIT BIT(7) |
| 79 | #define PM660_AUTO_RES_MODE_SHIFT 7 |
| 80 | #define PM660_CAL_DURATION_MASK GENMASK(6, 5) |
| 81 | #define PM660_CAL_DURATION_SHIFT 5 |
| 82 | #define PM660_QWD_DRIVE_DURATION_BIT BIT(4) |
| 83 | #define PM660_QWD_DRIVE_DURATION_SHIFT 4 |
| 84 | #define PM660_CAL_EOP_BIT BIT(3) |
| 85 | #define PM660_CAL_EOP_SHIFT 3 |
| 86 | #define PM660_LRA_RES_CAL_MASK GENMASK(2, 0) |
| 87 | #define HAP_PM660_RES_CAL_PERIOD_MAX 256 |
| 88 | |
| 89 | #define HAP_VMAX_CFG_REG(chip) (chip->base + 0x51) |
| 90 | #define HAP_VMAX_OVD_BIT BIT(6) |
| 91 | #define HAP_VMAX_MASK GENMASK(5, 1) |
| 92 | #define HAP_VMAX_SHIFT 1 |
| 93 | #define HAP_VMAX_MIN_MV 116 |
| 94 | #define HAP_VMAX_MAX_MV 3596 |
| 95 | |
| 96 | #define HAP_ILIM_CFG_REG(chip) (chip->base + 0x52) |
| 97 | #define HAP_ILIM_SEL_MASK BIT(0) |
| 98 | #define HAP_ILIM_400_MA 0 |
| 99 | #define HAP_ILIM_800_MA 1 |
| 100 | |
| 101 | #define HAP_SC_DEB_REG(chip) (chip->base + 0x53) |
| 102 | #define HAP_SC_DEB_MASK GENMASK(2, 0) |
| 103 | #define HAP_SC_DEB_CYCLES_MIN 0 |
| 104 | #define HAP_DEF_SC_DEB_CYCLES 8 |
| 105 | #define HAP_SC_DEB_CYCLES_MAX 32 |
| 106 | |
| 107 | #define HAP_RATE_CFG1_REG(chip) (chip->base + 0x54) |
| 108 | #define HAP_RATE_CFG1_MASK GENMASK(7, 0) |
| 109 | |
| 110 | #define HAP_RATE_CFG2_REG(chip) (chip->base + 0x55) |
| 111 | #define HAP_RATE_CFG2_MASK GENMASK(3, 0) |
| 112 | /* Shift needed to convert drive period upper bits [11:8] */ |
| 113 | #define HAP_RATE_CFG2_SHIFT 8 |
| 114 | |
| 115 | #define HAP_INT_PWM_REG(chip) (chip->base + 0x56) |
| 116 | #define INT_PWM_FREQ_SEL_MASK GENMASK(1, 0) |
| 117 | #define INT_PWM_FREQ_253_KHZ 0 |
| 118 | #define INT_PWM_FREQ_505_KHZ 1 |
| 119 | #define INT_PWM_FREQ_739_KHZ 2 |
| 120 | #define INT_PWM_FREQ_1076_KHZ 3 |
| 121 | |
| 122 | #define HAP_EXT_PWM_REG(chip) (chip->base + 0x57) |
| 123 | #define EXT_PWM_FREQ_SEL_MASK GENMASK(1, 0) |
| 124 | #define EXT_PWM_FREQ_25_KHZ 0 |
| 125 | #define EXT_PWM_FREQ_50_KHZ 1 |
| 126 | #define EXT_PWM_FREQ_75_KHZ 2 |
| 127 | #define EXT_PWM_FREQ_100_KHZ 3 |
| 128 | |
| 129 | #define HAP_PWM_CAP_REG(chip) (chip->base + 0x58) |
| 130 | |
| 131 | #define HAP_SC_CLR_REG(chip) (chip->base + 0x59) |
| 132 | #define SC_CLR_BIT BIT(0) |
| 133 | |
| 134 | #define HAP_BRAKE_REG(chip) (chip->base + 0x5C) |
| 135 | #define HAP_BRAKE_PAT_MASK 0x3 |
| 136 | |
| 137 | #define HAP_WF_REPEAT_REG(chip) (chip->base + 0x5E) |
| 138 | #define WF_REPEAT_MASK GENMASK(6, 4) |
| 139 | #define WF_REPEAT_SHIFT 4 |
| 140 | #define WF_REPEAT_MIN 1 |
| 141 | #define WF_REPEAT_MAX 128 |
| 142 | #define WF_S_REPEAT_MASK GENMASK(1, 0) |
| 143 | #define WF_S_REPEAT_MIN 1 |
| 144 | #define WF_S_REPEAT_MAX 8 |
| 145 | |
| 146 | #define HAP_WF_S1_REG(chip) (chip->base + 0x60) |
| 147 | #define HAP_WF_SIGN_BIT BIT(7) |
| 148 | #define HAP_WF_OVD_BIT BIT(6) |
| 149 | #define HAP_WF_SAMP_MAX GENMASK(5, 1) |
| 150 | #define HAP_WF_SAMPLE_LEN 8 |
| 151 | |
| 152 | #define HAP_PLAY_REG(chip) (chip->base + 0x70) |
| 153 | #define PLAY_BIT BIT(7) |
| 154 | #define PAUSE_BIT BIT(0) |
| 155 | |
| 156 | #define HAP_SEC_ACCESS_REG(chip) (chip->base + 0xD0) |
| 157 | |
| 158 | #define HAP_TEST2_REG(chip) (chip->base + 0xE3) |
| 159 | #define HAP_EXT_PWM_DTEST_MASK GENMASK(6, 4) |
| 160 | #define HAP_EXT_PWM_DTEST_SHIFT 4 |
| 161 | #define PWM_MAX_DTEST_LINES 4 |
| 162 | #define HAP_EXT_PWM_PEAK_DATA 0x7F |
| 163 | #define HAP_EXT_PWM_HALF_DUTY 50 |
| 164 | #define HAP_EXT_PWM_FULL_DUTY 100 |
| 165 | #define HAP_EXT_PWM_DATA_FACTOR 39 |
| 166 | |
| 167 | /* Other definitions */ |
| 168 | #define HAP_BRAKE_PAT_LEN 4 |
| 169 | #define HAP_WAVE_SAMP_LEN 8 |
| 170 | #define NUM_WF_SET 4 |
| 171 | #define HAP_WAVE_SAMP_SET_LEN (HAP_WAVE_SAMP_LEN * NUM_WF_SET) |
| 172 | #define HAP_RATE_CFG_STEP_US 5 |
| 173 | #define HAP_WAVE_PLAY_RATE_US_MIN 0 |
| 174 | #define HAP_DEF_WAVE_PLAY_RATE_US 5715 |
| 175 | #define HAP_WAVE_PLAY_RATE_US_MAX 20475 |
| 176 | #define HAP_MAX_PLAY_TIME_MS 15000 |
| 177 | |
| 178 | enum hap_brake_pat { |
| 179 | NO_BRAKE = 0, |
| 180 | BRAKE_VMAX_4, |
| 181 | BRAKE_VMAX_2, |
| 182 | BRAKE_VMAX, |
| 183 | }; |
| 184 | |
| 185 | enum hap_auto_res_mode { |
| 186 | HAP_AUTO_RES_NONE, |
| 187 | HAP_AUTO_RES_ZXD, |
| 188 | HAP_AUTO_RES_QWD, |
| 189 | HAP_AUTO_RES_MAX_QWD, |
| 190 | HAP_AUTO_RES_ZXD_EOP, |
| 191 | }; |
| 192 | |
| 193 | enum hap_pm660_auto_res_mode { |
| 194 | HAP_PM660_AUTO_RES_ZXD, |
| 195 | HAP_PM660_AUTO_RES_QWD, |
| 196 | }; |
| 197 | |
| 198 | /* high Z option lines */ |
| 199 | enum hap_high_z { |
| 200 | HAP_LRA_HIGH_Z_NONE, /* opt0 for PM660 */ |
| 201 | HAP_LRA_HIGH_Z_OPT1, |
| 202 | HAP_LRA_HIGH_Z_OPT2, |
| 203 | HAP_LRA_HIGH_Z_OPT3, |
| 204 | }; |
| 205 | |
| 206 | /* play modes */ |
| 207 | enum hap_mode { |
| 208 | HAP_DIRECT, |
| 209 | HAP_BUFFER, |
| 210 | HAP_AUDIO, |
| 211 | HAP_PWM, |
| 212 | }; |
| 213 | |
| 214 | /* wave/sample repeat */ |
| 215 | enum hap_rep_type { |
| 216 | HAP_WAVE_REPEAT = 1, |
| 217 | HAP_WAVE_SAMP_REPEAT, |
| 218 | }; |
| 219 | |
| 220 | /* status flags */ |
| 221 | enum hap_status { |
| 222 | AUTO_RESONANCE_ENABLED = BIT(0), |
| 223 | }; |
| 224 | |
| 225 | enum hap_play_control { |
| 226 | HAP_STOP, |
| 227 | HAP_PAUSE, |
| 228 | HAP_PLAY, |
| 229 | }; |
| 230 | |
| 231 | /* pwm channel parameters */ |
| 232 | struct pwm_param { |
| 233 | struct pwm_device *pwm_dev; |
| 234 | u32 duty_us; |
| 235 | u32 period_us; |
| 236 | }; |
| 237 | |
| 238 | /* |
| 239 | * hap_lra_ares_param - Haptic auto_resonance parameters |
| 240 | * @ lra_qwd_drive_duration - LRA QWD drive duration |
| 241 | * @ calibrate_at_eop - Calibrate at EOP |
| 242 | * @ lra_res_cal_period - LRA resonance calibration period |
| 243 | * @ auto_res_mode - auto resonace mode |
| 244 | * @ lra_high_z - high z option line |
| 245 | */ |
| 246 | struct hap_lra_ares_param { |
| 247 | int lra_qwd_drive_duration; |
| 248 | int calibrate_at_eop; |
| 249 | enum hap_high_z lra_high_z; |
| 250 | u16 lra_res_cal_period; |
| 251 | u8 auto_res_mode; |
| 252 | }; |
| 253 | |
| 254 | /* |
| 255 | * hap_chip - Haptics data structure |
| 256 | * @ pdev - platform device pointer |
| 257 | * @ regmap - regmap pointer |
| 258 | * @ bus_lock - spin lock for bus read/write |
| 259 | * @ play_lock - mutex lock for haptics play/enable control |
| 260 | * @ haptics_work - haptics worker |
| 261 | * @ stop_timer - hrtimer for stopping haptics |
| 262 | * @ auto_res_err_poll_timer - hrtimer for auto-resonance error |
| 263 | * @ base - base address |
| 264 | * @ play_irq - irq for play |
| 265 | * @ sc_irq - irq for short circuit |
| 266 | * @ pwm_data - pwm configuration |
| 267 | * @ ares_cfg - auto resonance configuration |
| 268 | * @ play_time_ms - play time set by the user in ms |
| 269 | * @ max_play_time_ms - max play time in ms |
| 270 | * @ vmax_mv - max voltage in mv |
| 271 | * @ ilim_ma - limiting current in ma |
| 272 | * @ sc_deb_cycles - short circuit debounce cycles |
| 273 | * @ wave_play_rate_us - play rate for waveform |
| 274 | * @ last_rate_cfg - Last rate config updated |
| 275 | * @ wave_rep_cnt - waveform repeat count |
| 276 | * @ wave_s_rep_cnt - waveform sample repeat count |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 277 | * @ wf_samp_len - waveform sample length |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 278 | * @ ext_pwm_freq_khz - external pwm frequency in KHz |
| 279 | * @ ext_pwm_dtest_line - DTEST line for external pwm |
| 280 | * @ status_flags - status |
| 281 | * @ play_mode - play mode |
| 282 | * @ act_type - actuator type |
| 283 | * @ wave_shape - waveform shape |
| 284 | * @ wave_samp_idx - wave sample id used to refer start of a sample set |
| 285 | * @ wave_samp - array of wave samples |
| 286 | * @ brake_pat - pattern for active breaking |
| 287 | * @ en_brake - brake state |
| 288 | * @ misc_clk_trim_error_reg - MISC clock trim error register if present |
| 289 | * @ clk_trim_error_code - MISC clock trim error code |
| 290 | * @ drive_period_code_max_limit - calculated drive period code with |
| 291 | percentage variation on the higher side. |
| 292 | * @ drive_period_code_min_limit - calculated drive period code with |
| 293 | percentage variation on the lower side |
| 294 | * @ drive_period_code_max_var_pct - maximum limit of percentage variation of |
| 295 | drive period code |
| 296 | * @ drive_period_code_min_var_pct - minimum limit of percentage variation of |
| 297 | drive period code |
| 298 | * @ last_sc_time - Last time short circuit was detected |
| 299 | * @ sc_count - counter to determine the duration of short circuit |
| 300 | condition |
| 301 | * @ perm_disable - Flag to disable module permanently |
| 302 | * @ state - current state of haptics |
| 303 | * @ module_en - module enable status of haptics |
| 304 | * @ lra_auto_mode - Auto mode selection |
| 305 | * @ play_irq_en - Play interrupt enable status |
| 306 | * @ auto_res_err_recovery_hw - Enable auto resonance error recovery by HW |
| 307 | */ |
| 308 | struct hap_chip { |
| 309 | struct platform_device *pdev; |
| 310 | struct regmap *regmap; |
| 311 | struct pmic_revid_data *revid; |
| 312 | struct led_classdev cdev; |
| 313 | spinlock_t bus_lock; |
| 314 | struct mutex play_lock; |
| 315 | struct mutex param_lock; |
| 316 | struct work_struct haptics_work; |
| 317 | struct hrtimer stop_timer; |
| 318 | struct hrtimer auto_res_err_poll_timer; |
| 319 | u16 base; |
| 320 | int play_irq; |
| 321 | int sc_irq; |
| 322 | struct pwm_param pwm_data; |
| 323 | struct hap_lra_ares_param ares_cfg; |
| 324 | u32 play_time_ms; |
| 325 | u32 max_play_time_ms; |
| 326 | u32 vmax_mv; |
| 327 | u8 ilim_ma; |
| 328 | u32 sc_deb_cycles; |
| 329 | u32 wave_play_rate_us; |
| 330 | u16 last_rate_cfg; |
| 331 | u32 wave_rep_cnt; |
| 332 | u32 wave_s_rep_cnt; |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 333 | u32 wf_samp_len; |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 334 | u32 ext_pwm_freq_khz; |
| 335 | u8 ext_pwm_dtest_line; |
| 336 | u32 status_flags; |
| 337 | enum hap_mode play_mode; |
| 338 | u8 act_type; |
| 339 | u8 wave_shape; |
| 340 | u8 wave_samp_idx; |
| 341 | u32 wave_samp[HAP_WAVE_SAMP_SET_LEN]; |
| 342 | u32 brake_pat[HAP_BRAKE_PAT_LEN]; |
| 343 | bool en_brake; |
| 344 | u32 misc_clk_trim_error_reg; |
| 345 | u8 clk_trim_error_code; |
| 346 | u16 drive_period_code_max_limit; |
| 347 | u16 drive_period_code_min_limit; |
| 348 | u8 drive_period_code_max_var_pct; |
| 349 | u8 drive_period_code_min_var_pct; |
| 350 | ktime_t last_sc_time; |
| 351 | u8 sc_count; |
| 352 | bool perm_disable; |
| 353 | atomic_t state; |
| 354 | bool module_en; |
| 355 | bool lra_auto_mode; |
| 356 | bool play_irq_en; |
| 357 | bool auto_res_err_recovery_hw; |
| 358 | }; |
| 359 | |
| 360 | static int qpnp_haptics_parse_buffer_dt(struct hap_chip *chip); |
| 361 | static int qpnp_haptics_parse_pwm_dt(struct hap_chip *chip); |
| 362 | |
| 363 | static int qpnp_haptics_read_reg(struct hap_chip *chip, u16 addr, u8 *val, |
| 364 | int len) |
| 365 | { |
| 366 | int rc; |
| 367 | |
| 368 | rc = regmap_bulk_read(chip->regmap, addr, val, len); |
| 369 | if (rc < 0) |
| 370 | pr_err("Error reading address: 0x%x - rc %d\n", addr, rc); |
| 371 | |
| 372 | return rc; |
| 373 | } |
| 374 | |
| 375 | static inline bool is_secure(u16 addr) |
| 376 | { |
| 377 | return ((addr & 0xFF) > 0xD0); |
| 378 | } |
| 379 | |
| 380 | static int qpnp_haptics_write_reg(struct hap_chip *chip, u16 addr, u8 *val, |
| 381 | int len) |
| 382 | { |
| 383 | unsigned long flags; |
| 384 | unsigned int unlock = 0xA5; |
| 385 | int rc = 0, i; |
| 386 | |
| 387 | spin_lock_irqsave(&chip->bus_lock, flags); |
| 388 | |
| 389 | if (is_secure(addr)) { |
| 390 | for (i = 0; i < len; i++) { |
| 391 | rc = regmap_write(chip->regmap, |
| 392 | HAP_SEC_ACCESS_REG(chip), unlock); |
| 393 | if (rc < 0) { |
| 394 | pr_err("Error writing unlock code - rc %d\n", |
| 395 | rc); |
| 396 | goto out; |
| 397 | } |
| 398 | |
| 399 | rc = regmap_write(chip->regmap, addr + i, val[i]); |
| 400 | if (rc < 0) { |
| 401 | pr_err("Error writing address 0x%x - rc %d\n", |
| 402 | addr + i, rc); |
| 403 | goto out; |
| 404 | } |
| 405 | } |
| 406 | } else { |
| 407 | if (len > 1) |
| 408 | rc = regmap_bulk_write(chip->regmap, addr, val, len); |
| 409 | else |
| 410 | rc = regmap_write(chip->regmap, addr, *val); |
| 411 | } |
| 412 | |
| 413 | if (rc < 0) |
| 414 | pr_err("Error writing address: 0x%x - rc %d\n", addr, rc); |
| 415 | |
| 416 | out: |
| 417 | spin_unlock_irqrestore(&chip->bus_lock, flags); |
| 418 | return rc; |
| 419 | } |
| 420 | |
| 421 | static int qpnp_haptics_masked_write_reg(struct hap_chip *chip, u16 addr, |
| 422 | u8 mask, u8 val) |
| 423 | { |
| 424 | unsigned long flags; |
| 425 | unsigned int unlock = 0xA5; |
| 426 | int rc; |
| 427 | |
| 428 | spin_lock_irqsave(&chip->bus_lock, flags); |
| 429 | if (is_secure(addr)) { |
| 430 | rc = regmap_write(chip->regmap, HAP_SEC_ACCESS_REG(chip), |
| 431 | unlock); |
| 432 | if (rc < 0) { |
| 433 | pr_err("Error writing unlock code - rc %d\n", rc); |
| 434 | goto out; |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | rc = regmap_update_bits(chip->regmap, addr, mask, val); |
| 439 | if (rc < 0) |
| 440 | pr_err("Error writing address: 0x%x - rc %d\n", addr, rc); |
| 441 | |
| 442 | if (!rc) |
| 443 | pr_debug("wrote to address 0x%x = 0x%x\n", addr, val); |
| 444 | out: |
| 445 | spin_unlock_irqrestore(&chip->bus_lock, flags); |
| 446 | return rc; |
| 447 | } |
| 448 | |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 449 | static inline int get_buffer_mode_duration(struct hap_chip *chip) |
| 450 | { |
| 451 | int sample_count, sample_duration; |
| 452 | |
| 453 | sample_count = chip->wave_rep_cnt * chip->wave_s_rep_cnt * |
| 454 | chip->wf_samp_len; |
| 455 | sample_duration = sample_count * chip->wave_play_rate_us; |
| 456 | pr_debug("sample_count: %d sample_duration: %d\n", sample_count, |
| 457 | sample_duration); |
| 458 | |
| 459 | return (sample_duration / 1000); |
| 460 | } |
| 461 | |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 462 | static bool is_sw_lra_auto_resonance_control(struct hap_chip *chip) |
| 463 | { |
| 464 | if (chip->act_type != HAP_LRA) |
| 465 | return false; |
| 466 | |
| 467 | if (chip->auto_res_err_recovery_hw) |
| 468 | return false; |
| 469 | |
| 470 | /* |
| 471 | * For short pattern in auto mode, we use buffer mode and auto |
| 472 | * resonance is not needed. |
| 473 | */ |
| 474 | if (chip->lra_auto_mode && chip->play_mode == HAP_BUFFER) |
| 475 | return false; |
| 476 | |
| 477 | return true; |
| 478 | } |
| 479 | |
| 480 | #define HAPTICS_BACK_EMF_DELAY_US 20000 |
| 481 | static int qpnp_haptics_auto_res_enable(struct hap_chip *chip, bool enable) |
| 482 | { |
| 483 | int rc = 0; |
| 484 | u32 delay_us = HAPTICS_BACK_EMF_DELAY_US; |
| 485 | u8 val, auto_res_mode_qwd; |
| 486 | |
| 487 | if (chip->act_type != HAP_LRA) |
| 488 | return 0; |
| 489 | |
| 490 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) |
| 491 | auto_res_mode_qwd = (chip->ares_cfg.auto_res_mode == |
| 492 | HAP_PM660_AUTO_RES_QWD); |
| 493 | else |
| 494 | auto_res_mode_qwd = (chip->ares_cfg.auto_res_mode == |
| 495 | HAP_AUTO_RES_QWD); |
| 496 | |
| 497 | /* |
| 498 | * Do not enable auto resonance if auto mode is enabled and auto |
| 499 | * resonance mode is QWD, meaning short pattern. |
| 500 | */ |
| 501 | if (chip->lra_auto_mode && auto_res_mode_qwd && enable) { |
| 502 | pr_debug("auto_mode enabled, not enabling auto_res\n"); |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | /* |
| 507 | * For auto resonance detection to work properly, sufficient back-emf |
| 508 | * has to be generated. In general, back-emf takes some time to build |
| 509 | * up. When the auto resonance mode is chosen as QWD, high-z will be |
| 510 | * applied for every LRA cycle and hence there won't be enough back-emf |
| 511 | * at the start-up. Hence, the motor needs to vibrate for few LRA cycles |
| 512 | * after the PLAY bit is asserted. Enable the auto resonance after |
| 513 | * 'time_required_to_generate_back_emf_us' is completed. |
| 514 | */ |
| 515 | |
| 516 | if (auto_res_mode_qwd && enable) |
| 517 | usleep_range(delay_us, delay_us + 1); |
| 518 | |
| 519 | val = enable ? AUTO_RES_EN_BIT : 0; |
| 520 | |
| 521 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) |
| 522 | rc = qpnp_haptics_masked_write_reg(chip, |
| 523 | HAP_AUTO_RES_CTRL_REG(chip), |
| 524 | AUTO_RES_EN_BIT, val); |
| 525 | else |
| 526 | rc = qpnp_haptics_masked_write_reg(chip, HAP_TEST2_REG(chip), |
| 527 | AUTO_RES_EN_BIT, val); |
| 528 | if (rc < 0) |
| 529 | return rc; |
| 530 | |
| 531 | if (enable) |
| 532 | chip->status_flags |= AUTO_RESONANCE_ENABLED; |
| 533 | else |
| 534 | chip->status_flags &= ~AUTO_RESONANCE_ENABLED; |
| 535 | |
| 536 | pr_debug("auto_res %sabled\n", enable ? "en" : "dis"); |
| 537 | return rc; |
| 538 | } |
| 539 | |
| 540 | static int qpnp_haptics_update_rate_cfg(struct hap_chip *chip, u16 play_rate) |
| 541 | { |
| 542 | int rc; |
| 543 | u8 val[2]; |
| 544 | |
| 545 | if (chip->last_rate_cfg == play_rate) { |
| 546 | pr_debug("Same rate_cfg %x\n", play_rate); |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | val[0] = play_rate & HAP_RATE_CFG1_MASK; |
| 551 | val[1] = (play_rate >> HAP_RATE_CFG2_SHIFT) & HAP_RATE_CFG2_MASK; |
| 552 | rc = qpnp_haptics_write_reg(chip, HAP_RATE_CFG1_REG(chip), val, 2); |
| 553 | if (rc < 0) |
| 554 | return rc; |
| 555 | |
| 556 | pr_debug("Play rate code 0x%x\n", play_rate); |
| 557 | chip->last_rate_cfg = play_rate; |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | static void qpnp_haptics_update_lra_frequency(struct hap_chip *chip) |
| 562 | { |
| 563 | u8 lra_auto_res[2], val; |
| 564 | u32 play_rate_code; |
| 565 | u16 rate_cfg; |
| 566 | int rc; |
| 567 | |
| 568 | rc = qpnp_haptics_read_reg(chip, HAP_LRA_AUTO_RES_LO_REG(chip), |
| 569 | lra_auto_res, 2); |
| 570 | if (rc < 0) { |
| 571 | pr_err("Error in reading LRA_AUTO_RES_LO/HI, rc=%d\n", rc); |
| 572 | return; |
| 573 | } |
| 574 | |
| 575 | play_rate_code = |
| 576 | (lra_auto_res[1] & 0xF0) << 4 | (lra_auto_res[0] & 0xFF); |
| 577 | |
| 578 | pr_debug("lra_auto_res_lo = 0x%x lra_auto_res_hi = 0x%x play_rate_code = 0x%x\n", |
| 579 | lra_auto_res[0], lra_auto_res[1], play_rate_code); |
| 580 | |
| 581 | rc = qpnp_haptics_read_reg(chip, HAP_STATUS_1_REG(chip), &val, 1); |
| 582 | if (rc < 0) |
| 583 | return; |
| 584 | |
| 585 | /* |
| 586 | * If the drive period code read from AUTO_RES_LO and AUTO_RES_HI |
| 587 | * registers is more than the max limit percent variation or less |
| 588 | * than the min limit percent variation specified through DT, then |
| 589 | * auto-resonance is disabled. |
| 590 | */ |
| 591 | |
| 592 | if ((val & AUTO_RES_ERROR_BIT) || |
| 593 | ((play_rate_code <= chip->drive_period_code_min_limit) || |
| 594 | (play_rate_code >= chip->drive_period_code_max_limit))) { |
| 595 | if (val & AUTO_RES_ERROR_BIT) |
| 596 | pr_debug("Auto-resonance error %x\n", val); |
| 597 | else |
| 598 | pr_debug("play rate %x out of bounds [min: 0x%x, max: 0x%x]\n", |
| 599 | play_rate_code, |
| 600 | chip->drive_period_code_min_limit, |
| 601 | chip->drive_period_code_max_limit); |
| 602 | rc = qpnp_haptics_auto_res_enable(chip, false); |
| 603 | if (rc < 0) |
| 604 | pr_debug("Auto-resonance disable failed\n"); |
| 605 | return; |
| 606 | } |
| 607 | |
| 608 | /* |
| 609 | * bits[7:4] of AUTO_RES_HI should be written to bits[3:0] of RATE_CFG2 |
| 610 | */ |
| 611 | lra_auto_res[1] >>= 4; |
| 612 | rate_cfg = lra_auto_res[1] << 8 | lra_auto_res[0]; |
| 613 | rc = qpnp_haptics_update_rate_cfg(chip, rate_cfg); |
| 614 | if (rc < 0) |
| 615 | pr_debug("Error in updating rate_cfg\n"); |
| 616 | } |
| 617 | |
| 618 | #define MAX_RETRIES 5 |
| 619 | #define HAP_CYCLES 4 |
| 620 | static bool is_haptics_idle(struct hap_chip *chip) |
| 621 | { |
| 622 | unsigned long wait_time_us; |
| 623 | int rc, i; |
| 624 | u8 val; |
| 625 | |
| 626 | rc = qpnp_haptics_read_reg(chip, HAP_STATUS_1_REG(chip), &val, 1); |
| 627 | if (rc < 0) |
| 628 | return false; |
| 629 | |
| 630 | if (!(val & HAP_BUSY_BIT)) |
| 631 | return true; |
| 632 | |
| 633 | if (chip->play_time_ms <= 20) |
| 634 | wait_time_us = chip->play_time_ms * 1000; |
| 635 | else |
| 636 | wait_time_us = chip->wave_play_rate_us * HAP_CYCLES; |
| 637 | |
| 638 | for (i = 0; i < MAX_RETRIES; i++) { |
| 639 | /* wait for play_rate cycles */ |
| 640 | usleep_range(wait_time_us, wait_time_us + 1); |
| 641 | |
| 642 | if (chip->play_mode == HAP_DIRECT || |
| 643 | chip->play_mode == HAP_PWM) |
| 644 | return true; |
| 645 | |
| 646 | rc = qpnp_haptics_read_reg(chip, HAP_STATUS_1_REG(chip), &val, |
| 647 | 1); |
| 648 | if (rc < 0) |
| 649 | return false; |
| 650 | |
| 651 | if (!(val & HAP_BUSY_BIT)) |
| 652 | return true; |
| 653 | } |
| 654 | |
| 655 | if (i >= MAX_RETRIES && (val & HAP_BUSY_BIT)) { |
| 656 | pr_debug("Haptics Busy after %d retries\n", i); |
| 657 | return false; |
| 658 | } |
| 659 | |
| 660 | return true; |
| 661 | } |
| 662 | |
| 663 | static int qpnp_haptics_mod_enable(struct hap_chip *chip, bool enable) |
| 664 | { |
| 665 | u8 val; |
| 666 | int rc; |
| 667 | |
| 668 | if (chip->module_en == enable) |
| 669 | return 0; |
| 670 | |
| 671 | if (!enable) { |
| 672 | if (!is_haptics_idle(chip)) |
| 673 | pr_debug("Disabling module forcibly\n"); |
| 674 | } |
| 675 | |
| 676 | val = enable ? HAP_EN_BIT : 0; |
| 677 | rc = qpnp_haptics_write_reg(chip, HAP_EN_CTL_REG(chip), &val, 1); |
| 678 | if (rc < 0) |
| 679 | return rc; |
| 680 | |
| 681 | chip->module_en = enable; |
| 682 | return 0; |
| 683 | } |
| 684 | |
| 685 | static int qpnp_haptics_play_control(struct hap_chip *chip, |
| 686 | enum hap_play_control ctrl) |
| 687 | { |
| 688 | u8 val; |
| 689 | int rc; |
| 690 | |
| 691 | switch (ctrl) { |
| 692 | case HAP_STOP: |
| 693 | val = 0; |
| 694 | break; |
| 695 | case HAP_PAUSE: |
| 696 | val = PAUSE_BIT; |
| 697 | break; |
| 698 | case HAP_PLAY: |
| 699 | val = PLAY_BIT; |
| 700 | break; |
| 701 | default: |
| 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | rc = qpnp_haptics_write_reg(chip, HAP_PLAY_REG(chip), &val, 1); |
| 706 | if (rc < 0) { |
| 707 | pr_err("Error in writing to PLAY_REG, rc=%d\n", rc); |
| 708 | return rc; |
| 709 | } |
| 710 | |
| 711 | pr_debug("haptics play ctrl: %d\n", ctrl); |
| 712 | return rc; |
| 713 | } |
| 714 | |
| 715 | #define AUTO_RES_ERR_POLL_TIME_NS (20 * NSEC_PER_MSEC) |
| 716 | static int qpnp_haptics_play(struct hap_chip *chip, bool enable) |
| 717 | { |
| 718 | int rc = 0, time_ms = chip->play_time_ms; |
| 719 | |
| 720 | if (chip->perm_disable && enable) |
| 721 | return 0; |
| 722 | |
| 723 | mutex_lock(&chip->play_lock); |
| 724 | |
| 725 | if (enable) { |
| 726 | if (chip->play_mode == HAP_PWM) { |
| 727 | rc = pwm_enable(chip->pwm_data.pwm_dev); |
| 728 | if (rc < 0) { |
| 729 | pr_err("Error in enabling PWM, rc=%d\n", rc); |
| 730 | goto out; |
| 731 | } |
| 732 | } |
| 733 | |
| 734 | rc = qpnp_haptics_auto_res_enable(chip, false); |
| 735 | if (rc < 0) { |
| 736 | pr_err("Error in disabling auto_res, rc=%d\n", rc); |
| 737 | goto out; |
| 738 | } |
| 739 | |
| 740 | rc = qpnp_haptics_mod_enable(chip, true); |
| 741 | if (rc < 0) { |
| 742 | pr_err("Error in enabling module, rc=%d\n", rc); |
| 743 | goto out; |
| 744 | } |
| 745 | |
| 746 | rc = qpnp_haptics_play_control(chip, HAP_PLAY); |
| 747 | if (rc < 0) { |
| 748 | pr_err("Error in enabling play, rc=%d\n", rc); |
| 749 | goto out; |
| 750 | } |
| 751 | |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 752 | if (chip->play_mode == HAP_BUFFER) |
| 753 | time_ms = get_buffer_mode_duration(chip); |
| 754 | hrtimer_start(&chip->stop_timer, |
| 755 | ktime_set(time_ms / MSEC_PER_SEC, |
| 756 | (time_ms % MSEC_PER_SEC) * NSEC_PER_MSEC), |
| 757 | HRTIMER_MODE_REL); |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 758 | |
| 759 | rc = qpnp_haptics_auto_res_enable(chip, true); |
| 760 | if (rc < 0) { |
| 761 | pr_err("Error in enabling auto_res, rc=%d\n", rc); |
| 762 | goto out; |
| 763 | } |
| 764 | |
| 765 | if (is_sw_lra_auto_resonance_control(chip)) |
| 766 | hrtimer_start(&chip->auto_res_err_poll_timer, |
| 767 | ktime_set(0, AUTO_RES_ERR_POLL_TIME_NS), |
| 768 | HRTIMER_MODE_REL); |
| 769 | } else { |
| 770 | rc = qpnp_haptics_play_control(chip, HAP_STOP); |
| 771 | if (rc < 0) { |
| 772 | pr_err("Error in disabling play, rc=%d\n", rc); |
| 773 | goto out; |
| 774 | } |
| 775 | |
| 776 | if (is_sw_lra_auto_resonance_control(chip)) { |
| 777 | if (chip->status_flags & AUTO_RESONANCE_ENABLED) |
| 778 | qpnp_haptics_update_lra_frequency(chip); |
| 779 | hrtimer_cancel(&chip->auto_res_err_poll_timer); |
| 780 | } |
| 781 | |
| 782 | if (chip->play_mode == HAP_PWM) |
| 783 | pwm_disable(chip->pwm_data.pwm_dev); |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 784 | |
| 785 | if (chip->play_mode == HAP_BUFFER) |
| 786 | chip->wave_samp_idx = 0; |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | out: |
| 790 | mutex_unlock(&chip->play_lock); |
| 791 | return rc; |
| 792 | } |
| 793 | |
| 794 | static void qpnp_haptics_work(struct work_struct *work) |
| 795 | { |
| 796 | struct hap_chip *chip = container_of(work, struct hap_chip, |
| 797 | haptics_work); |
| 798 | int rc; |
| 799 | bool enable; |
| 800 | |
| 801 | enable = atomic_read(&chip->state); |
| 802 | pr_debug("state: %d\n", enable); |
| 803 | rc = qpnp_haptics_play(chip, enable); |
| 804 | if (rc < 0) |
| 805 | pr_err("Error in %sing haptics, rc=%d\n", |
| 806 | enable ? "play" : "stopp", rc); |
| 807 | } |
| 808 | |
| 809 | static enum hrtimer_restart hap_stop_timer(struct hrtimer *timer) |
| 810 | { |
| 811 | struct hap_chip *chip = container_of(timer, struct hap_chip, |
| 812 | stop_timer); |
| 813 | |
| 814 | atomic_set(&chip->state, 0); |
| 815 | schedule_work(&chip->haptics_work); |
| 816 | |
| 817 | return HRTIMER_NORESTART; |
| 818 | } |
| 819 | |
| 820 | static enum hrtimer_restart hap_auto_res_err_poll_timer(struct hrtimer *timer) |
| 821 | { |
| 822 | struct hap_chip *chip = container_of(timer, struct hap_chip, |
| 823 | auto_res_err_poll_timer); |
| 824 | |
| 825 | if (!(chip->status_flags & AUTO_RESONANCE_ENABLED)) |
| 826 | return HRTIMER_NORESTART; |
| 827 | |
| 828 | qpnp_haptics_update_lra_frequency(chip); |
| 829 | hrtimer_forward(&chip->auto_res_err_poll_timer, ktime_get(), |
| 830 | ktime_set(0, AUTO_RES_ERR_POLL_TIME_NS)); |
| 831 | |
| 832 | return HRTIMER_NORESTART; |
| 833 | } |
| 834 | |
| 835 | static int qpnp_haptics_suspend(struct device *dev) |
| 836 | { |
| 837 | struct hap_chip *chip = dev_get_drvdata(dev); |
| 838 | int rc; |
| 839 | |
| 840 | rc = qpnp_haptics_play(chip, false); |
| 841 | if (rc < 0) |
| 842 | pr_err("Error in stopping haptics, rc=%d\n", rc); |
| 843 | |
| 844 | rc = qpnp_haptics_mod_enable(chip, false); |
| 845 | if (rc < 0) |
| 846 | pr_err("Error in disabling module, rc=%d\n", rc); |
| 847 | |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int qpnp_haptics_wave_rep_config(struct hap_chip *chip, |
| 852 | enum hap_rep_type type) |
| 853 | { |
| 854 | int rc; |
| 855 | u8 val = 0, mask = 0; |
| 856 | |
| 857 | if (type & HAP_WAVE_REPEAT) { |
| 858 | if (chip->wave_rep_cnt < WF_REPEAT_MIN) |
| 859 | chip->wave_rep_cnt = WF_REPEAT_MIN; |
| 860 | else if (chip->wave_rep_cnt > WF_REPEAT_MAX) |
| 861 | chip->wave_rep_cnt = WF_REPEAT_MAX; |
| 862 | mask = WF_REPEAT_MASK; |
| 863 | val = ilog2(chip->wave_rep_cnt) << WF_REPEAT_SHIFT; |
| 864 | } |
| 865 | |
| 866 | if (type & HAP_WAVE_SAMP_REPEAT) { |
| 867 | if (chip->wave_s_rep_cnt < WF_S_REPEAT_MIN) |
| 868 | chip->wave_s_rep_cnt = WF_S_REPEAT_MIN; |
| 869 | else if (chip->wave_s_rep_cnt > WF_S_REPEAT_MAX) |
| 870 | chip->wave_s_rep_cnt = WF_S_REPEAT_MAX; |
| 871 | mask |= WF_S_REPEAT_MASK; |
| 872 | val |= ilog2(chip->wave_s_rep_cnt); |
| 873 | } |
| 874 | |
| 875 | rc = qpnp_haptics_masked_write_reg(chip, HAP_WF_REPEAT_REG(chip), |
| 876 | mask, val); |
| 877 | return rc; |
| 878 | } |
| 879 | |
| 880 | /* configuration api for buffer mode */ |
| 881 | static int qpnp_haptics_buffer_config(struct hap_chip *chip, u32 *wave_samp, |
| 882 | bool overdrive) |
| 883 | { |
| 884 | u8 buf[HAP_WAVE_SAMP_LEN]; |
| 885 | u32 *ptr; |
| 886 | int rc, i; |
| 887 | |
| 888 | if (wave_samp) { |
| 889 | ptr = wave_samp; |
| 890 | } else { |
| 891 | if (chip->wave_samp_idx >= ARRAY_SIZE(chip->wave_samp)) { |
| 892 | pr_err("Incorrect wave_samp_idx %d\n", |
| 893 | chip->wave_samp_idx); |
| 894 | return -EINVAL; |
| 895 | } |
| 896 | |
| 897 | ptr = &chip->wave_samp[chip->wave_samp_idx]; |
| 898 | } |
| 899 | |
| 900 | /* Don't set override bit in waveform sample for PM660 */ |
| 901 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) |
| 902 | overdrive = false; |
| 903 | |
| 904 | /* Configure WAVE_SAMPLE1 to WAVE_SAMPLE8 register */ |
| 905 | for (i = 0; i < HAP_WAVE_SAMP_LEN; i++) { |
| 906 | buf[i] = ptr[i]; |
| 907 | if (buf[i]) |
| 908 | buf[i] |= (overdrive ? HAP_WF_OVD_BIT : 0); |
| 909 | } |
| 910 | |
| 911 | rc = qpnp_haptics_write_reg(chip, HAP_WF_S1_REG(chip), buf, |
| 912 | HAP_WAVE_SAMP_LEN); |
| 913 | return rc; |
| 914 | } |
| 915 | |
| 916 | /* configuration api for pwm */ |
| 917 | static int qpnp_haptics_pwm_config(struct hap_chip *chip) |
| 918 | { |
| 919 | u8 val = 0; |
| 920 | int rc; |
| 921 | |
| 922 | if (chip->ext_pwm_freq_khz == 0) |
| 923 | return 0; |
| 924 | |
| 925 | /* Configure the EXTERNAL_PWM register */ |
| 926 | if (chip->ext_pwm_freq_khz <= EXT_PWM_FREQ_25_KHZ) { |
| 927 | chip->ext_pwm_freq_khz = EXT_PWM_FREQ_25_KHZ; |
| 928 | val = 0; |
| 929 | } else if (chip->ext_pwm_freq_khz <= EXT_PWM_FREQ_50_KHZ) { |
| 930 | chip->ext_pwm_freq_khz = EXT_PWM_FREQ_50_KHZ; |
| 931 | val = 1; |
| 932 | } else if (chip->ext_pwm_freq_khz <= EXT_PWM_FREQ_75_KHZ) { |
| 933 | chip->ext_pwm_freq_khz = EXT_PWM_FREQ_75_KHZ; |
| 934 | val = 2; |
| 935 | } else { |
| 936 | chip->ext_pwm_freq_khz = EXT_PWM_FREQ_100_KHZ; |
| 937 | val = 3; |
| 938 | } |
| 939 | |
| 940 | rc = qpnp_haptics_masked_write_reg(chip, HAP_EXT_PWM_REG(chip), |
| 941 | EXT_PWM_FREQ_SEL_MASK, val); |
| 942 | if (rc < 0) |
| 943 | return rc; |
| 944 | |
| 945 | if (chip->ext_pwm_dtest_line < 0 || |
| 946 | chip->ext_pwm_dtest_line > PWM_MAX_DTEST_LINES) { |
| 947 | pr_err("invalid dtest line\n"); |
| 948 | return -EINVAL; |
| 949 | } |
| 950 | |
| 951 | if (chip->ext_pwm_dtest_line > 0) { |
| 952 | /* disable auto res for PWM mode */ |
| 953 | val = chip->ext_pwm_dtest_line << HAP_EXT_PWM_DTEST_SHIFT; |
| 954 | rc = qpnp_haptics_masked_write_reg(chip, HAP_TEST2_REG(chip), |
| 955 | HAP_EXT_PWM_DTEST_MASK | AUTO_RES_EN_BIT, val); |
| 956 | if (rc < 0) |
| 957 | return rc; |
| 958 | } |
| 959 | |
| 960 | rc = pwm_config(chip->pwm_data.pwm_dev, |
| 961 | chip->pwm_data.duty_us * NSEC_PER_USEC, |
| 962 | chip->pwm_data.period_us * NSEC_PER_USEC); |
| 963 | if (rc < 0) { |
| 964 | pr_err("pwm_config failed, rc=%d\n", rc); |
| 965 | return rc; |
| 966 | } |
| 967 | |
| 968 | return 0; |
| 969 | } |
| 970 | |
| 971 | static int qpnp_haptics_lra_auto_res_config(struct hap_chip *chip, |
| 972 | struct hap_lra_ares_param *tmp_cfg) |
| 973 | { |
| 974 | struct hap_lra_ares_param *ares_cfg; |
| 975 | int rc; |
| 976 | u8 val = 0, mask = 0; |
| 977 | |
| 978 | /* disable auto resonance for ERM */ |
| 979 | if (chip->act_type == HAP_ERM) { |
| 980 | val = 0x00; |
| 981 | rc = qpnp_haptics_write_reg(chip, HAP_LRA_AUTO_RES_REG(chip), |
| 982 | &val, 1); |
| 983 | return rc; |
| 984 | } |
| 985 | |
| 986 | if (chip->auto_res_err_recovery_hw) { |
| 987 | rc = qpnp_haptics_masked_write_reg(chip, |
| 988 | HAP_AUTO_RES_CTRL_REG(chip), |
| 989 | AUTO_RES_ERR_RECOVERY_BIT, AUTO_RES_ERR_RECOVERY_BIT); |
| 990 | if (rc < 0) |
| 991 | return rc; |
| 992 | } |
| 993 | |
| 994 | if (tmp_cfg) |
| 995 | ares_cfg = tmp_cfg; |
| 996 | else |
| 997 | ares_cfg = &chip->ares_cfg; |
| 998 | |
| 999 | if (ares_cfg->lra_res_cal_period < HAP_RES_CAL_PERIOD_MIN) |
| 1000 | ares_cfg->lra_res_cal_period = HAP_RES_CAL_PERIOD_MIN; |
| 1001 | |
| 1002 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 1003 | if (ares_cfg->lra_res_cal_period > |
| 1004 | HAP_PM660_RES_CAL_PERIOD_MAX) |
| 1005 | ares_cfg->lra_res_cal_period = |
| 1006 | HAP_PM660_RES_CAL_PERIOD_MAX; |
| 1007 | |
| 1008 | if (ares_cfg->auto_res_mode == HAP_PM660_AUTO_RES_QWD) |
| 1009 | ares_cfg->lra_res_cal_period = 0; |
| 1010 | |
| 1011 | if (ares_cfg->lra_res_cal_period) |
| 1012 | val = ilog2(ares_cfg->lra_res_cal_period / |
| 1013 | HAP_RES_CAL_PERIOD_MIN) + 1; |
| 1014 | } else { |
| 1015 | if (ares_cfg->lra_res_cal_period > HAP_RES_CAL_PERIOD_MAX) |
| 1016 | ares_cfg->lra_res_cal_period = |
| 1017 | HAP_RES_CAL_PERIOD_MAX; |
| 1018 | |
| 1019 | if (ares_cfg->lra_res_cal_period) |
| 1020 | val = ilog2(ares_cfg->lra_res_cal_period / |
| 1021 | HAP_RES_CAL_PERIOD_MIN); |
| 1022 | } |
| 1023 | |
| 1024 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 1025 | val |= ares_cfg->auto_res_mode << PM660_AUTO_RES_MODE_SHIFT; |
| 1026 | mask = PM660_AUTO_RES_MODE_BIT; |
| 1027 | val |= ares_cfg->lra_high_z << PM660_CAL_DURATION_SHIFT; |
| 1028 | mask |= PM660_CAL_DURATION_MASK; |
| 1029 | if (ares_cfg->lra_qwd_drive_duration != -EINVAL) { |
| 1030 | val |= ares_cfg->lra_qwd_drive_duration << |
| 1031 | PM660_QWD_DRIVE_DURATION_SHIFT; |
| 1032 | mask |= PM660_QWD_DRIVE_DURATION_BIT; |
| 1033 | } |
| 1034 | if (ares_cfg->calibrate_at_eop != -EINVAL) { |
| 1035 | val |= ares_cfg->calibrate_at_eop << |
| 1036 | PM660_CAL_EOP_SHIFT; |
| 1037 | mask |= PM660_CAL_EOP_BIT; |
| 1038 | } |
| 1039 | mask |= PM660_LRA_RES_CAL_MASK; |
| 1040 | } else { |
| 1041 | val |= (ares_cfg->auto_res_mode << LRA_AUTO_RES_MODE_SHIFT); |
| 1042 | val |= (ares_cfg->lra_high_z << LRA_HIGH_Z_SHIFT); |
| 1043 | mask = LRA_AUTO_RES_MODE_MASK | LRA_HIGH_Z_MASK | |
| 1044 | LRA_RES_CAL_MASK; |
| 1045 | } |
| 1046 | |
| 1047 | pr_debug("mode: %d hi_z period: %d cal_period: %d\n", |
| 1048 | ares_cfg->auto_res_mode, ares_cfg->lra_high_z, |
| 1049 | ares_cfg->lra_res_cal_period); |
| 1050 | |
| 1051 | rc = qpnp_haptics_masked_write_reg(chip, HAP_LRA_AUTO_RES_REG(chip), |
| 1052 | mask, val); |
| 1053 | return rc; |
| 1054 | } |
| 1055 | |
| 1056 | /* configuration api for play mode */ |
| 1057 | static int qpnp_haptics_play_mode_config(struct hap_chip *chip) |
| 1058 | { |
| 1059 | u8 val = 0; |
| 1060 | int rc; |
| 1061 | |
| 1062 | if (!is_haptics_idle(chip)) |
| 1063 | return -EBUSY; |
| 1064 | |
| 1065 | val = chip->play_mode << HAP_WF_SOURCE_SHIFT; |
| 1066 | rc = qpnp_haptics_masked_write_reg(chip, HAP_SEL_REG(chip), |
| 1067 | HAP_WF_SOURCE_MASK, val); |
| 1068 | if (!rc) { |
| 1069 | if (chip->play_mode == HAP_BUFFER && !chip->play_irq_en) { |
| 1070 | enable_irq(chip->play_irq); |
| 1071 | chip->play_irq_en = true; |
| 1072 | } else if (chip->play_mode != HAP_BUFFER && chip->play_irq_en) { |
| 1073 | disable_irq(chip->play_irq); |
| 1074 | chip->play_irq_en = false; |
| 1075 | } |
| 1076 | } |
| 1077 | return rc; |
| 1078 | } |
| 1079 | |
| 1080 | /* configuration api for max voltage */ |
| 1081 | static int qpnp_haptics_vmax_config(struct hap_chip *chip, int vmax_mv, |
| 1082 | bool overdrive) |
| 1083 | { |
| 1084 | u8 val = 0; |
| 1085 | int rc; |
| 1086 | |
| 1087 | if (vmax_mv < 0) |
| 1088 | return -EINVAL; |
| 1089 | |
| 1090 | /* Allow setting override bit in VMAX_CFG only for PM660 */ |
| 1091 | if (chip->revid->pmic_subtype != PM660_SUBTYPE) |
| 1092 | overdrive = false; |
| 1093 | |
| 1094 | if (vmax_mv < HAP_VMAX_MIN_MV) |
| 1095 | vmax_mv = HAP_VMAX_MIN_MV; |
| 1096 | else if (vmax_mv > HAP_VMAX_MAX_MV) |
| 1097 | vmax_mv = HAP_VMAX_MAX_MV; |
| 1098 | |
| 1099 | val = DIV_ROUND_CLOSEST(vmax_mv, HAP_VMAX_MIN_MV); |
| 1100 | val <<= HAP_VMAX_SHIFT; |
| 1101 | if (overdrive) |
| 1102 | val |= HAP_VMAX_OVD_BIT; |
| 1103 | |
| 1104 | rc = qpnp_haptics_masked_write_reg(chip, HAP_VMAX_CFG_REG(chip), |
| 1105 | HAP_VMAX_MASK | HAP_VMAX_OVD_BIT, val); |
| 1106 | return rc; |
| 1107 | } |
| 1108 | |
| 1109 | /* configuration api for ilim */ |
| 1110 | static int qpnp_haptics_ilim_config(struct hap_chip *chip) |
| 1111 | { |
| 1112 | int rc; |
| 1113 | |
| 1114 | if (chip->ilim_ma < HAP_ILIM_400_MA) |
| 1115 | chip->ilim_ma = HAP_ILIM_400_MA; |
| 1116 | else if (chip->ilim_ma > HAP_ILIM_800_MA) |
| 1117 | chip->ilim_ma = HAP_ILIM_800_MA; |
| 1118 | |
| 1119 | rc = qpnp_haptics_masked_write_reg(chip, HAP_ILIM_CFG_REG(chip), |
| 1120 | HAP_ILIM_SEL_MASK, chip->ilim_ma); |
| 1121 | return rc; |
| 1122 | } |
| 1123 | |
| 1124 | /* configuration api for short circuit debounce */ |
| 1125 | static int qpnp_haptics_sc_deb_config(struct hap_chip *chip) |
| 1126 | { |
| 1127 | u8 val = 0; |
| 1128 | int rc; |
| 1129 | |
| 1130 | if (chip->sc_deb_cycles < HAP_SC_DEB_CYCLES_MIN) |
| 1131 | chip->sc_deb_cycles = HAP_SC_DEB_CYCLES_MIN; |
| 1132 | else if (chip->sc_deb_cycles > HAP_SC_DEB_CYCLES_MAX) |
| 1133 | chip->sc_deb_cycles = HAP_SC_DEB_CYCLES_MAX; |
| 1134 | |
| 1135 | if (chip->sc_deb_cycles != HAP_SC_DEB_CYCLES_MIN) |
| 1136 | val = ilog2(chip->sc_deb_cycles / |
| 1137 | HAP_DEF_SC_DEB_CYCLES) + 1; |
| 1138 | else |
| 1139 | val = HAP_SC_DEB_CYCLES_MIN; |
| 1140 | |
| 1141 | rc = qpnp_haptics_masked_write_reg(chip, HAP_SC_DEB_REG(chip), |
| 1142 | HAP_SC_DEB_MASK, val); |
| 1143 | |
| 1144 | return rc; |
| 1145 | } |
| 1146 | |
| 1147 | static int qpnp_haptics_brake_config(struct hap_chip *chip, u32 *brake_pat) |
| 1148 | { |
| 1149 | int rc, i; |
| 1150 | u32 temp, *ptr; |
| 1151 | u8 val; |
| 1152 | |
| 1153 | /* Configure BRAKE register */ |
| 1154 | rc = qpnp_haptics_masked_write_reg(chip, HAP_EN_CTL2_REG(chip), |
| 1155 | BRAKE_EN_BIT, (u8)chip->en_brake); |
| 1156 | if (rc < 0) |
| 1157 | return rc; |
| 1158 | |
| 1159 | /* If braking is not enabled, skip configuring brake pattern */ |
| 1160 | if (!chip->en_brake) |
| 1161 | return 0; |
| 1162 | |
| 1163 | if (!brake_pat) |
| 1164 | ptr = chip->brake_pat; |
| 1165 | else |
| 1166 | ptr = brake_pat; |
| 1167 | |
| 1168 | for (i = HAP_BRAKE_PAT_LEN - 1, val = 0; i >= 0; i--) { |
| 1169 | ptr[i] &= HAP_BRAKE_PAT_MASK; |
| 1170 | temp = i << 1; |
| 1171 | val |= ptr[i] << temp; |
| 1172 | } |
| 1173 | |
| 1174 | rc = qpnp_haptics_write_reg(chip, HAP_BRAKE_REG(chip), &val, 1); |
| 1175 | if (rc < 0) |
| 1176 | return rc; |
| 1177 | |
| 1178 | return 0; |
| 1179 | } |
| 1180 | |
| 1181 | static int qpnp_haptics_auto_mode_config(struct hap_chip *chip, int time_ms) |
| 1182 | { |
| 1183 | struct hap_lra_ares_param ares_cfg; |
| 1184 | enum hap_mode old_play_mode; |
| 1185 | u8 old_ares_mode; |
| 1186 | u32 brake_pat[HAP_BRAKE_PAT_LEN] = {0}; |
| 1187 | u32 wave_samp[HAP_WAVE_SAMP_LEN] = {0}; |
| 1188 | int rc, vmax_mv; |
| 1189 | |
| 1190 | if (!chip->lra_auto_mode) |
| 1191 | return false; |
| 1192 | |
| 1193 | /* For now, this is for LRA only */ |
| 1194 | if (chip->act_type == HAP_ERM) |
| 1195 | return 0; |
| 1196 | |
| 1197 | old_ares_mode = chip->ares_cfg.auto_res_mode; |
| 1198 | old_play_mode = chip->play_mode; |
| 1199 | pr_debug("auto_mode, time_ms: %d\n", time_ms); |
| 1200 | if (time_ms <= 20) { |
| 1201 | wave_samp[0] = HAP_WF_SAMP_MAX; |
| 1202 | wave_samp[1] = HAP_WF_SAMP_MAX; |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1203 | chip->wf_samp_len = 2; |
| 1204 | if (time_ms > 15) { |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1205 | wave_samp[2] = HAP_WF_SAMP_MAX; |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1206 | chip->wf_samp_len = 3; |
| 1207 | } |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1208 | |
| 1209 | /* short pattern */ |
| 1210 | rc = qpnp_haptics_parse_buffer_dt(chip); |
| 1211 | if (!rc) { |
| 1212 | rc = qpnp_haptics_wave_rep_config(chip, |
| 1213 | HAP_WAVE_REPEAT | HAP_WAVE_SAMP_REPEAT); |
| 1214 | if (rc < 0) { |
| 1215 | pr_err("Error in configuring wave_rep config %d\n", |
| 1216 | rc); |
| 1217 | return rc; |
| 1218 | } |
| 1219 | |
| 1220 | rc = qpnp_haptics_buffer_config(chip, wave_samp, true); |
| 1221 | if (rc < 0) { |
| 1222 | pr_err("Error in configuring buffer mode %d\n", |
| 1223 | rc); |
| 1224 | return rc; |
| 1225 | } |
| 1226 | } |
| 1227 | |
| 1228 | ares_cfg.lra_high_z = HAP_LRA_HIGH_Z_OPT1; |
| 1229 | ares_cfg.lra_res_cal_period = HAP_RES_CAL_PERIOD_MIN; |
| 1230 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 1231 | ares_cfg.auto_res_mode = HAP_PM660_AUTO_RES_QWD; |
| 1232 | ares_cfg.lra_qwd_drive_duration = 0; |
| 1233 | ares_cfg.calibrate_at_eop = 0; |
| 1234 | } else { |
| 1235 | ares_cfg.auto_res_mode = HAP_AUTO_RES_QWD; |
| 1236 | ares_cfg.lra_qwd_drive_duration = -EINVAL; |
| 1237 | ares_cfg.calibrate_at_eop = -EINVAL; |
| 1238 | } |
| 1239 | |
| 1240 | vmax_mv = HAP_VMAX_MAX_MV; |
| 1241 | rc = qpnp_haptics_vmax_config(chip, vmax_mv, true); |
| 1242 | if (rc < 0) |
| 1243 | return rc; |
| 1244 | |
| 1245 | rc = qpnp_haptics_brake_config(chip, brake_pat); |
| 1246 | if (rc < 0) |
| 1247 | return rc; |
| 1248 | |
| 1249 | /* enable play_irq for buffer mode */ |
| 1250 | if (chip->play_irq >= 0 && !chip->play_irq_en) { |
| 1251 | enable_irq(chip->play_irq); |
| 1252 | chip->play_irq_en = true; |
| 1253 | } |
| 1254 | |
| 1255 | chip->play_mode = HAP_BUFFER; |
| 1256 | chip->wave_shape = HAP_WAVE_SQUARE; |
| 1257 | } else { |
| 1258 | /* long pattern */ |
| 1259 | ares_cfg.lra_high_z = HAP_LRA_HIGH_Z_OPT1; |
| 1260 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 1261 | ares_cfg.auto_res_mode = HAP_PM660_AUTO_RES_ZXD; |
| 1262 | ares_cfg.lra_res_cal_period = |
| 1263 | HAP_PM660_RES_CAL_PERIOD_MAX; |
| 1264 | ares_cfg.lra_qwd_drive_duration = 0; |
| 1265 | ares_cfg.calibrate_at_eop = 1; |
| 1266 | } else { |
| 1267 | ares_cfg.auto_res_mode = HAP_AUTO_RES_ZXD_EOP; |
| 1268 | ares_cfg.lra_res_cal_period = HAP_RES_CAL_PERIOD_MAX; |
| 1269 | ares_cfg.lra_qwd_drive_duration = -EINVAL; |
| 1270 | ares_cfg.calibrate_at_eop = -EINVAL; |
| 1271 | } |
| 1272 | |
| 1273 | vmax_mv = chip->vmax_mv; |
| 1274 | rc = qpnp_haptics_vmax_config(chip, vmax_mv, false); |
| 1275 | if (rc < 0) |
| 1276 | return rc; |
| 1277 | |
| 1278 | brake_pat[0] = 0x3; |
| 1279 | rc = qpnp_haptics_brake_config(chip, brake_pat); |
| 1280 | if (rc < 0) |
| 1281 | return rc; |
| 1282 | |
| 1283 | /* enable play_irq for direct mode */ |
| 1284 | if (chip->play_irq >= 0 && chip->play_irq_en) { |
| 1285 | disable_irq(chip->play_irq); |
| 1286 | chip->play_irq_en = false; |
| 1287 | } |
| 1288 | |
| 1289 | chip->play_mode = HAP_DIRECT; |
| 1290 | chip->wave_shape = HAP_WAVE_SINE; |
| 1291 | } |
| 1292 | |
| 1293 | chip->ares_cfg.auto_res_mode = ares_cfg.auto_res_mode; |
| 1294 | rc = qpnp_haptics_lra_auto_res_config(chip, &ares_cfg); |
| 1295 | if (rc < 0) { |
| 1296 | chip->ares_cfg.auto_res_mode = old_ares_mode; |
| 1297 | return rc; |
| 1298 | } |
| 1299 | |
| 1300 | rc = qpnp_haptics_play_mode_config(chip); |
| 1301 | if (rc < 0) { |
| 1302 | chip->play_mode = old_play_mode; |
| 1303 | return rc; |
| 1304 | } |
| 1305 | |
| 1306 | rc = qpnp_haptics_masked_write_reg(chip, HAP_CFG2_REG(chip), |
| 1307 | HAP_LRA_RES_TYPE_MASK, chip->wave_shape); |
| 1308 | if (rc < 0) |
| 1309 | return rc; |
| 1310 | |
| 1311 | return 0; |
| 1312 | } |
| 1313 | |
| 1314 | static irqreturn_t qpnp_haptics_play_irq_handler(int irq, void *data) |
| 1315 | { |
| 1316 | struct hap_chip *chip = data; |
| 1317 | int rc; |
| 1318 | |
| 1319 | if (chip->play_mode != HAP_BUFFER) |
| 1320 | goto irq_handled; |
| 1321 | |
| 1322 | if (chip->wave_samp[chip->wave_samp_idx + HAP_WAVE_SAMP_LEN] > 0) { |
| 1323 | chip->wave_samp_idx += HAP_WAVE_SAMP_LEN; |
| 1324 | if (chip->wave_samp_idx >= ARRAY_SIZE(chip->wave_samp)) { |
| 1325 | pr_debug("Samples over\n"); |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1326 | } else { |
| 1327 | pr_debug("moving to next sample set %d\n", |
| 1328 | chip->wave_samp_idx); |
| 1329 | |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1330 | /* Moving to next set of wave sample */ |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1331 | rc = qpnp_haptics_buffer_config(chip, NULL, false); |
| 1332 | if (rc < 0) { |
| 1333 | pr_err("Error in configuring buffer, rc=%d\n", |
| 1334 | rc); |
| 1335 | goto irq_handled; |
| 1336 | } |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1337 | } |
| 1338 | } |
| 1339 | |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1340 | irq_handled: |
| 1341 | return IRQ_HANDLED; |
| 1342 | } |
| 1343 | |
| 1344 | #define SC_MAX_COUNT 5 |
| 1345 | #define SC_COUNT_RST_DELAY_US 1000000 |
| 1346 | static irqreturn_t qpnp_haptics_sc_irq_handler(int irq, void *data) |
| 1347 | { |
| 1348 | struct hap_chip *chip = data; |
| 1349 | int rc; |
| 1350 | u8 val; |
| 1351 | s64 sc_delta_time_us; |
| 1352 | ktime_t temp; |
| 1353 | |
| 1354 | rc = qpnp_haptics_read_reg(chip, HAP_STATUS_1_REG(chip), &val, 1); |
| 1355 | if (rc < 0) |
| 1356 | goto irq_handled; |
| 1357 | |
| 1358 | if (!(val & SC_FLAG_BIT)) { |
| 1359 | chip->sc_count = 0; |
| 1360 | goto irq_handled; |
| 1361 | } |
| 1362 | |
| 1363 | pr_debug("SC irq fired\n"); |
| 1364 | temp = ktime_get(); |
| 1365 | sc_delta_time_us = ktime_us_delta(temp, chip->last_sc_time); |
| 1366 | chip->last_sc_time = temp; |
| 1367 | |
| 1368 | if (sc_delta_time_us > SC_COUNT_RST_DELAY_US) |
| 1369 | chip->sc_count = 0; |
| 1370 | else |
| 1371 | chip->sc_count++; |
| 1372 | |
| 1373 | val = SC_CLR_BIT; |
| 1374 | rc = qpnp_haptics_write_reg(chip, HAP_SC_CLR_REG(chip), &val, 1); |
| 1375 | if (rc < 0) { |
| 1376 | pr_err("Error in writing to SC_CLR_REG, rc=%d\n", rc); |
| 1377 | goto irq_handled; |
| 1378 | } |
| 1379 | |
| 1380 | /* Permanently disable module if SC condition persists */ |
| 1381 | if (chip->sc_count > SC_MAX_COUNT) { |
| 1382 | pr_crit("SC persists, permanently disabling haptics\n"); |
| 1383 | rc = qpnp_haptics_mod_enable(chip, false); |
| 1384 | if (rc < 0) { |
| 1385 | pr_err("Error in disabling module, rc=%d\n", rc); |
| 1386 | goto irq_handled; |
| 1387 | } |
| 1388 | chip->perm_disable = true; |
| 1389 | } |
| 1390 | |
| 1391 | irq_handled: |
| 1392 | return IRQ_HANDLED; |
| 1393 | } |
| 1394 | |
| 1395 | /* All sysfs show/store functions below */ |
| 1396 | |
| 1397 | #define HAP_STR_SIZE 128 |
| 1398 | static int parse_string(const char *in_buf, char *out_buf) |
| 1399 | { |
| 1400 | int i; |
| 1401 | |
| 1402 | if (snprintf(out_buf, HAP_STR_SIZE, "%s", in_buf) > HAP_STR_SIZE) |
| 1403 | return -EINVAL; |
| 1404 | |
| 1405 | for (i = 0; i < strlen(out_buf); i++) { |
| 1406 | if (out_buf[i] == ' ' || out_buf[i] == '\n' || |
| 1407 | out_buf[i] == '\t') { |
| 1408 | out_buf[i] = '\0'; |
| 1409 | break; |
| 1410 | } |
| 1411 | } |
| 1412 | |
| 1413 | return 0; |
| 1414 | } |
| 1415 | |
| 1416 | static ssize_t qpnp_haptics_show_state(struct device *dev, |
| 1417 | struct device_attribute *attr, char *buf) |
| 1418 | { |
| 1419 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1420 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1421 | |
| 1422 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->module_en); |
| 1423 | } |
| 1424 | |
| 1425 | static ssize_t qpnp_haptics_store_state(struct device *dev, |
| 1426 | struct device_attribute *attr, const char *buf, size_t count) |
| 1427 | { |
| 1428 | |
| 1429 | /* At present, nothing to do with setting state */ |
| 1430 | return count; |
| 1431 | } |
| 1432 | |
| 1433 | static ssize_t qpnp_haptics_show_duration(struct device *dev, |
| 1434 | struct device_attribute *attr, char *buf) |
| 1435 | { |
| 1436 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1437 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1438 | ktime_t time_rem; |
| 1439 | s64 time_us = 0; |
| 1440 | |
| 1441 | if (hrtimer_active(&chip->stop_timer)) { |
| 1442 | time_rem = hrtimer_get_remaining(&chip->stop_timer); |
| 1443 | time_us = ktime_to_us(time_rem); |
| 1444 | } |
| 1445 | |
Tirupathi Reddy | 8f0b419 | 2018-01-11 15:34:54 +0530 | [diff] [blame] | 1446 | return snprintf(buf, PAGE_SIZE, "%lld\n", div_s64(time_us, 1000)); |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1447 | } |
| 1448 | |
| 1449 | static ssize_t qpnp_haptics_store_duration(struct device *dev, |
| 1450 | struct device_attribute *attr, const char *buf, size_t count) |
| 1451 | { |
| 1452 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1453 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1454 | u32 val; |
| 1455 | int rc; |
| 1456 | |
| 1457 | rc = kstrtouint(buf, 0, &val); |
| 1458 | if (rc < 0) |
| 1459 | return rc; |
| 1460 | |
| 1461 | /* setting 0 on duration is NOP for now */ |
| 1462 | if (val <= 0) |
| 1463 | return count; |
| 1464 | |
| 1465 | if (val > chip->max_play_time_ms) |
| 1466 | return -EINVAL; |
| 1467 | |
| 1468 | mutex_lock(&chip->param_lock); |
| 1469 | rc = qpnp_haptics_auto_mode_config(chip, val); |
| 1470 | if (rc < 0) { |
| 1471 | pr_err("Unable to do auto mode config\n"); |
| 1472 | mutex_unlock(&chip->param_lock); |
| 1473 | return rc; |
| 1474 | } |
| 1475 | |
| 1476 | chip->play_time_ms = val; |
| 1477 | mutex_unlock(&chip->param_lock); |
| 1478 | |
| 1479 | return count; |
| 1480 | } |
| 1481 | |
| 1482 | static ssize_t qpnp_haptics_show_activate(struct device *dev, |
| 1483 | struct device_attribute *attr, char *buf) |
| 1484 | { |
| 1485 | /* For now nothing to show */ |
| 1486 | return snprintf(buf, PAGE_SIZE, "%d\n", 0); |
| 1487 | } |
| 1488 | |
| 1489 | static ssize_t qpnp_haptics_store_activate(struct device *dev, |
| 1490 | struct device_attribute *attr, const char *buf, size_t count) |
| 1491 | { |
| 1492 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1493 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1494 | u32 val; |
| 1495 | int rc; |
| 1496 | |
| 1497 | rc = kstrtouint(buf, 0, &val); |
| 1498 | if (rc < 0) |
| 1499 | return rc; |
| 1500 | |
| 1501 | if (val != 0 && val != 1) |
| 1502 | return count; |
| 1503 | |
| 1504 | if (val) { |
| 1505 | hrtimer_cancel(&chip->stop_timer); |
| 1506 | if (is_sw_lra_auto_resonance_control(chip)) |
| 1507 | hrtimer_cancel(&chip->auto_res_err_poll_timer); |
| 1508 | cancel_work_sync(&chip->haptics_work); |
| 1509 | |
| 1510 | atomic_set(&chip->state, 1); |
| 1511 | schedule_work(&chip->haptics_work); |
| 1512 | } else { |
| 1513 | rc = qpnp_haptics_mod_enable(chip, false); |
| 1514 | if (rc < 0) { |
| 1515 | pr_err("Error in disabling module, rc=%d\n", rc); |
| 1516 | return rc; |
| 1517 | } |
| 1518 | } |
| 1519 | |
| 1520 | return count; |
| 1521 | } |
| 1522 | |
| 1523 | static ssize_t qpnp_haptics_show_play_mode(struct device *dev, |
| 1524 | struct device_attribute *attr, char *buf) |
| 1525 | { |
| 1526 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1527 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1528 | char *str; |
| 1529 | |
| 1530 | if (chip->play_mode == HAP_BUFFER) |
| 1531 | str = "buffer"; |
| 1532 | else if (chip->play_mode == HAP_DIRECT) |
| 1533 | str = "direct"; |
| 1534 | else if (chip->play_mode == HAP_AUDIO) |
| 1535 | str = "audio"; |
| 1536 | else if (chip->play_mode == HAP_PWM) |
| 1537 | str = "pwm"; |
| 1538 | else |
| 1539 | return -EINVAL; |
| 1540 | |
| 1541 | return snprintf(buf, PAGE_SIZE, "%s\n", str); |
| 1542 | } |
| 1543 | |
| 1544 | static ssize_t qpnp_haptics_store_play_mode(struct device *dev, |
| 1545 | struct device_attribute *attr, const char *buf, size_t count) |
| 1546 | { |
| 1547 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1548 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1549 | char str[HAP_STR_SIZE + 1]; |
| 1550 | int rc = 0, temp, old_mode; |
| 1551 | |
| 1552 | rc = parse_string(buf, str); |
| 1553 | if (rc < 0) |
| 1554 | return rc; |
| 1555 | |
| 1556 | if (strcmp(str, "buffer") == 0) |
| 1557 | temp = HAP_BUFFER; |
| 1558 | else if (strcmp(str, "direct") == 0) |
| 1559 | temp = HAP_DIRECT; |
| 1560 | else if (strcmp(str, "audio") == 0) |
| 1561 | temp = HAP_AUDIO; |
| 1562 | else if (strcmp(str, "pwm") == 0) |
| 1563 | temp = HAP_PWM; |
| 1564 | else |
| 1565 | return -EINVAL; |
| 1566 | |
| 1567 | if (temp == chip->play_mode) |
| 1568 | return count; |
| 1569 | |
| 1570 | if (temp == HAP_BUFFER) { |
| 1571 | rc = qpnp_haptics_parse_buffer_dt(chip); |
| 1572 | if (!rc) { |
| 1573 | rc = qpnp_haptics_wave_rep_config(chip, |
| 1574 | HAP_WAVE_REPEAT | HAP_WAVE_SAMP_REPEAT); |
| 1575 | if (rc < 0) { |
| 1576 | pr_err("Error in configuring wave_rep config %d\n", |
| 1577 | rc); |
| 1578 | return rc; |
| 1579 | } |
| 1580 | } |
| 1581 | |
| 1582 | rc = qpnp_haptics_buffer_config(chip, NULL, true); |
| 1583 | } else if (temp == HAP_PWM) { |
| 1584 | rc = qpnp_haptics_parse_pwm_dt(chip); |
| 1585 | if (!rc) |
| 1586 | rc = qpnp_haptics_pwm_config(chip); |
| 1587 | } |
| 1588 | |
| 1589 | if (rc < 0) |
| 1590 | return rc; |
| 1591 | |
| 1592 | rc = qpnp_haptics_mod_enable(chip, false); |
| 1593 | if (rc < 0) |
| 1594 | return rc; |
| 1595 | |
| 1596 | old_mode = chip->play_mode; |
| 1597 | chip->play_mode = temp; |
| 1598 | rc = qpnp_haptics_play_mode_config(chip); |
| 1599 | if (rc < 0) { |
| 1600 | chip->play_mode = old_mode; |
| 1601 | return rc; |
| 1602 | } |
| 1603 | |
| 1604 | if (chip->play_mode == HAP_AUDIO) { |
| 1605 | rc = qpnp_haptics_mod_enable(chip, true); |
| 1606 | if (rc < 0) { |
| 1607 | chip->play_mode = old_mode; |
| 1608 | return rc; |
| 1609 | } |
| 1610 | } |
| 1611 | |
| 1612 | return count; |
| 1613 | } |
| 1614 | |
| 1615 | static ssize_t qpnp_haptics_show_wf_samp(struct device *dev, |
| 1616 | struct device_attribute *attr, char *buf) |
| 1617 | { |
| 1618 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1619 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1620 | char str[HAP_STR_SIZE + 1]; |
| 1621 | char *ptr = str; |
| 1622 | int i, len = 0; |
| 1623 | |
| 1624 | for (i = 0; i < ARRAY_SIZE(chip->wave_samp); i++) { |
| 1625 | len = scnprintf(ptr, HAP_STR_SIZE, "%x ", chip->wave_samp[i]); |
| 1626 | ptr += len; |
| 1627 | } |
| 1628 | ptr[len] = '\0'; |
| 1629 | |
| 1630 | return snprintf(buf, PAGE_SIZE, "%s\n", str); |
| 1631 | } |
| 1632 | |
| 1633 | static ssize_t qpnp_haptics_store_wf_samp(struct device *dev, |
| 1634 | struct device_attribute *attr, const char *buf, size_t count) |
| 1635 | { |
| 1636 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1637 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1638 | u8 samp[HAP_WAVE_SAMP_SET_LEN] = {0}; |
| 1639 | int bytes_read, rc; |
| 1640 | unsigned int data, pos = 0, i = 0; |
| 1641 | |
| 1642 | while (pos < count && i < ARRAY_SIZE(samp) && |
| 1643 | sscanf(buf + pos, "%x%n", &data, &bytes_read) == 1) { |
| 1644 | /* bit 0 is not used in WF_Sx */ |
| 1645 | samp[i++] = data & GENMASK(7, 1); |
| 1646 | pos += bytes_read; |
| 1647 | } |
| 1648 | |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1649 | chip->wf_samp_len = i; |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 1650 | for (i = 0; i < ARRAY_SIZE(chip->wave_samp); i++) |
| 1651 | chip->wave_samp[i] = samp[i]; |
| 1652 | |
| 1653 | rc = qpnp_haptics_buffer_config(chip, NULL, false); |
| 1654 | if (rc < 0) { |
| 1655 | pr_err("Error in configuring buffer mode %d\n", rc); |
| 1656 | return rc; |
| 1657 | } |
| 1658 | |
| 1659 | return count; |
| 1660 | } |
| 1661 | |
| 1662 | static ssize_t qpnp_haptics_show_wf_rep_count(struct device *dev, |
| 1663 | struct device_attribute *attr, char *buf) |
| 1664 | { |
| 1665 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1666 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1667 | |
| 1668 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->wave_rep_cnt); |
| 1669 | } |
| 1670 | |
| 1671 | static ssize_t qpnp_haptics_store_wf_rep_count(struct device *dev, |
| 1672 | struct device_attribute *attr, const char *buf, size_t count) |
| 1673 | { |
| 1674 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1675 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1676 | int data, rc, old_wave_rep_cnt; |
| 1677 | |
| 1678 | rc = kstrtoint(buf, 10, &data); |
| 1679 | if (rc < 0) |
| 1680 | return rc; |
| 1681 | |
| 1682 | old_wave_rep_cnt = chip->wave_rep_cnt; |
| 1683 | chip->wave_rep_cnt = data; |
| 1684 | rc = qpnp_haptics_wave_rep_config(chip, HAP_WAVE_REPEAT); |
| 1685 | if (rc < 0) { |
| 1686 | chip->wave_rep_cnt = old_wave_rep_cnt; |
| 1687 | return rc; |
| 1688 | } |
| 1689 | |
| 1690 | return count; |
| 1691 | } |
| 1692 | |
| 1693 | static ssize_t qpnp_haptics_show_wf_s_rep_count(struct device *dev, |
| 1694 | struct device_attribute *attr, char *buf) |
| 1695 | { |
| 1696 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1697 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1698 | |
| 1699 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->wave_s_rep_cnt); |
| 1700 | } |
| 1701 | |
| 1702 | static ssize_t qpnp_haptics_store_wf_s_rep_count(struct device *dev, |
| 1703 | struct device_attribute *attr, const char *buf, size_t count) |
| 1704 | { |
| 1705 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1706 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1707 | int data, rc, old_wave_s_rep_cnt; |
| 1708 | |
| 1709 | rc = kstrtoint(buf, 10, &data); |
| 1710 | if (rc < 0) |
| 1711 | return rc; |
| 1712 | |
| 1713 | old_wave_s_rep_cnt = chip->wave_s_rep_cnt; |
| 1714 | chip->wave_s_rep_cnt = data; |
| 1715 | rc = qpnp_haptics_wave_rep_config(chip, HAP_WAVE_SAMP_REPEAT); |
| 1716 | if (rc < 0) { |
| 1717 | chip->wave_s_rep_cnt = old_wave_s_rep_cnt; |
| 1718 | return rc; |
| 1719 | } |
| 1720 | |
| 1721 | return count; |
| 1722 | } |
| 1723 | |
| 1724 | static ssize_t qpnp_haptics_show_vmax(struct device *dev, |
| 1725 | struct device_attribute *attr, char *buf) |
| 1726 | { |
| 1727 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1728 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1729 | |
| 1730 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->vmax_mv); |
| 1731 | } |
| 1732 | |
| 1733 | static ssize_t qpnp_haptics_store_vmax(struct device *dev, |
| 1734 | struct device_attribute *attr, const char *buf, size_t count) |
| 1735 | { |
| 1736 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1737 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1738 | int data, rc, old_vmax_mv; |
| 1739 | |
| 1740 | rc = kstrtoint(buf, 10, &data); |
| 1741 | if (rc < 0) |
| 1742 | return rc; |
| 1743 | |
| 1744 | old_vmax_mv = chip->vmax_mv; |
| 1745 | chip->vmax_mv = data; |
| 1746 | rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv, false); |
| 1747 | if (rc < 0) { |
| 1748 | chip->vmax_mv = old_vmax_mv; |
| 1749 | return rc; |
| 1750 | } |
| 1751 | |
| 1752 | return count; |
| 1753 | } |
| 1754 | |
| 1755 | static ssize_t qpnp_haptics_show_lra_auto_mode(struct device *dev, |
| 1756 | struct device_attribute *attr, char *buf) |
| 1757 | { |
| 1758 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1759 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1760 | |
| 1761 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->lra_auto_mode); |
| 1762 | } |
| 1763 | |
| 1764 | static ssize_t qpnp_haptics_store_lra_auto_mode(struct device *dev, |
| 1765 | struct device_attribute *attr, const char *buf, size_t count) |
| 1766 | { |
| 1767 | struct led_classdev *cdev = dev_get_drvdata(dev); |
| 1768 | struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); |
| 1769 | int rc, data; |
| 1770 | |
| 1771 | rc = kstrtoint(buf, 10, &data); |
| 1772 | if (rc < 0) |
| 1773 | return rc; |
| 1774 | |
| 1775 | if (data != 0 && data != 1) |
| 1776 | return count; |
| 1777 | |
| 1778 | chip->lra_auto_mode = !!data; |
| 1779 | return count; |
| 1780 | } |
| 1781 | |
| 1782 | static struct device_attribute qpnp_haptics_attrs[] = { |
| 1783 | __ATTR(state, 0664, qpnp_haptics_show_state, qpnp_haptics_store_state), |
| 1784 | __ATTR(duration, 0664, qpnp_haptics_show_duration, |
| 1785 | qpnp_haptics_store_duration), |
| 1786 | __ATTR(activate, 0664, qpnp_haptics_show_activate, |
| 1787 | qpnp_haptics_store_activate), |
| 1788 | __ATTR(play_mode, 0664, qpnp_haptics_show_play_mode, |
| 1789 | qpnp_haptics_store_play_mode), |
| 1790 | __ATTR(wf_samp, 0664, qpnp_haptics_show_wf_samp, |
| 1791 | qpnp_haptics_store_wf_samp), |
| 1792 | __ATTR(wf_rep_count, 0664, qpnp_haptics_show_wf_rep_count, |
| 1793 | qpnp_haptics_store_wf_rep_count), |
| 1794 | __ATTR(wf_s_rep_count, 0664, qpnp_haptics_show_wf_s_rep_count, |
| 1795 | qpnp_haptics_store_wf_s_rep_count), |
| 1796 | __ATTR(vmax_mv, 0664, qpnp_haptics_show_vmax, qpnp_haptics_store_vmax), |
| 1797 | __ATTR(lra_auto_mode, 0664, qpnp_haptics_show_lra_auto_mode, |
| 1798 | qpnp_haptics_store_lra_auto_mode), |
| 1799 | }; |
| 1800 | |
| 1801 | /* Dummy functions for brightness */ |
| 1802 | static |
| 1803 | enum led_brightness qpnp_haptics_brightness_get(struct led_classdev *cdev) |
| 1804 | { |
| 1805 | return 0; |
| 1806 | } |
| 1807 | |
| 1808 | static void qpnp_haptics_brightness_set(struct led_classdev *cdev, |
| 1809 | enum led_brightness level) |
| 1810 | { |
| 1811 | } |
| 1812 | |
| 1813 | static int qpnp_haptics_config(struct hap_chip *chip) |
| 1814 | { |
| 1815 | u8 rc_clk_err_deci_pct; |
| 1816 | u16 play_rate = 0; |
| 1817 | int rc; |
| 1818 | |
| 1819 | /* Configure the CFG1 register for actuator type */ |
| 1820 | rc = qpnp_haptics_masked_write_reg(chip, HAP_CFG1_REG(chip), |
| 1821 | HAP_ACT_TYPE_MASK, chip->act_type); |
| 1822 | if (rc < 0) |
| 1823 | return rc; |
| 1824 | |
| 1825 | /* Configure auto resonance parameters */ |
| 1826 | rc = qpnp_haptics_lra_auto_res_config(chip, NULL); |
| 1827 | if (rc < 0) |
| 1828 | return rc; |
| 1829 | |
| 1830 | /* Configure the PLAY MODE register */ |
| 1831 | rc = qpnp_haptics_play_mode_config(chip); |
| 1832 | if (rc < 0) |
| 1833 | return rc; |
| 1834 | |
| 1835 | /* Configure the VMAX register */ |
| 1836 | rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv, false); |
| 1837 | if (rc < 0) |
| 1838 | return rc; |
| 1839 | |
| 1840 | /* Configure the ILIM register */ |
| 1841 | rc = qpnp_haptics_ilim_config(chip); |
| 1842 | if (rc < 0) |
| 1843 | return rc; |
| 1844 | |
| 1845 | /* Configure the short circuit debounce register */ |
| 1846 | rc = qpnp_haptics_sc_deb_config(chip); |
| 1847 | if (rc < 0) |
| 1848 | return rc; |
| 1849 | |
| 1850 | /* Configure the WAVE SHAPE register */ |
| 1851 | rc = qpnp_haptics_masked_write_reg(chip, HAP_CFG2_REG(chip), |
| 1852 | HAP_LRA_RES_TYPE_MASK, chip->wave_shape); |
| 1853 | if (rc < 0) |
| 1854 | return rc; |
| 1855 | |
| 1856 | play_rate = chip->wave_play_rate_us / HAP_RATE_CFG_STEP_US; |
| 1857 | |
| 1858 | /* |
| 1859 | * The frequency of 19.2 MHz RC clock is subject to variation. Currently |
| 1860 | * some PMI chips have MISC_TRIM_ERROR_RC19P2_CLK register present in |
| 1861 | * MISC peripheral. This register holds the trim error of RC clock. |
| 1862 | */ |
| 1863 | if (chip->act_type == HAP_LRA && chip->misc_clk_trim_error_reg) { |
| 1864 | /* |
| 1865 | * Error is available in bits[3:0] and each LSB is 0.7%. |
| 1866 | * Bit 7 is the sign bit for error code. If it is set, then a |
| 1867 | * negative error correction needs to be made. Otherwise, a |
| 1868 | * positive error correction needs to be made. |
| 1869 | */ |
| 1870 | rc_clk_err_deci_pct = (chip->clk_trim_error_code & 0x0F) * 7; |
| 1871 | if (chip->clk_trim_error_code & BIT(7)) |
| 1872 | play_rate = (play_rate * |
| 1873 | (1000 - rc_clk_err_deci_pct)) / 1000; |
| 1874 | else |
| 1875 | play_rate = (play_rate * |
| 1876 | (1000 + rc_clk_err_deci_pct)) / 1000; |
| 1877 | |
| 1878 | pr_debug("TRIM register = 0x%x, play_rate=%d\n", |
| 1879 | chip->clk_trim_error_code, play_rate); |
| 1880 | } |
| 1881 | |
| 1882 | /* |
| 1883 | * Configure RATE_CFG1 and RATE_CFG2 registers. |
| 1884 | * Note: For ERM these registers act as play rate and |
| 1885 | * for LRA these represent resonance period |
| 1886 | */ |
| 1887 | rc = qpnp_haptics_update_rate_cfg(chip, play_rate); |
| 1888 | if (chip->act_type == HAP_LRA) { |
| 1889 | chip->drive_period_code_max_limit = (play_rate * |
| 1890 | (100 + chip->drive_period_code_max_var_pct)) / 100; |
| 1891 | chip->drive_period_code_min_limit = (play_rate * |
| 1892 | (100 - chip->drive_period_code_min_var_pct)) / 100; |
| 1893 | pr_debug("Drive period code max limit %x min limit %x\n", |
| 1894 | chip->drive_period_code_max_limit, |
| 1895 | chip->drive_period_code_min_limit); |
| 1896 | } |
| 1897 | |
| 1898 | rc = qpnp_haptics_brake_config(chip, NULL); |
| 1899 | if (rc < 0) |
| 1900 | return rc; |
| 1901 | |
| 1902 | if (chip->play_mode == HAP_BUFFER) { |
| 1903 | rc = qpnp_haptics_wave_rep_config(chip, |
| 1904 | HAP_WAVE_REPEAT | HAP_WAVE_SAMP_REPEAT); |
| 1905 | if (rc < 0) |
| 1906 | return rc; |
| 1907 | |
| 1908 | rc = qpnp_haptics_buffer_config(chip, NULL, false); |
| 1909 | } else if (chip->play_mode == HAP_PWM) { |
| 1910 | rc = qpnp_haptics_pwm_config(chip); |
| 1911 | } else if (chip->play_mode == HAP_AUDIO) { |
| 1912 | rc = qpnp_haptics_mod_enable(chip, true); |
| 1913 | } |
| 1914 | |
| 1915 | if (rc < 0) |
| 1916 | return rc; |
| 1917 | |
| 1918 | /* setup play irq */ |
| 1919 | if (chip->play_irq >= 0) { |
| 1920 | rc = devm_request_threaded_irq(&chip->pdev->dev, chip->play_irq, |
| 1921 | NULL, qpnp_haptics_play_irq_handler, IRQF_ONESHOT, |
| 1922 | "haptics_play_irq", chip); |
| 1923 | if (rc < 0) { |
| 1924 | pr_err("Unable to request play(%d) IRQ(err:%d)\n", |
| 1925 | chip->play_irq, rc); |
| 1926 | return rc; |
| 1927 | } |
| 1928 | |
| 1929 | /* use play_irq only for buffer mode */ |
| 1930 | if (chip->play_mode != HAP_BUFFER) { |
| 1931 | disable_irq(chip->play_irq); |
| 1932 | chip->play_irq_en = false; |
| 1933 | } |
| 1934 | } |
| 1935 | |
| 1936 | /* setup short circuit irq */ |
| 1937 | if (chip->sc_irq >= 0) { |
| 1938 | rc = devm_request_threaded_irq(&chip->pdev->dev, chip->sc_irq, |
| 1939 | NULL, qpnp_haptics_sc_irq_handler, IRQF_ONESHOT, |
| 1940 | "haptics_sc_irq", chip); |
| 1941 | if (rc < 0) { |
| 1942 | pr_err("Unable to request sc(%d) IRQ(err:%d)\n", |
| 1943 | chip->sc_irq, rc); |
| 1944 | return rc; |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | return rc; |
| 1949 | } |
| 1950 | |
| 1951 | static int qpnp_haptics_parse_buffer_dt(struct hap_chip *chip) |
| 1952 | { |
| 1953 | struct device_node *node = chip->pdev->dev.of_node; |
| 1954 | u32 temp; |
| 1955 | int rc, i, wf_samp_len; |
| 1956 | |
| 1957 | if (chip->wave_rep_cnt > 0 || chip->wave_s_rep_cnt > 0) |
| 1958 | return 0; |
| 1959 | |
| 1960 | chip->wave_rep_cnt = WF_REPEAT_MIN; |
| 1961 | rc = of_property_read_u32(node, "qcom,wave-rep-cnt", &temp); |
| 1962 | if (!rc) { |
| 1963 | chip->wave_rep_cnt = temp; |
| 1964 | } else if (rc != -EINVAL) { |
| 1965 | pr_err("Unable to read rep cnt rc=%d\n", rc); |
| 1966 | return rc; |
| 1967 | } |
| 1968 | |
| 1969 | chip->wave_s_rep_cnt = WF_S_REPEAT_MIN; |
| 1970 | rc = of_property_read_u32(node, |
| 1971 | "qcom,wave-samp-rep-cnt", &temp); |
| 1972 | if (!rc) { |
| 1973 | chip->wave_s_rep_cnt = temp; |
| 1974 | } else if (rc != -EINVAL) { |
| 1975 | pr_err("Unable to read samp rep cnt rc=%d\n", rc); |
| 1976 | return rc; |
| 1977 | } |
| 1978 | |
| 1979 | wf_samp_len = of_property_count_elems_of_size(node, |
| 1980 | "qcom,wave-samples", sizeof(u32)); |
| 1981 | if (wf_samp_len > 0) { |
| 1982 | if (wf_samp_len > HAP_WAVE_SAMP_SET_LEN) { |
| 1983 | pr_err("Invalid length for wave samples\n"); |
| 1984 | return -EINVAL; |
| 1985 | } |
| 1986 | |
| 1987 | rc = of_property_read_u32_array(node, "qcom,wave-samples", |
| 1988 | chip->wave_samp, wf_samp_len); |
| 1989 | if (rc < 0) { |
| 1990 | pr_err("Error in reading qcom,wave-samples, rc=%d\n", |
| 1991 | rc); |
| 1992 | return rc; |
| 1993 | } |
| 1994 | } else { |
| 1995 | /* Use default values */ |
| 1996 | for (i = 0; i < HAP_WAVE_SAMP_LEN; i++) |
| 1997 | chip->wave_samp[i] = HAP_WF_SAMP_MAX; |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 1998 | |
| 1999 | wf_samp_len = HAP_WAVE_SAMP_LEN; |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 2000 | } |
Subbaraman Narayanamurthy | 6ff7c75 | 2018-01-08 14:57:12 -0800 | [diff] [blame] | 2001 | chip->wf_samp_len = wf_samp_len; |
Subbaraman Narayanamurthy | 0b5fbf3 | 2017-05-11 18:50:43 -0700 | [diff] [blame] | 2002 | |
| 2003 | return 0; |
| 2004 | } |
| 2005 | |
| 2006 | static int qpnp_haptics_parse_pwm_dt(struct hap_chip *chip) |
| 2007 | { |
| 2008 | struct device_node *node = chip->pdev->dev.of_node; |
| 2009 | u32 temp; |
| 2010 | int rc; |
| 2011 | |
| 2012 | if (chip->pwm_data.period_us > 0 && chip->pwm_data.duty_us > 0) |
| 2013 | return 0; |
| 2014 | |
| 2015 | chip->pwm_data.pwm_dev = of_pwm_get(node, NULL); |
| 2016 | if (IS_ERR(chip->pwm_data.pwm_dev)) { |
| 2017 | rc = PTR_ERR(chip->pwm_data.pwm_dev); |
| 2018 | pr_err("Cannot get PWM device rc=%d\n", rc); |
| 2019 | chip->pwm_data.pwm_dev = NULL; |
| 2020 | return rc; |
| 2021 | } |
| 2022 | |
| 2023 | rc = of_property_read_u32(node, "qcom,period-us", &temp); |
| 2024 | if (!rc) { |
| 2025 | chip->pwm_data.period_us = temp; |
| 2026 | } else { |
| 2027 | pr_err("Cannot read PWM period rc=%d\n", rc); |
| 2028 | return rc; |
| 2029 | } |
| 2030 | |
| 2031 | rc = of_property_read_u32(node, "qcom,duty-us", &temp); |
| 2032 | if (!rc) { |
| 2033 | chip->pwm_data.duty_us = temp; |
| 2034 | } else { |
| 2035 | pr_err("Cannot read PWM duty rc=%d\n", rc); |
| 2036 | return rc; |
| 2037 | } |
| 2038 | |
| 2039 | rc = of_property_read_u32(node, "qcom,ext-pwm-dtest-line", &temp); |
| 2040 | if (!rc) |
| 2041 | chip->ext_pwm_dtest_line = temp; |
| 2042 | |
| 2043 | rc = of_property_read_u32(node, "qcom,ext-pwm-freq-khz", &temp); |
| 2044 | if (!rc) { |
| 2045 | chip->ext_pwm_freq_khz = temp; |
| 2046 | } else if (rc != -EINVAL) { |
| 2047 | pr_err("Unable to read ext pwm freq rc=%d\n", rc); |
| 2048 | return rc; |
| 2049 | } |
| 2050 | |
| 2051 | return 0; |
| 2052 | } |
| 2053 | |
| 2054 | static int qpnp_haptics_parse_dt(struct hap_chip *chip) |
| 2055 | { |
| 2056 | struct device_node *node = chip->pdev->dev.of_node; |
| 2057 | struct device_node *revid_node, *misc_node; |
| 2058 | const char *temp_str; |
| 2059 | int rc, temp; |
| 2060 | |
| 2061 | rc = of_property_read_u32(node, "reg", &temp); |
| 2062 | if (rc < 0) { |
| 2063 | pr_err("Couldn't find reg in node = %s rc = %d\n", |
| 2064 | node->full_name, rc); |
| 2065 | return rc; |
| 2066 | } |
| 2067 | |
| 2068 | if (temp <= 0) { |
| 2069 | pr_err("Invalid base address %x\n", temp); |
| 2070 | return -EINVAL; |
| 2071 | } |
| 2072 | chip->base = (u16)temp; |
| 2073 | |
| 2074 | revid_node = of_parse_phandle(node, "qcom,pmic-revid", 0); |
| 2075 | if (!revid_node) { |
| 2076 | pr_err("Missing qcom,pmic-revid property\n"); |
| 2077 | return -EINVAL; |
| 2078 | } |
| 2079 | |
| 2080 | chip->revid = get_revid_data(revid_node); |
| 2081 | of_node_put(revid_node); |
| 2082 | if (IS_ERR_OR_NULL(chip->revid)) { |
| 2083 | pr_err("Unable to get pmic_revid rc=%ld\n", |
| 2084 | PTR_ERR(chip->revid)); |
| 2085 | /* |
| 2086 | * the revid peripheral must be registered, any failure |
| 2087 | * here only indicates that the rev-id module has not |
| 2088 | * probed yet. |
| 2089 | */ |
| 2090 | return -EPROBE_DEFER; |
| 2091 | } |
| 2092 | |
| 2093 | if (of_find_property(node, "qcom,pmic-misc", NULL)) { |
| 2094 | misc_node = of_parse_phandle(node, "qcom,pmic-misc", 0); |
| 2095 | if (!misc_node) |
| 2096 | return -EINVAL; |
| 2097 | |
| 2098 | rc = of_property_read_u32(node, "qcom,misc-clk-trim-error-reg", |
| 2099 | &chip->misc_clk_trim_error_reg); |
| 2100 | if (rc < 0 || !chip->misc_clk_trim_error_reg) { |
| 2101 | pr_err("Invalid or missing misc-clk-trim-error-reg\n"); |
| 2102 | of_node_put(misc_node); |
| 2103 | return rc; |
| 2104 | } |
| 2105 | |
| 2106 | rc = qpnp_misc_read_reg(misc_node, |
| 2107 | chip->misc_clk_trim_error_reg, |
| 2108 | &chip->clk_trim_error_code); |
| 2109 | if (rc < 0) { |
| 2110 | pr_err("Couldn't get clk_trim_error_code, rc=%d\n", rc); |
| 2111 | of_node_put(misc_node); |
| 2112 | return -EPROBE_DEFER; |
| 2113 | } |
| 2114 | of_node_put(misc_node); |
| 2115 | } |
| 2116 | |
| 2117 | chip->play_irq = platform_get_irq_byname(chip->pdev, "hap-play-irq"); |
| 2118 | if (chip->play_irq < 0) { |
| 2119 | pr_err("Unable to get play irq\n"); |
| 2120 | return chip->play_irq; |
| 2121 | } |
| 2122 | |
| 2123 | chip->sc_irq = platform_get_irq_byname(chip->pdev, "hap-sc-irq"); |
| 2124 | if (chip->sc_irq < 0) { |
| 2125 | pr_err("Unable to get sc irq\n"); |
| 2126 | return chip->sc_irq; |
| 2127 | } |
| 2128 | |
| 2129 | chip->act_type = HAP_LRA; |
| 2130 | rc = of_property_read_u32(node, "qcom,actuator-type", &temp); |
| 2131 | if (!rc) { |
| 2132 | if (temp != HAP_LRA && temp != HAP_ERM) { |
| 2133 | pr_err("Incorrect actuator type\n"); |
| 2134 | return -EINVAL; |
| 2135 | } |
| 2136 | chip->act_type = temp; |
| 2137 | } |
| 2138 | |
| 2139 | chip->lra_auto_mode = of_property_read_bool(node, "qcom,lra-auto-mode"); |
| 2140 | |
| 2141 | rc = of_property_read_string(node, "qcom,play-mode", &temp_str); |
| 2142 | if (!rc) { |
| 2143 | if (strcmp(temp_str, "direct") == 0) |
| 2144 | chip->play_mode = HAP_DIRECT; |
| 2145 | else if (strcmp(temp_str, "buffer") == 0) |
| 2146 | chip->play_mode = HAP_BUFFER; |
| 2147 | else if (strcmp(temp_str, "pwm") == 0) |
| 2148 | chip->play_mode = HAP_PWM; |
| 2149 | else if (strcmp(temp_str, "audio") == 0) |
| 2150 | chip->play_mode = HAP_AUDIO; |
| 2151 | else { |
| 2152 | pr_err("Invalid play mode\n"); |
| 2153 | return -EINVAL; |
| 2154 | } |
| 2155 | } else { |
| 2156 | if (rc == -EINVAL && chip->act_type == HAP_LRA) { |
| 2157 | pr_info("Play mode not specified, using auto mode\n"); |
| 2158 | chip->lra_auto_mode = true; |
| 2159 | } else { |
| 2160 | pr_err("Unable to read play mode\n"); |
| 2161 | return rc; |
| 2162 | } |
| 2163 | } |
| 2164 | |
| 2165 | chip->max_play_time_ms = HAP_MAX_PLAY_TIME_MS; |
| 2166 | rc = of_property_read_u32(node, "qcom,max-play-time-ms", &temp); |
| 2167 | if (!rc) { |
| 2168 | chip->max_play_time_ms = temp; |
| 2169 | } else if (rc != -EINVAL) { |
| 2170 | pr_err("Unable to read max-play-time rc=%d\n", rc); |
| 2171 | return rc; |
| 2172 | } |
| 2173 | |
| 2174 | chip->vmax_mv = HAP_VMAX_MAX_MV; |
| 2175 | rc = of_property_read_u32(node, "qcom,vmax-mv", &temp); |
| 2176 | if (!rc) { |
| 2177 | chip->vmax_mv = temp; |
| 2178 | } else if (rc != -EINVAL) { |
| 2179 | pr_err("Unable to read Vmax rc=%d\n", rc); |
| 2180 | return rc; |
| 2181 | } |
| 2182 | |
| 2183 | chip->ilim_ma = HAP_ILIM_400_MA; |
| 2184 | rc = of_property_read_u32(node, "qcom,ilim-ma", &temp); |
| 2185 | if (!rc) { |
| 2186 | chip->ilim_ma = (u8)temp; |
| 2187 | } else if (rc != -EINVAL) { |
| 2188 | pr_err("Unable to read ILIM rc=%d\n", rc); |
| 2189 | return rc; |
| 2190 | } |
| 2191 | |
| 2192 | chip->sc_deb_cycles = HAP_DEF_SC_DEB_CYCLES; |
| 2193 | rc = of_property_read_u32(node, "qcom,sc-dbc-cycles", &temp); |
| 2194 | if (!rc) { |
| 2195 | chip->sc_deb_cycles = temp; |
| 2196 | } else if (rc != -EINVAL) { |
| 2197 | pr_err("Unable to read sc debounce rc=%d\n", rc); |
| 2198 | return rc; |
| 2199 | } |
| 2200 | |
| 2201 | chip->wave_shape = HAP_WAVE_SQUARE; |
| 2202 | rc = of_property_read_string(node, "qcom,wave-shape", &temp_str); |
| 2203 | if (!rc) { |
| 2204 | if (strcmp(temp_str, "sine") == 0) |
| 2205 | chip->wave_shape = HAP_WAVE_SINE; |
| 2206 | else if (strcmp(temp_str, "square") == 0) |
| 2207 | chip->wave_shape = HAP_WAVE_SQUARE; |
| 2208 | else { |
| 2209 | pr_err("Unsupported wave shape\n"); |
| 2210 | return -EINVAL; |
| 2211 | } |
| 2212 | } else if (rc != -EINVAL) { |
| 2213 | pr_err("Unable to read wave shape rc=%d\n", rc); |
| 2214 | return rc; |
| 2215 | } |
| 2216 | |
| 2217 | chip->wave_play_rate_us = HAP_DEF_WAVE_PLAY_RATE_US; |
| 2218 | rc = of_property_read_u32(node, |
| 2219 | "qcom,wave-play-rate-us", &temp); |
| 2220 | if (!rc) { |
| 2221 | chip->wave_play_rate_us = temp; |
| 2222 | } else if (rc != -EINVAL) { |
| 2223 | pr_err("Unable to read play rate rc=%d\n", rc); |
| 2224 | return rc; |
| 2225 | } |
| 2226 | |
| 2227 | if (chip->wave_play_rate_us < HAP_WAVE_PLAY_RATE_US_MIN) |
| 2228 | chip->wave_play_rate_us = HAP_WAVE_PLAY_RATE_US_MIN; |
| 2229 | else if (chip->wave_play_rate_us > HAP_WAVE_PLAY_RATE_US_MAX) |
| 2230 | chip->wave_play_rate_us = HAP_WAVE_PLAY_RATE_US_MAX; |
| 2231 | |
| 2232 | chip->en_brake = of_property_read_bool(node, "qcom,en-brake"); |
| 2233 | |
| 2234 | rc = of_property_count_elems_of_size(node, |
| 2235 | "qcom,brake-pattern", sizeof(u32)); |
| 2236 | if (rc > 0) { |
| 2237 | if (rc != HAP_BRAKE_PAT_LEN) { |
| 2238 | pr_err("Invalid length for brake pattern\n"); |
| 2239 | return -EINVAL; |
| 2240 | } |
| 2241 | |
| 2242 | rc = of_property_read_u32_array(node, "qcom,brake-pattern", |
| 2243 | chip->brake_pat, HAP_BRAKE_PAT_LEN); |
| 2244 | if (rc < 0) { |
| 2245 | pr_err("Error in reading qcom,brake-pattern, rc=%d\n", |
| 2246 | rc); |
| 2247 | return rc; |
| 2248 | } |
| 2249 | } |
| 2250 | |
| 2251 | /* Read the following properties only for LRA */ |
| 2252 | if (chip->act_type == HAP_LRA) { |
| 2253 | rc = of_property_read_string(node, "qcom,lra-auto-res-mode", |
| 2254 | &temp_str); |
| 2255 | if (!rc) { |
| 2256 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 2257 | chip->ares_cfg.auto_res_mode = |
| 2258 | HAP_PM660_AUTO_RES_QWD; |
| 2259 | if (strcmp(temp_str, "zxd") == 0) |
| 2260 | chip->ares_cfg.auto_res_mode = |
| 2261 | HAP_PM660_AUTO_RES_ZXD; |
| 2262 | else if (strcmp(temp_str, "qwd") == 0) |
| 2263 | chip->ares_cfg.auto_res_mode = |
| 2264 | HAP_PM660_AUTO_RES_QWD; |
| 2265 | } else { |
| 2266 | chip->ares_cfg.auto_res_mode = |
| 2267 | HAP_AUTO_RES_ZXD_EOP; |
| 2268 | if (strcmp(temp_str, "none") == 0) |
| 2269 | chip->ares_cfg.auto_res_mode = |
| 2270 | HAP_AUTO_RES_NONE; |
| 2271 | else if (strcmp(temp_str, "zxd") == 0) |
| 2272 | chip->ares_cfg.auto_res_mode = |
| 2273 | HAP_AUTO_RES_ZXD; |
| 2274 | else if (strcmp(temp_str, "qwd") == 0) |
| 2275 | chip->ares_cfg.auto_res_mode = |
| 2276 | HAP_AUTO_RES_QWD; |
| 2277 | else if (strcmp(temp_str, "max-qwd") == 0) |
| 2278 | chip->ares_cfg.auto_res_mode = |
| 2279 | HAP_AUTO_RES_MAX_QWD; |
| 2280 | else |
| 2281 | chip->ares_cfg.auto_res_mode = |
| 2282 | HAP_AUTO_RES_ZXD_EOP; |
| 2283 | } |
| 2284 | } else if (rc != -EINVAL) { |
| 2285 | pr_err("Unable to read auto res mode rc=%d\n", rc); |
| 2286 | return rc; |
| 2287 | } |
| 2288 | |
| 2289 | chip->ares_cfg.lra_high_z = HAP_LRA_HIGH_Z_OPT3; |
| 2290 | rc = of_property_read_string(node, "qcom,lra-high-z", |
| 2291 | &temp_str); |
| 2292 | if (!rc) { |
| 2293 | if (strcmp(temp_str, "none") == 0) |
| 2294 | chip->ares_cfg.lra_high_z = |
| 2295 | HAP_LRA_HIGH_Z_NONE; |
| 2296 | else if (strcmp(temp_str, "opt1") == 0) |
| 2297 | chip->ares_cfg.lra_high_z = |
| 2298 | HAP_LRA_HIGH_Z_OPT1; |
| 2299 | else if (strcmp(temp_str, "opt2") == 0) |
| 2300 | chip->ares_cfg.lra_high_z = |
| 2301 | HAP_LRA_HIGH_Z_OPT2; |
| 2302 | else |
| 2303 | chip->ares_cfg.lra_high_z = |
| 2304 | HAP_LRA_HIGH_Z_OPT3; |
| 2305 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 2306 | if (strcmp(temp_str, "opt0") == 0) |
| 2307 | chip->ares_cfg.lra_high_z = |
| 2308 | HAP_LRA_HIGH_Z_NONE; |
| 2309 | } |
| 2310 | } else if (rc != -EINVAL) { |
| 2311 | pr_err("Unable to read LRA high-z rc=%d\n", rc); |
| 2312 | return rc; |
| 2313 | } |
| 2314 | |
| 2315 | chip->ares_cfg.lra_res_cal_period = HAP_RES_CAL_PERIOD_MAX; |
| 2316 | rc = of_property_read_u32(node, |
| 2317 | "qcom,lra-res-cal-period", &temp); |
| 2318 | if (!rc) { |
| 2319 | chip->ares_cfg.lra_res_cal_period = temp; |
| 2320 | } else if (rc != -EINVAL) { |
| 2321 | pr_err("Unable to read cal period rc=%d\n", rc); |
| 2322 | return rc; |
| 2323 | } |
| 2324 | |
| 2325 | chip->ares_cfg.lra_qwd_drive_duration = -EINVAL; |
| 2326 | chip->ares_cfg.calibrate_at_eop = -EINVAL; |
| 2327 | if (chip->revid->pmic_subtype == PM660_SUBTYPE) { |
| 2328 | rc = of_property_read_u32(node, |
| 2329 | "qcom,lra-qwd-drive-duration", |
| 2330 | &chip->ares_cfg.lra_qwd_drive_duration); |
| 2331 | if (rc && rc != -EINVAL) { |
| 2332 | pr_err("Unable to read LRA QWD drive duration rc=%d\n", |
| 2333 | rc); |
| 2334 | return rc; |
| 2335 | } |
| 2336 | |
| 2337 | rc = of_property_read_u32(node, |
| 2338 | "qcom,lra-calibrate-at-eop", |
| 2339 | &chip->ares_cfg.calibrate_at_eop); |
| 2340 | if (rc && rc != -EINVAL) { |
| 2341 | pr_err("Unable to read Calibrate at EOP rc=%d\n", |
| 2342 | rc); |
| 2343 | return rc; |
| 2344 | } |
| 2345 | } |
| 2346 | |
| 2347 | chip->drive_period_code_max_var_pct = 25; |
| 2348 | rc = of_property_read_u32(node, |
| 2349 | "qcom,drive-period-code-max-variation-pct", &temp); |
| 2350 | if (!rc) { |
| 2351 | if (temp > 0 && temp < 100) |
| 2352 | chip->drive_period_code_max_var_pct = (u8)temp; |
| 2353 | } else if (rc != -EINVAL) { |
| 2354 | pr_err("Unable to read drive period code max var pct rc=%d\n", |
| 2355 | rc); |
| 2356 | return rc; |
| 2357 | } |
| 2358 | |
| 2359 | chip->drive_period_code_min_var_pct = 25; |
| 2360 | rc = of_property_read_u32(node, |
| 2361 | "qcom,drive-period-code-min-variation-pct", &temp); |
| 2362 | if (!rc) { |
| 2363 | if (temp > 0 && temp < 100) |
| 2364 | chip->drive_period_code_min_var_pct = (u8)temp; |
| 2365 | } else if (rc != -EINVAL) { |
| 2366 | pr_err("Unable to read drive period code min var pct rc=%d\n", |
| 2367 | rc); |
| 2368 | return rc; |
| 2369 | } |
| 2370 | |
| 2371 | chip->auto_res_err_recovery_hw = |
| 2372 | of_property_read_bool(node, |
| 2373 | "qcom,auto-res-err-recovery-hw"); |
| 2374 | |
| 2375 | if (chip->revid->pmic_subtype != PM660_SUBTYPE) |
| 2376 | chip->auto_res_err_recovery_hw = false; |
| 2377 | } |
| 2378 | |
| 2379 | if (rc == -EINVAL) |
| 2380 | rc = 0; |
| 2381 | |
| 2382 | if (chip->play_mode == HAP_BUFFER) |
| 2383 | rc = qpnp_haptics_parse_buffer_dt(chip); |
| 2384 | else if (chip->play_mode == HAP_PWM) |
| 2385 | rc = qpnp_haptics_parse_pwm_dt(chip); |
| 2386 | |
| 2387 | return rc; |
| 2388 | } |
| 2389 | |
| 2390 | static int qpnp_haptics_probe(struct platform_device *pdev) |
| 2391 | { |
| 2392 | struct hap_chip *chip; |
| 2393 | int rc, i; |
| 2394 | |
| 2395 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
| 2396 | if (!chip) |
| 2397 | return -ENOMEM; |
| 2398 | |
| 2399 | chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2400 | if (!chip->regmap) { |
| 2401 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 2402 | return -EINVAL; |
| 2403 | } |
| 2404 | |
| 2405 | chip->pdev = pdev; |
| 2406 | rc = qpnp_haptics_parse_dt(chip); |
| 2407 | if (rc < 0) { |
| 2408 | dev_err(&pdev->dev, "Error in parsing DT parameters, rc=%d\n", |
| 2409 | rc); |
| 2410 | return rc; |
| 2411 | } |
| 2412 | |
| 2413 | spin_lock_init(&chip->bus_lock); |
| 2414 | mutex_init(&chip->play_lock); |
| 2415 | mutex_init(&chip->param_lock); |
| 2416 | INIT_WORK(&chip->haptics_work, qpnp_haptics_work); |
| 2417 | |
| 2418 | rc = qpnp_haptics_config(chip); |
| 2419 | if (rc < 0) { |
| 2420 | dev_err(&pdev->dev, "Error in configuring haptics, rc=%d\n", |
| 2421 | rc); |
| 2422 | goto fail; |
| 2423 | } |
| 2424 | |
| 2425 | hrtimer_init(&chip->stop_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
| 2426 | chip->stop_timer.function = hap_stop_timer; |
| 2427 | hrtimer_init(&chip->auto_res_err_poll_timer, CLOCK_MONOTONIC, |
| 2428 | HRTIMER_MODE_REL); |
| 2429 | chip->auto_res_err_poll_timer.function = hap_auto_res_err_poll_timer; |
| 2430 | dev_set_drvdata(&pdev->dev, chip); |
| 2431 | |
| 2432 | chip->cdev.name = "vibrator"; |
| 2433 | chip->cdev.brightness_get = qpnp_haptics_brightness_get; |
| 2434 | chip->cdev.brightness_set = qpnp_haptics_brightness_set; |
| 2435 | chip->cdev.max_brightness = 100; |
| 2436 | rc = devm_led_classdev_register(&pdev->dev, &chip->cdev); |
| 2437 | if (rc < 0) { |
| 2438 | dev_err(&pdev->dev, "Error in registering led class device, rc=%d\n", |
| 2439 | rc); |
| 2440 | goto register_fail; |
| 2441 | } |
| 2442 | |
| 2443 | for (i = 0; i < ARRAY_SIZE(qpnp_haptics_attrs); i++) { |
| 2444 | rc = sysfs_create_file(&chip->cdev.dev->kobj, |
| 2445 | &qpnp_haptics_attrs[i].attr); |
| 2446 | if (rc < 0) { |
| 2447 | dev_err(&pdev->dev, "Error in creating sysfs file, rc=%d\n", |
| 2448 | rc); |
| 2449 | goto sysfs_fail; |
| 2450 | } |
| 2451 | } |
| 2452 | |
| 2453 | return 0; |
| 2454 | |
| 2455 | sysfs_fail: |
| 2456 | for (--i; i >= 0; i--) |
| 2457 | sysfs_remove_file(&chip->cdev.dev->kobj, |
| 2458 | &qpnp_haptics_attrs[i].attr); |
| 2459 | register_fail: |
| 2460 | cancel_work_sync(&chip->haptics_work); |
| 2461 | hrtimer_cancel(&chip->auto_res_err_poll_timer); |
| 2462 | hrtimer_cancel(&chip->stop_timer); |
| 2463 | fail: |
| 2464 | mutex_destroy(&chip->play_lock); |
| 2465 | mutex_destroy(&chip->param_lock); |
| 2466 | if (chip->pwm_data.pwm_dev) |
| 2467 | pwm_put(chip->pwm_data.pwm_dev); |
| 2468 | dev_set_drvdata(&pdev->dev, NULL); |
| 2469 | return rc; |
| 2470 | } |
| 2471 | |
| 2472 | static int qpnp_haptics_remove(struct platform_device *pdev) |
| 2473 | { |
| 2474 | struct hap_chip *chip = dev_get_drvdata(&pdev->dev); |
| 2475 | |
| 2476 | cancel_work_sync(&chip->haptics_work); |
| 2477 | hrtimer_cancel(&chip->auto_res_err_poll_timer); |
| 2478 | hrtimer_cancel(&chip->stop_timer); |
| 2479 | mutex_destroy(&chip->play_lock); |
| 2480 | mutex_destroy(&chip->param_lock); |
| 2481 | if (chip->pwm_data.pwm_dev) |
| 2482 | pwm_put(chip->pwm_data.pwm_dev); |
| 2483 | dev_set_drvdata(&pdev->dev, NULL); |
| 2484 | |
| 2485 | return 0; |
| 2486 | } |
| 2487 | |
| 2488 | static const struct dev_pm_ops qpnp_haptics_pm_ops = { |
| 2489 | .suspend = qpnp_haptics_suspend, |
| 2490 | }; |
| 2491 | |
| 2492 | static const struct of_device_id hap_match_table[] = { |
| 2493 | { .compatible = "qcom,qpnp-haptics" }, |
| 2494 | { }, |
| 2495 | }; |
| 2496 | |
| 2497 | static struct platform_driver qpnp_haptics_driver = { |
| 2498 | .driver = { |
| 2499 | .name = "qcom,qpnp-haptics", |
| 2500 | .of_match_table = hap_match_table, |
| 2501 | .pm = &qpnp_haptics_pm_ops, |
| 2502 | }, |
| 2503 | .probe = qpnp_haptics_probe, |
| 2504 | .remove = qpnp_haptics_remove, |
| 2505 | }; |
| 2506 | module_platform_driver(qpnp_haptics_driver); |
| 2507 | |
| 2508 | MODULE_DESCRIPTION("QPNP haptics driver"); |
| 2509 | MODULE_LICENSE("GPL v2"); |