blob: 5b5afc14447817ede31e23807af451f4def6e989 [file] [log] [blame]
Mark Brownf10485e2008-06-05 13:49:33 +01001/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <asm/div64.h>
30
31#include "wm8990.h"
32
Mark Brownf10485e2008-06-05 13:49:33 +010033#define WM8990_VERSION "0.2"
34
Mark Brownf10485e2008-06-05 13:49:33 +010035/* codec private data */
36struct wm8990_priv {
37 unsigned int sysclk;
38 unsigned int pcmclk;
39};
40
41/*
42 * wm8990 register cache. Note that register 0 is not included in the
43 * cache.
44 */
45static const u16 wm8990_reg[] = {
46 0x8990, /* R0 - Reset */
47 0x0000, /* R1 - Power Management (1) */
48 0x6000, /* R2 - Power Management (2) */
49 0x0000, /* R3 - Power Management (3) */
50 0x4050, /* R4 - Audio Interface (1) */
51 0x4000, /* R5 - Audio Interface (2) */
52 0x01C8, /* R6 - Clocking (1) */
53 0x0000, /* R7 - Clocking (2) */
54 0x0040, /* R8 - Audio Interface (3) */
55 0x0040, /* R9 - Audio Interface (4) */
56 0x0004, /* R10 - DAC CTRL */
57 0x00C0, /* R11 - Left DAC Digital Volume */
58 0x00C0, /* R12 - Right DAC Digital Volume */
59 0x0000, /* R13 - Digital Side Tone */
60 0x0100, /* R14 - ADC CTRL */
61 0x00C0, /* R15 - Left ADC Digital Volume */
62 0x00C0, /* R16 - Right ADC Digital Volume */
63 0x0000, /* R17 */
64 0x0000, /* R18 - GPIO CTRL 1 */
65 0x1000, /* R19 - GPIO1 & GPIO2 */
66 0x1010, /* R20 - GPIO3 & GPIO4 */
67 0x1010, /* R21 - GPIO5 & GPIO6 */
68 0x8000, /* R22 - GPIOCTRL 2 */
69 0x0800, /* R23 - GPIO_POL */
70 0x008B, /* R24 - Left Line Input 1&2 Volume */
71 0x008B, /* R25 - Left Line Input 3&4 Volume */
72 0x008B, /* R26 - Right Line Input 1&2 Volume */
73 0x008B, /* R27 - Right Line Input 3&4 Volume */
74 0x0000, /* R28 - Left Output Volume */
75 0x0000, /* R29 - Right Output Volume */
76 0x0066, /* R30 - Line Outputs Volume */
77 0x0022, /* R31 - Out3/4 Volume */
78 0x0079, /* R32 - Left OPGA Volume */
79 0x0079, /* R33 - Right OPGA Volume */
80 0x0003, /* R34 - Speaker Volume */
81 0x0003, /* R35 - ClassD1 */
82 0x0000, /* R36 */
83 0x0100, /* R37 - ClassD3 */
Mark Brown97bb8122008-08-15 16:22:33 +010084 0x0079, /* R38 - ClassD4 */
Mark Brownf10485e2008-06-05 13:49:33 +010085 0x0000, /* R39 - Input Mixer1 */
86 0x0000, /* R40 - Input Mixer2 */
87 0x0000, /* R41 - Input Mixer3 */
88 0x0000, /* R42 - Input Mixer4 */
89 0x0000, /* R43 - Input Mixer5 */
90 0x0000, /* R44 - Input Mixer6 */
91 0x0000, /* R45 - Output Mixer1 */
92 0x0000, /* R46 - Output Mixer2 */
93 0x0000, /* R47 - Output Mixer3 */
94 0x0000, /* R48 - Output Mixer4 */
95 0x0000, /* R49 - Output Mixer5 */
96 0x0000, /* R50 - Output Mixer6 */
97 0x0180, /* R51 - Out3/4 Mixer */
98 0x0000, /* R52 - Line Mixer1 */
99 0x0000, /* R53 - Line Mixer2 */
100 0x0000, /* R54 - Speaker Mixer */
101 0x0000, /* R55 - Additional Control */
102 0x0000, /* R56 - AntiPOP1 */
103 0x0000, /* R57 - AntiPOP2 */
104 0x0000, /* R58 - MICBIAS */
105 0x0000, /* R59 */
106 0x0008, /* R60 - PLL1 */
107 0x0031, /* R61 - PLL2 */
108 0x0026, /* R62 - PLL3 */
Mark Brownba533e92008-11-17 16:59:24 +0000109 0x0000, /* R63 - Driver internal */
Mark Brownf10485e2008-06-05 13:49:33 +0100110};
111
112/*
113 * read wm8990 register cache
114 */
115static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
116 unsigned int reg)
117{
118 u16 *cache = codec->reg_cache;
119 BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1);
120 return cache[reg];
121}
122
123/*
124 * write wm8990 register cache
125 */
126static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
127 unsigned int reg, unsigned int value)
128{
129 u16 *cache = codec->reg_cache;
Mark Brownf10485e2008-06-05 13:49:33 +0100130
Mark Brownba533e92008-11-17 16:59:24 +0000131 /* Reset register and reserved registers are uncached */
132 if (reg == 0 || reg > ARRAY_SIZE(wm8990_reg) - 1)
Mark Brownf10485e2008-06-05 13:49:33 +0100133 return;
134
135 cache[reg] = value;
136}
137
138/*
139 * write to the wm8990 register space
140 */
141static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
142 unsigned int value)
143{
144 u8 data[3];
145
146 data[0] = reg & 0xFF;
147 data[1] = (value >> 8) & 0xFF;
148 data[2] = value & 0xFF;
149
150 wm8990_write_reg_cache(codec, reg, value);
151
152 if (codec->hw_write(codec->control_data, data, 3) == 2)
153 return 0;
154 else
155 return -EIO;
156}
157
158#define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
159
160static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
161
162static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000);
163
164static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100);
165
166static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600);
167
168static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0);
169
170static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0);
171
172static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763);
173
174static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0);
175
176static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
177 struct snd_ctl_elem_value *ucontrol)
178{
179 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
180 int reg = kcontrol->private_value & 0xff;
181 int ret;
182 u16 val;
183
184 ret = snd_soc_put_volsw(kcontrol, ucontrol);
185 if (ret < 0)
186 return ret;
187
188 /* now hit the volume update bits (always bit 8) */
189 val = wm8990_read_reg_cache(codec, reg);
190 return wm8990_write(codec, reg, val | 0x0100);
191}
192
193#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
194 tlv_array) {\
195 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
196 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
197 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
198 .tlv.p = (tlv_array), \
199 .info = snd_soc_info_volsw, \
200 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
201 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
202
203
204static const char *wm8990_digital_sidetone[] =
205 {"None", "Left ADC", "Right ADC", "Reserved"};
206
207static const struct soc_enum wm8990_left_digital_sidetone_enum =
208SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
209 WM8990_ADC_TO_DACL_SHIFT,
210 WM8990_ADC_TO_DACL_MASK,
211 wm8990_digital_sidetone);
212
213static const struct soc_enum wm8990_right_digital_sidetone_enum =
214SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
215 WM8990_ADC_TO_DACR_SHIFT,
216 WM8990_ADC_TO_DACR_MASK,
217 wm8990_digital_sidetone);
218
219static const char *wm8990_adcmode[] =
220 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
221
222static const struct soc_enum wm8990_right_adcmode_enum =
223SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
224 WM8990_ADC_HPF_CUT_SHIFT,
225 WM8990_ADC_HPF_CUT_MASK,
226 wm8990_adcmode);
227
228static const struct snd_kcontrol_new wm8990_snd_controls[] = {
229/* INMIXL */
230SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
231SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
232/* INMIXR */
233SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
234SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
235
236/* LOMIX */
237SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
238 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
239SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
240 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
241SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
242 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
243SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
244 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
245SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
246 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
247SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
248 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
249
250/* ROMIX */
251SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
252 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
253SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
254 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
255SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
256 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
257SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
258 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
259SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
260 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
261SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
262 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
263
264/* LOUT */
265SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
266 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
267SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
268
269/* ROUT */
270SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
271 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
272SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
273
274/* LOPGA */
275SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
276 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
277SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
278 WM8990_LOPGAZC_BIT, 1, 0),
279
280/* ROPGA */
281SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
282 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
283SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
284 WM8990_ROPGAZC_BIT, 1, 0),
285
286SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
287 WM8990_LONMUTE_BIT, 1, 0),
288SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
289 WM8990_LOPMUTE_BIT, 1, 0),
290SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
291 WM8990_LOATTN_BIT, 1, 0),
292SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
293 WM8990_RONMUTE_BIT, 1, 0),
294SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
295 WM8990_ROPMUTE_BIT, 1, 0),
296SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
297 WM8990_ROATTN_BIT, 1, 0),
298
299SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
300 WM8990_OUT3MUTE_BIT, 1, 0),
301SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
302 WM8990_OUT3ATTN_BIT, 1, 0),
303
304SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
305 WM8990_OUT4MUTE_BIT, 1, 0),
306SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
307 WM8990_OUT4ATTN_BIT, 1, 0),
308
309SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
310 WM8990_CDMODE_BIT, 1, 0),
311
312SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
Mark Brown97bb8122008-08-15 16:22:33 +0100313 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
Mark Brownf10485e2008-06-05 13:49:33 +0100314SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
315 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
316SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
317 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
Mark Brown97bb8122008-08-15 16:22:33 +0100318SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
319 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
320SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
321 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
Mark Brownf10485e2008-06-05 13:49:33 +0100322
323SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
324 WM8990_LEFT_DAC_DIGITAL_VOLUME,
325 WM8990_DACL_VOL_SHIFT,
326 WM8990_DACL_VOL_MASK,
327 0,
328 out_dac_tlv),
329
330SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
331 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
332 WM8990_DACR_VOL_SHIFT,
333 WM8990_DACR_VOL_MASK,
334 0,
335 out_dac_tlv),
336
337SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
338SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
339
340SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
341 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
342 out_sidetone_tlv),
343SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
344 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
345 out_sidetone_tlv),
346
347SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
348 WM8990_ADC_HPF_ENA_BIT, 1, 0),
349
350SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
351
352SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
353 WM8990_LEFT_ADC_DIGITAL_VOLUME,
354 WM8990_ADCL_VOL_SHIFT,
355 WM8990_ADCL_VOL_MASK,
356 0,
357 in_adc_tlv),
358
359SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
360 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
361 WM8990_ADCR_VOL_SHIFT,
362 WM8990_ADCR_VOL_MASK,
363 0,
364 in_adc_tlv),
365
366SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
367 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
368 WM8990_LIN12VOL_SHIFT,
369 WM8990_LIN12VOL_MASK,
370 0,
371 in_pga_tlv),
372
373SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
374 WM8990_LI12ZC_BIT, 1, 0),
375
376SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
377 WM8990_LI12MUTE_BIT, 1, 0),
378
379SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
380 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
381 WM8990_LIN34VOL_SHIFT,
382 WM8990_LIN34VOL_MASK,
383 0,
384 in_pga_tlv),
385
386SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
387 WM8990_LI34ZC_BIT, 1, 0),
388
389SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
390 WM8990_LI34MUTE_BIT, 1, 0),
391
392SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
393 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
394 WM8990_RIN12VOL_SHIFT,
395 WM8990_RIN12VOL_MASK,
396 0,
397 in_pga_tlv),
398
399SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
400 WM8990_RI12ZC_BIT, 1, 0),
401
402SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
403 WM8990_RI12MUTE_BIT, 1, 0),
404
405SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
406 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
407 WM8990_RIN34VOL_SHIFT,
408 WM8990_RIN34VOL_MASK,
409 0,
410 in_pga_tlv),
411
412SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
413 WM8990_RI34ZC_BIT, 1, 0),
414
415SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
416 WM8990_RI34MUTE_BIT, 1, 0),
417
418};
419
420/* add non dapm controls */
421static int wm8990_add_controls(struct snd_soc_codec *codec)
422{
423 int err, i;
424
425 for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) {
426 err = snd_ctl_add(codec->card,
427 snd_soc_cnew(&wm8990_snd_controls[i], codec,
428 NULL));
429 if (err < 0)
430 return err;
431 }
432 return 0;
433}
434
435/*
436 * _DAPM_ Controls
437 */
438
439static int inmixer_event(struct snd_soc_dapm_widget *w,
440 struct snd_kcontrol *kcontrol, int event)
441{
442 u16 reg, fakepower;
443
444 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2);
445 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS);
446
447 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
448 (1 << WM8990_AINLMUX_PWR_BIT))) {
449 reg |= WM8990_AINL_ENA;
450 } else {
451 reg &= ~WM8990_AINL_ENA;
452 }
453
454 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
455 (1 << WM8990_AINRMUX_PWR_BIT))) {
456 reg |= WM8990_AINR_ENA;
457 } else {
458 reg &= ~WM8990_AINL_ENA;
459 }
460 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
461
462 return 0;
463}
464
465static int outmixer_event(struct snd_soc_dapm_widget *w,
466 struct snd_kcontrol *kcontrol, int event)
467{
468 u32 reg_shift = kcontrol->private_value & 0xfff;
469 int ret = 0;
470 u16 reg;
471
472 switch (reg_shift) {
473 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
474 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1);
475 if (reg & WM8990_LDLO) {
476 printk(KERN_WARNING
477 "Cannot set as Output Mixer 1 LDLO Set\n");
478 ret = -1;
479 }
480 break;
481 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
482 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2);
483 if (reg & WM8990_RDRO) {
484 printk(KERN_WARNING
485 "Cannot set as Output Mixer 2 RDRO Set\n");
486 ret = -1;
487 }
488 break;
489 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
490 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
491 if (reg & WM8990_LDSPK) {
492 printk(KERN_WARNING
493 "Cannot set as Speaker Mixer LDSPK Set\n");
494 ret = -1;
495 }
496 break;
497 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
498 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
499 if (reg & WM8990_RDSPK) {
500 printk(KERN_WARNING
501 "Cannot set as Speaker Mixer RDSPK Set\n");
502 ret = -1;
503 }
504 break;
505 }
506
507 return ret;
508}
509
510/* INMIX dB values */
511static const unsigned int in_mix_tlv[] = {
512 TLV_DB_RANGE_HEAD(1),
513 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600),
514};
515
516/* Left In PGA Connections */
517static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
518SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
519SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
520};
521
522static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
523SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
524SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
525};
526
527/* Right In PGA Connections */
528static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
529SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
530SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
531};
532
533static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
534SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
535SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
536};
537
538/* INMIXL */
539static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
540SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
541 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
542SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
543 7, 0, in_mix_tlv),
544SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
545 1, 0),
546SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
547 1, 0),
548};
549
550/* INMIXR */
551static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
552SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
553 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
554SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
555 7, 0, in_mix_tlv),
556SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
557 1, 0),
558SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
559 1, 0),
560};
561
562/* AINLMUX */
563static const char *wm8990_ainlmux[] =
564 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
565
566static const struct soc_enum wm8990_ainlmux_enum =
567SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
568 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
569
570static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
571SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
572
573/* DIFFINL */
574
575/* AINRMUX */
576static const char *wm8990_ainrmux[] =
577 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
578
579static const struct soc_enum wm8990_ainrmux_enum =
580SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
581 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
582
583static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
584SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
585
586/* RXVOICE */
587static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
588SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
589 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
590SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
591 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
592};
593
594/* LOMIX */
595static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
596SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
597 WM8990_LRBLO_BIT, 1, 0),
598SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
599 WM8990_LLBLO_BIT, 1, 0),
600SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
601 WM8990_LRI3LO_BIT, 1, 0),
602SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
603 WM8990_LLI3LO_BIT, 1, 0),
604SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
605 WM8990_LR12LO_BIT, 1, 0),
606SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
607 WM8990_LL12LO_BIT, 1, 0),
608SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
609 WM8990_LDLO_BIT, 1, 0),
610};
611
612/* ROMIX */
613static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
614SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
615 WM8990_RLBRO_BIT, 1, 0),
616SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
617 WM8990_RRBRO_BIT, 1, 0),
618SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
619 WM8990_RLI3RO_BIT, 1, 0),
620SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
621 WM8990_RRI3RO_BIT, 1, 0),
622SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
623 WM8990_RL12RO_BIT, 1, 0),
624SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
625 WM8990_RR12RO_BIT, 1, 0),
626SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
627 WM8990_RDRO_BIT, 1, 0),
628};
629
630/* LONMIX */
631static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
632SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
633 WM8990_LLOPGALON_BIT, 1, 0),
634SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
635 WM8990_LROPGALON_BIT, 1, 0),
636SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
637 WM8990_LOPLON_BIT, 1, 0),
638};
639
640/* LOPMIX */
641static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
642SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
643 WM8990_LR12LOP_BIT, 1, 0),
644SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
645 WM8990_LL12LOP_BIT, 1, 0),
646SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
647 WM8990_LLOPGALOP_BIT, 1, 0),
648};
649
650/* RONMIX */
651static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
652SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
653 WM8990_RROPGARON_BIT, 1, 0),
654SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
655 WM8990_RLOPGARON_BIT, 1, 0),
656SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
657 WM8990_ROPRON_BIT, 1, 0),
658};
659
660/* ROPMIX */
661static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
662SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
663 WM8990_RL12ROP_BIT, 1, 0),
664SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
665 WM8990_RR12ROP_BIT, 1, 0),
666SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
667 WM8990_RROPGAROP_BIT, 1, 0),
668};
669
670/* OUT3MIX */
671static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
672SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
673 WM8990_LI4O3_BIT, 1, 0),
674SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
675 WM8990_LPGAO3_BIT, 1, 0),
676};
677
678/* OUT4MIX */
679static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
680SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
681 WM8990_RPGAO4_BIT, 1, 0),
682SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
683 WM8990_RI4O4_BIT, 1, 0),
684};
685
686/* SPKMIX */
687static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
688SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
689 WM8990_LI2SPK_BIT, 1, 0),
690SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
691 WM8990_LB2SPK_BIT, 1, 0),
692SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
693 WM8990_LOPGASPK_BIT, 1, 0),
694SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
695 WM8990_LDSPK_BIT, 1, 0),
696SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
697 WM8990_RDSPK_BIT, 1, 0),
698SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
699 WM8990_ROPGASPK_BIT, 1, 0),
700SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
701 WM8990_RL12ROP_BIT, 1, 0),
702SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
703 WM8990_RI2SPK_BIT, 1, 0),
704};
705
706static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
707/* Input Side */
708/* Input Lines */
709SND_SOC_DAPM_INPUT("LIN1"),
710SND_SOC_DAPM_INPUT("LIN2"),
711SND_SOC_DAPM_INPUT("LIN3"),
712SND_SOC_DAPM_INPUT("LIN4/RXN"),
713SND_SOC_DAPM_INPUT("RIN3"),
714SND_SOC_DAPM_INPUT("RIN4/RXP"),
715SND_SOC_DAPM_INPUT("RIN1"),
716SND_SOC_DAPM_INPUT("RIN2"),
717SND_SOC_DAPM_INPUT("Internal ADC Source"),
718
719/* DACs */
720SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
721 WM8990_ADCL_ENA_BIT, 0),
722SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
723 WM8990_ADCR_ENA_BIT, 0),
724
725/* Input PGAs */
726SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
727 0, &wm8990_dapm_lin12_pga_controls[0],
728 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
729SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
730 0, &wm8990_dapm_lin34_pga_controls[0],
731 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
732SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
733 0, &wm8990_dapm_rin12_pga_controls[0],
734 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
735SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
736 0, &wm8990_dapm_rin34_pga_controls[0],
737 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
738
739/* INMIXL */
740SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
741 &wm8990_dapm_inmixl_controls[0],
742 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
743 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
744
745/* AINLMUX */
746SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
747 &wm8990_dapm_ainlmux_controls, inmixer_event,
748 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
749
750/* INMIXR */
751SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
752 &wm8990_dapm_inmixr_controls[0],
753 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
754 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
755
756/* AINRMUX */
757SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
758 &wm8990_dapm_ainrmux_controls, inmixer_event,
759 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
760
761/* Output Side */
762/* DACs */
763SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
764 WM8990_DACL_ENA_BIT, 0),
765SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
766 WM8990_DACR_ENA_BIT, 0),
767
768/* LOMIX */
769SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
770 0, &wm8990_dapm_lomix_controls[0],
771 ARRAY_SIZE(wm8990_dapm_lomix_controls),
772 outmixer_event, SND_SOC_DAPM_PRE_REG),
773
774/* LONMIX */
775SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
776 &wm8990_dapm_lonmix_controls[0],
777 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
778
779/* LOPMIX */
780SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
781 &wm8990_dapm_lopmix_controls[0],
782 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
783
784/* OUT3MIX */
785SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
786 &wm8990_dapm_out3mix_controls[0],
787 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
788
789/* SPKMIX */
790SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
791 &wm8990_dapm_spkmix_controls[0],
792 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
793 SND_SOC_DAPM_PRE_REG),
794
795/* OUT4MIX */
796SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
797 &wm8990_dapm_out4mix_controls[0],
798 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
799
800/* ROPMIX */
801SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
802 &wm8990_dapm_ropmix_controls[0],
803 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
804
805/* RONMIX */
806SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
807 &wm8990_dapm_ronmix_controls[0],
808 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
809
810/* ROMIX */
811SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
812 0, &wm8990_dapm_romix_controls[0],
813 ARRAY_SIZE(wm8990_dapm_romix_controls),
814 outmixer_event, SND_SOC_DAPM_PRE_REG),
815
816/* LOUT PGA */
817SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
818 NULL, 0),
819
820/* ROUT PGA */
821SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
822 NULL, 0),
823
824/* LOPGA */
825SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
826 NULL, 0),
827
828/* ROPGA */
829SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
830 NULL, 0),
831
832/* MICBIAS */
833SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
834 WM8990_MICBIAS_ENA_BIT, 0),
835
836SND_SOC_DAPM_OUTPUT("LON"),
837SND_SOC_DAPM_OUTPUT("LOP"),
838SND_SOC_DAPM_OUTPUT("OUT3"),
839SND_SOC_DAPM_OUTPUT("LOUT"),
840SND_SOC_DAPM_OUTPUT("SPKN"),
841SND_SOC_DAPM_OUTPUT("SPKP"),
842SND_SOC_DAPM_OUTPUT("ROUT"),
843SND_SOC_DAPM_OUTPUT("OUT4"),
844SND_SOC_DAPM_OUTPUT("ROP"),
845SND_SOC_DAPM_OUTPUT("RON"),
846
847SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
848};
849
850static const struct snd_soc_dapm_route audio_map[] = {
851 /* Make DACs turn on when playing even if not mixed into any outputs */
852 {"Internal DAC Sink", NULL, "Left DAC"},
853 {"Internal DAC Sink", NULL, "Right DAC"},
854
855 /* Make ADCs turn on when recording even if not mixed from any inputs */
856 {"Left ADC", NULL, "Internal ADC Source"},
857 {"Right ADC", NULL, "Internal ADC Source"},
858
859 /* Input Side */
860 /* LIN12 PGA */
861 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
862 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
863 /* LIN34 PGA */
864 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
865 {"LIN34 PGA", "LIN4 Switch", "LIN4"},
866 /* INMIXL */
867 {"INMIXL", "Record Left Volume", "LOMIX"},
868 {"INMIXL", "LIN2 Volume", "LIN2"},
869 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
870 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
871 /* AILNMUX */
872 {"AILNMUX", "INMIXL Mix", "INMIXL"},
873 {"AILNMUX", "DIFFINL Mix", "LIN12PGA"},
874 {"AILNMUX", "DIFFINL Mix", "LIN34PGA"},
875 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
876 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
877 /* ADC */
878 {"Left ADC", NULL, "AILNMUX"},
879
880 /* RIN12 PGA */
881 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
882 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
883 /* RIN34 PGA */
884 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
885 {"RIN34 PGA", "RIN4 Switch", "RIN4"},
886 /* INMIXL */
887 {"INMIXR", "Record Right Volume", "ROMIX"},
888 {"INMIXR", "RIN2 Volume", "RIN2"},
889 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
890 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
891 /* AIRNMUX */
892 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
893 {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"},
894 {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"},
895 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"},
896 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
897 /* ADC */
898 {"Right ADC", NULL, "AIRNMUX"},
899
900 /* LOMIX */
901 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
902 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
903 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
904 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
905 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
906 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
907 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
908
909 /* ROMIX */
910 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
911 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
912 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
913 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
914 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
915 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
916 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
917
918 /* SPKMIX */
919 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
920 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
921 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
922 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
923 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
924 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
925 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
Mark Brown436a7452008-08-15 16:22:32 +0100926 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
Mark Brownf10485e2008-06-05 13:49:33 +0100927
928 /* LONMIX */
929 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
930 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
931 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
932
933 /* LOPMIX */
934 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
935 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
936 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
937
938 /* OUT3MIX */
939 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"},
940 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
941
942 /* OUT4MIX */
943 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
944 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
945
946 /* RONMIX */
947 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
948 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
949 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
950
951 /* ROPMIX */
952 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
953 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
954 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
955
956 /* Out Mixer PGAs */
957 {"LOPGA", NULL, "LOMIX"},
958 {"ROPGA", NULL, "ROMIX"},
959
960 {"LOUT PGA", NULL, "LOMIX"},
961 {"ROUT PGA", NULL, "ROMIX"},
962
963 /* Output Pins */
964 {"LON", NULL, "LONMIX"},
965 {"LOP", NULL, "LOPMIX"},
966 {"OUT", NULL, "OUT3MIX"},
967 {"LOUT", NULL, "LOUT PGA"},
968 {"SPKN", NULL, "SPKMIX"},
969 {"ROUT", NULL, "ROUT PGA"},
970 {"OUT4", NULL, "OUT4MIX"},
971 {"ROP", NULL, "ROPMIX"},
972 {"RON", NULL, "RONMIX"},
973};
974
975static int wm8990_add_widgets(struct snd_soc_codec *codec)
976{
977 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
978 ARRAY_SIZE(wm8990_dapm_widgets));
979
980 /* set up the WM8990 audio map */
981 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
982
983 snd_soc_dapm_new_widgets(codec);
984 return 0;
985}
986
987/* PLL divisors */
988struct _pll_div {
989 u32 div2;
990 u32 n;
991 u32 k;
992};
993
994/* The size in bits of the pll divide multiplied by 10
995 * to allow rounding later */
996#define FIXED_PLL_SIZE ((1 << 16) * 10)
997
998static void pll_factors(struct _pll_div *pll_div, unsigned int target,
999 unsigned int source)
1000{
1001 u64 Kpart;
1002 unsigned int K, Ndiv, Nmod;
1003
1004
1005 Ndiv = target / source;
1006 if (Ndiv < 6) {
1007 source >>= 1;
1008 pll_div->div2 = 1;
1009 Ndiv = target / source;
1010 } else
1011 pll_div->div2 = 0;
1012
1013 if ((Ndiv < 6) || (Ndiv > 12))
1014 printk(KERN_WARNING
1015 "WM8990 N value outwith recommended range! N = %d\n", Ndiv);
1016
1017 pll_div->n = Ndiv;
1018 Nmod = target % source;
1019 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1020
1021 do_div(Kpart, source);
1022
1023 K = Kpart & 0xFFFFFFFF;
1024
1025 /* Check if we need to round */
1026 if ((K % 10) >= 5)
1027 K += 5;
1028
1029 /* Move down to proper range now rounding is done */
1030 K /= 10;
1031
1032 pll_div->k = K;
1033}
1034
Liam Girdwoode550e172008-07-07 16:07:52 +01001035static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001036 int pll_id, unsigned int freq_in, unsigned int freq_out)
1037{
1038 u16 reg;
1039 struct snd_soc_codec *codec = codec_dai->codec;
1040 struct _pll_div pll_div;
1041
1042 if (freq_in && freq_out) {
1043 pll_factors(&pll_div, freq_out * 4, freq_in);
1044
1045 /* Turn on PLL */
1046 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1047 reg |= WM8990_PLL_ENA;
1048 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1049
1050 /* sysclk comes from PLL */
1051 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2);
1052 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
1053
1054 /* set up N , fractional mode and pre-divisor if neccessary */
1055 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1056 (pll_div.div2?WM8990_PRESCALE:0));
1057 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1058 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1059 } else {
1060 /* Turn on PLL */
1061 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1062 reg &= ~WM8990_PLL_ENA;
1063 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1064 }
1065 return 0;
1066}
1067
1068/*
1069 * Clock after PLL and dividers
1070 */
Liam Girdwoode550e172008-07-07 16:07:52 +01001071static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001072 int clk_id, unsigned int freq, int dir)
1073{
1074 struct snd_soc_codec *codec = codec_dai->codec;
1075 struct wm8990_priv *wm8990 = codec->private_data;
1076
1077 wm8990->sysclk = freq;
1078 return 0;
1079}
1080
1081/*
1082 * Set's ADC and Voice DAC format.
1083 */
Liam Girdwoode550e172008-07-07 16:07:52 +01001084static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001085 unsigned int fmt)
1086{
1087 struct snd_soc_codec *codec = codec_dai->codec;
1088 u16 audio1, audio3;
1089
1090 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1091 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3);
1092
1093 /* set master/slave audio interface */
1094 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1095 case SND_SOC_DAIFMT_CBS_CFS:
1096 audio3 &= ~WM8990_AIF_MSTR1;
1097 break;
1098 case SND_SOC_DAIFMT_CBM_CFM:
1099 audio3 |= WM8990_AIF_MSTR1;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 audio1 &= ~WM8990_AIF_FMT_MASK;
1106
1107 /* interface format */
1108 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1109 case SND_SOC_DAIFMT_I2S:
1110 audio1 |= WM8990_AIF_TMF_I2S;
1111 audio1 &= ~WM8990_AIF_LRCLK_INV;
1112 break;
1113 case SND_SOC_DAIFMT_RIGHT_J:
1114 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1115 audio1 &= ~WM8990_AIF_LRCLK_INV;
1116 break;
1117 case SND_SOC_DAIFMT_LEFT_J:
1118 audio1 |= WM8990_AIF_TMF_LEFTJ;
1119 audio1 &= ~WM8990_AIF_LRCLK_INV;
1120 break;
1121 case SND_SOC_DAIFMT_DSP_A:
1122 audio1 |= WM8990_AIF_TMF_DSP;
1123 audio1 &= ~WM8990_AIF_LRCLK_INV;
1124 break;
1125 case SND_SOC_DAIFMT_DSP_B:
1126 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1127 break;
1128 default:
1129 return -EINVAL;
1130 }
1131
1132 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1133 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1134 return 0;
1135}
1136
Liam Girdwoode550e172008-07-07 16:07:52 +01001137static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001138 int div_id, int div)
1139{
1140 struct snd_soc_codec *codec = codec_dai->codec;
1141 u16 reg;
1142
1143 switch (div_id) {
1144 case WM8990_MCLK_DIV:
1145 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1146 ~WM8990_MCLK_DIV_MASK;
1147 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1148 break;
1149 case WM8990_DACCLK_DIV:
1150 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1151 ~WM8990_DAC_CLKDIV_MASK;
1152 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1153 break;
1154 case WM8990_ADCCLK_DIV:
1155 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1156 ~WM8990_ADC_CLKDIV_MASK;
1157 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1158 break;
1159 case WM8990_BCLK_DIV:
1160 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) &
1161 ~WM8990_BCLK_DIV_MASK;
1162 wm8990_write(codec, WM8990_CLOCKING_1, reg | div);
1163 break;
1164 default:
1165 return -EINVAL;
1166 }
1167
1168 return 0;
1169}
1170
1171/*
1172 * Set PCM DAI bit size and sample rate.
1173 */
1174static int wm8990_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +00001175 struct snd_pcm_hw_params *params,
1176 struct snd_soc_dai *dai)
Mark Brownf10485e2008-06-05 13:49:33 +01001177{
1178 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1179 struct snd_soc_device *socdev = rtd->socdev;
1180 struct snd_soc_codec *codec = socdev->codec;
1181 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1182
1183 audio1 &= ~WM8990_AIF_WL_MASK;
1184 /* bit size */
1185 switch (params_format(params)) {
1186 case SNDRV_PCM_FORMAT_S16_LE:
1187 break;
1188 case SNDRV_PCM_FORMAT_S20_3LE:
1189 audio1 |= WM8990_AIF_WL_20BITS;
1190 break;
1191 case SNDRV_PCM_FORMAT_S24_LE:
1192 audio1 |= WM8990_AIF_WL_24BITS;
1193 break;
1194 case SNDRV_PCM_FORMAT_S32_LE:
1195 audio1 |= WM8990_AIF_WL_32BITS;
1196 break;
1197 }
1198
1199 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1200 return 0;
1201}
1202
Liam Girdwoode550e172008-07-07 16:07:52 +01001203static int wm8990_mute(struct snd_soc_dai *dai, int mute)
Mark Brownf10485e2008-06-05 13:49:33 +01001204{
1205 struct snd_soc_codec *codec = dai->codec;
1206 u16 val;
1207
1208 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1209
1210 if (mute)
1211 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1212 else
1213 wm8990_write(codec, WM8990_DAC_CTRL, val);
1214
1215 return 0;
1216}
1217
1218static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1219 enum snd_soc_bias_level level)
1220{
1221 u16 val;
1222
1223 switch (level) {
1224 case SND_SOC_BIAS_ON:
1225 break;
Mark Brown2adb9832008-11-17 17:11:14 +00001226
Mark Brownf10485e2008-06-05 13:49:33 +01001227 case SND_SOC_BIAS_PREPARE:
Mark Brown2adb9832008-11-17 17:11:14 +00001228 /* VMID=2*50k */
1229 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) &
1230 ~WM8990_VMID_MODE_MASK;
1231 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
Mark Brownf10485e2008-06-05 13:49:33 +01001232 break;
Mark Brown2adb9832008-11-17 17:11:14 +00001233
Mark Brownf10485e2008-06-05 13:49:33 +01001234 case SND_SOC_BIAS_STANDBY:
1235 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1236 /* Enable all output discharge bits */
1237 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1238 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1239 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1240 WM8990_DIS_ROUT);
1241
1242 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1243 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1244 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1245 WM8990_VMIDTOG);
1246
1247 /* Delay to allow output caps to discharge */
1248 msleep(msecs_to_jiffies(300));
1249
1250 /* Disable VMIDTOG */
1251 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1252 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1253
1254 /* disable all output discharge bits */
1255 wm8990_write(codec, WM8990_ANTIPOP1, 0);
1256
1257 /* Enable outputs */
1258 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1259
1260 msleep(msecs_to_jiffies(50));
1261
1262 /* Enable VMID at 2x50k */
1263 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1264
1265 msleep(msecs_to_jiffies(100));
1266
1267 /* Enable VREF */
1268 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1269
1270 msleep(msecs_to_jiffies(600));
1271
1272 /* Enable BUFIOEN */
1273 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1274 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1275 WM8990_BUFIOEN);
1276
1277 /* Disable outputs */
1278 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1279
1280 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1281 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
Mark Brownf10485e2008-06-05 13:49:33 +01001282
Mark Brownbe1b87c2008-11-17 17:09:34 +00001283 /* Enable workaround for ADC clocking issue. */
1284 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1285 wm8990_write(codec, WM8990_EXT_CTL1, 0xa003);
1286 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0);
Mark Brownf10485e2008-06-05 13:49:33 +01001287 }
Mark Brown2adb9832008-11-17 17:11:14 +00001288
1289 /* VMID=2*250k */
1290 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) &
1291 ~WM8990_VMID_MODE_MASK;
1292 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
Mark Brownf10485e2008-06-05 13:49:33 +01001293 break;
1294
1295 case SND_SOC_BIAS_OFF:
1296 /* Enable POBCTRL and SOFT_ST */
1297 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1298 WM8990_POBCTRL | WM8990_BUFIOEN);
1299
1300 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1301 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1302 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1303 WM8990_BUFIOEN);
1304
1305 /* mute DAC */
1306 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL);
1307 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1308
1309 /* Enable any disabled outputs */
1310 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1311
1312 /* Disable VMID */
1313 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1314
1315 msleep(msecs_to_jiffies(300));
1316
1317 /* Enable all output discharge bits */
1318 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1319 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1320 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1321 WM8990_DIS_ROUT);
1322
1323 /* Disable VREF */
1324 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1325
1326 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1327 wm8990_write(codec, WM8990_ANTIPOP2, 0x0);
1328 break;
1329 }
1330
1331 codec->bias_level = level;
1332 return 0;
1333}
1334
1335#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1336 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1337 SNDRV_PCM_RATE_48000)
1338
1339#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1340 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1341
1342/*
1343 * The WM8990 supports 2 different and mutually exclusive DAI
1344 * configurations.
1345 *
1346 * 1. ADC/DAC on Primary Interface
1347 * 2. ADC on Primary Interface/DAC on secondary
1348 */
Liam Girdwoode550e172008-07-07 16:07:52 +01001349struct snd_soc_dai wm8990_dai = {
Mark Brownf10485e2008-06-05 13:49:33 +01001350/* ADC/DAC on primary */
1351 .name = "WM8990 ADC/DAC Primary",
1352 .id = 1,
1353 .playback = {
1354 .stream_name = "Playback",
1355 .channels_min = 1,
1356 .channels_max = 2,
1357 .rates = WM8990_RATES,
1358 .formats = WM8990_FORMATS,},
1359 .capture = {
1360 .stream_name = "Capture",
1361 .channels_min = 1,
1362 .channels_max = 2,
1363 .rates = WM8990_RATES,
1364 .formats = WM8990_FORMATS,},
1365 .ops = {
Mark Browndee89c42008-11-18 22:11:38 +00001366 .hw_params = wm8990_hw_params,
Mark Brownf10485e2008-06-05 13:49:33 +01001367 .digital_mute = wm8990_mute,
1368 .set_fmt = wm8990_set_dai_fmt,
1369 .set_clkdiv = wm8990_set_dai_clkdiv,
1370 .set_pll = wm8990_set_dai_pll,
1371 .set_sysclk = wm8990_set_dai_sysclk,
1372 },
1373};
1374EXPORT_SYMBOL_GPL(wm8990_dai);
1375
1376static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
1377{
1378 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1379 struct snd_soc_codec *codec = socdev->codec;
1380
1381 /* we only need to suspend if we are a valid card */
1382 if (!codec->card)
1383 return 0;
1384
1385 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1386 return 0;
1387}
1388
1389static int wm8990_resume(struct platform_device *pdev)
1390{
1391 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1392 struct snd_soc_codec *codec = socdev->codec;
1393 int i;
1394 u8 data[2];
1395 u16 *cache = codec->reg_cache;
1396
1397 /* we only need to resume if we are a valid card */
1398 if (!codec->card)
1399 return 0;
1400
1401 /* Sync reg_cache with the hardware */
1402 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1403 if (i + 1 == WM8990_RESET)
1404 continue;
1405 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1406 data[1] = cache[i] & 0x00ff;
1407 codec->hw_write(codec->control_data, data, 2);
1408 }
1409
1410 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1411 return 0;
1412}
1413
1414/*
1415 * initialise the WM8990 driver
1416 * register the mixer and dsp interfaces with the kernel
1417 */
1418static int wm8990_init(struct snd_soc_device *socdev)
1419{
1420 struct snd_soc_codec *codec = socdev->codec;
1421 u16 reg;
1422 int ret = 0;
1423
1424 codec->name = "WM8990";
1425 codec->owner = THIS_MODULE;
1426 codec->read = wm8990_read_reg_cache;
1427 codec->write = wm8990_write;
1428 codec->set_bias_level = wm8990_set_bias_level;
1429 codec->dai = &wm8990_dai;
1430 codec->num_dai = 2;
1431 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
1432 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
1433
1434 if (codec->reg_cache == NULL)
1435 return -ENOMEM;
1436
1437 wm8990_reset(codec);
1438
1439 /* register pcms */
1440 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1441 if (ret < 0) {
1442 printk(KERN_ERR "wm8990: failed to create pcms\n");
1443 goto pcm_err;
1444 }
1445
1446 /* charge output caps */
1447 codec->bias_level = SND_SOC_BIAS_OFF;
1448 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1449
1450 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4);
1451 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1452
1453 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) &
1454 ~WM8990_GPIO1_SEL_MASK;
1455 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1456
1457 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1458 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1459
1460 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1461 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1462
1463 wm8990_add_controls(codec);
1464 wm8990_add_widgets(codec);
Mark Brown968a6022008-11-28 11:49:07 +00001465 ret = snd_soc_init_card(socdev);
Mark Brownf10485e2008-06-05 13:49:33 +01001466 if (ret < 0) {
1467 printk(KERN_ERR "wm8990: failed to register card\n");
1468 goto card_err;
1469 }
1470 return ret;
1471
1472card_err:
1473 snd_soc_free_pcms(socdev);
1474 snd_soc_dapm_free(socdev);
1475pcm_err:
1476 kfree(codec->reg_cache);
1477 return ret;
1478}
1479
1480/* If the i2c layer weren't so broken, we could pass this kind of data
1481 around */
1482static struct snd_soc_device *wm8990_socdev;
1483
1484#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1485
1486/*
1487 * WM891 2 wire address is determined by GPIO5
1488 * state during powerup.
1489 * low = 0x34
1490 * high = 0x36
1491 */
Mark Brownf10485e2008-06-05 13:49:33 +01001492
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001493static int wm8990_i2c_probe(struct i2c_client *i2c,
1494 const struct i2c_device_id *id)
Mark Brownf10485e2008-06-05 13:49:33 +01001495{
1496 struct snd_soc_device *socdev = wm8990_socdev;
Mark Brownf10485e2008-06-05 13:49:33 +01001497 struct snd_soc_codec *codec = socdev->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001498 int ret;
1499
Mark Brownf10485e2008-06-05 13:49:33 +01001500 i2c_set_clientdata(i2c, codec);
1501 codec->control_data = i2c;
1502
Mark Brownf10485e2008-06-05 13:49:33 +01001503 ret = wm8990_init(socdev);
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001504 if (ret < 0)
Mark Browna5c95e92008-06-23 14:51:29 +01001505 pr_err("failed to initialise WM8990\n");
Mark Brownf10485e2008-06-05 13:49:33 +01001506
Mark Brownf10485e2008-06-05 13:49:33 +01001507 return ret;
1508}
1509
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001510static int wm8990_i2c_remove(struct i2c_client *client)
Mark Brownf10485e2008-06-05 13:49:33 +01001511{
1512 struct snd_soc_codec *codec = i2c_get_clientdata(client);
Mark Brownf10485e2008-06-05 13:49:33 +01001513 kfree(codec->reg_cache);
Mark Brownf10485e2008-06-05 13:49:33 +01001514 return 0;
1515}
1516
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001517static const struct i2c_device_id wm8990_i2c_id[] = {
1518 { "wm8990", 0 },
1519 { }
1520};
1521MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
Mark Brownf10485e2008-06-05 13:49:33 +01001522
1523static struct i2c_driver wm8990_i2c_driver = {
1524 .driver = {
1525 .name = "WM8990 I2C Codec",
1526 .owner = THIS_MODULE,
1527 },
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001528 .probe = wm8990_i2c_probe,
1529 .remove = wm8990_i2c_remove,
1530 .id_table = wm8990_i2c_id,
Mark Brownf10485e2008-06-05 13:49:33 +01001531};
1532
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001533static int wm8990_add_i2c_device(struct platform_device *pdev,
1534 const struct wm8990_setup_data *setup)
1535{
1536 struct i2c_board_info info;
1537 struct i2c_adapter *adapter;
1538 struct i2c_client *client;
1539 int ret;
1540
1541 ret = i2c_add_driver(&wm8990_i2c_driver);
1542 if (ret != 0) {
1543 dev_err(&pdev->dev, "can't add i2c driver\n");
1544 return ret;
1545 }
1546
1547 memset(&info, 0, sizeof(struct i2c_board_info));
1548 info.addr = setup->i2c_address;
1549 strlcpy(info.type, "wm8990", I2C_NAME_SIZE);
1550
1551 adapter = i2c_get_adapter(setup->i2c_bus);
1552 if (!adapter) {
1553 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1554 setup->i2c_bus);
1555 goto err_driver;
1556 }
1557
1558 client = i2c_new_device(adapter, &info);
1559 i2c_put_adapter(adapter);
1560 if (!client) {
1561 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1562 (unsigned int)info.addr);
1563 goto err_driver;
1564 }
1565
1566 return 0;
1567
1568err_driver:
1569 i2c_del_driver(&wm8990_i2c_driver);
1570 return -ENODEV;
1571}
Mark Brownf10485e2008-06-05 13:49:33 +01001572#endif
1573
1574static int wm8990_probe(struct platform_device *pdev)
1575{
1576 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1577 struct wm8990_setup_data *setup;
1578 struct snd_soc_codec *codec;
1579 struct wm8990_priv *wm8990;
Mark Brownb7c9d852008-09-01 18:47:04 +01001580 int ret;
Mark Brownf10485e2008-06-05 13:49:33 +01001581
Mark Browna5c95e92008-06-23 14:51:29 +01001582 pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION);
Mark Brownf10485e2008-06-05 13:49:33 +01001583
1584 setup = socdev->codec_data;
1585 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1586 if (codec == NULL)
1587 return -ENOMEM;
1588
1589 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1590 if (wm8990 == NULL) {
1591 kfree(codec);
1592 return -ENOMEM;
1593 }
1594
1595 codec->private_data = wm8990;
1596 socdev->codec = codec;
1597 mutex_init(&codec->mutex);
1598 INIT_LIST_HEAD(&codec->dapm_widgets);
1599 INIT_LIST_HEAD(&codec->dapm_paths);
1600 wm8990_socdev = socdev;
1601
Mark Brownb7c9d852008-09-01 18:47:04 +01001602 ret = -ENODEV;
1603
Mark Brownf10485e2008-06-05 13:49:33 +01001604#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1605 if (setup->i2c_address) {
Mark Brownf10485e2008-06-05 13:49:33 +01001606 codec->hw_write = (hw_write_t)i2c_master_send;
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001607 ret = wm8990_add_i2c_device(pdev, setup);
Mark Brownf10485e2008-06-05 13:49:33 +01001608 }
Mark Brownf10485e2008-06-05 13:49:33 +01001609#endif
Jean Delvare3051e412008-08-25 11:49:20 +01001610
1611 if (ret != 0) {
1612 kfree(codec->private_data);
1613 kfree(codec);
1614 }
Mark Brownf10485e2008-06-05 13:49:33 +01001615 return ret;
1616}
1617
1618/* power down chip */
1619static int wm8990_remove(struct platform_device *pdev)
1620{
1621 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1622 struct snd_soc_codec *codec = socdev->codec;
1623
1624 if (codec->control_data)
1625 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1626 snd_soc_free_pcms(socdev);
1627 snd_soc_dapm_free(socdev);
1628#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001629 i2c_unregister_device(codec->control_data);
Mark Brownf10485e2008-06-05 13:49:33 +01001630 i2c_del_driver(&wm8990_i2c_driver);
1631#endif
1632 kfree(codec->private_data);
1633 kfree(codec);
1634
1635 return 0;
1636}
1637
1638struct snd_soc_codec_device soc_codec_dev_wm8990 = {
1639 .probe = wm8990_probe,
1640 .remove = wm8990_remove,
1641 .suspend = wm8990_suspend,
1642 .resume = wm8990_resume,
1643};
1644EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
1645
Takashi Iwaic9b3a402008-12-10 07:47:22 +01001646static int __init wm8990_modinit(void)
Mark Brown64089b82008-12-08 19:17:58 +00001647{
1648 return snd_soc_register_dai(&wm8990_dai);
1649}
1650module_init(wm8990_modinit);
1651
1652static void __exit wm8990_exit(void)
1653{
1654 snd_soc_unregister_dai(&wm8990_dai);
1655}
1656module_exit(wm8990_exit);
1657
Mark Brownf10485e2008-06-05 13:49:33 +01001658MODULE_DESCRIPTION("ASoC WM8990 driver");
1659MODULE_AUTHOR("Liam Girdwood");
1660MODULE_LICENSE("GPL");