Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012-2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * Daniel Vetter <daniel.vetter@ffwll.ch> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/vgaarb.h> |
| 31 | |
| 32 | #include "i915_drv.h" |
| 33 | #include "intel_drv.h" |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 34 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 35 | /** |
| 36 | * DOC: runtime pm |
| 37 | * |
| 38 | * The i915 driver supports dynamic enabling and disabling of entire hardware |
| 39 | * blocks at runtime. This is especially important on the display side where |
| 40 | * software is supposed to control many power gates manually on recent hardware, |
| 41 | * since on the GT side a lot of the power management is done by the hardware. |
| 42 | * But even there some manual control at the device level is required. |
| 43 | * |
| 44 | * Since i915 supports a diverse set of platforms with a unified codebase and |
| 45 | * hardware engineers just love to shuffle functionality around between power |
| 46 | * domains there's a sizeable amount of indirection required. This file provides |
| 47 | * generic functions to the driver for grabbing and releasing references for |
| 48 | * abstract power domains. It then maps those to the actual power wells |
| 49 | * present for a given platform. |
| 50 | */ |
| 51 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
| 53 | for (i = 0; \ |
| 54 | i < (power_domains)->power_well_count && \ |
| 55 | ((power_well) = &(power_domains)->power_wells[i]); \ |
| 56 | i++) \ |
| 57 | if ((power_well)->domains & (domain_mask)) |
| 58 | |
| 59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ |
| 60 | for (i = (power_domains)->power_well_count - 1; \ |
| 61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
| 62 | i--) \ |
| 63 | if ((power_well)->domains & (domain_mask)) |
| 64 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 65 | /* |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 66 | * We should only use the power well if we explicitly asked the hardware to |
| 67 | * enable it, so check if it's enabled and also check if we've requested it to |
| 68 | * be enabled. |
| 69 | */ |
| 70 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
| 71 | struct i915_power_well *power_well) |
| 72 | { |
| 73 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 74 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); |
| 75 | } |
| 76 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 77 | /** |
| 78 | * __intel_display_power_is_enabled - unlocked check for a power domain |
| 79 | * @dev_priv: i915 device instance |
| 80 | * @domain: power domain to check |
| 81 | * |
| 82 | * This is the unlocked version of intel_display_power_is_enabled() and should |
| 83 | * only be used from error capture and recovery code where deadlocks are |
| 84 | * possible. |
| 85 | * |
| 86 | * Returns: |
| 87 | * True when the power domain is enabled, false otherwise. |
| 88 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 89 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 90 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 91 | { |
| 92 | struct i915_power_domains *power_domains; |
| 93 | struct i915_power_well *power_well; |
| 94 | bool is_enabled; |
| 95 | int i; |
| 96 | |
| 97 | if (dev_priv->pm.suspended) |
| 98 | return false; |
| 99 | |
| 100 | power_domains = &dev_priv->power_domains; |
| 101 | |
| 102 | is_enabled = true; |
| 103 | |
| 104 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 105 | if (power_well->always_on) |
| 106 | continue; |
| 107 | |
| 108 | if (!power_well->hw_enabled) { |
| 109 | is_enabled = false; |
| 110 | break; |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | return is_enabled; |
| 115 | } |
| 116 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 117 | /** |
Damien Lespiau | f61ccae | 2014-11-25 13:45:41 +0000 | [diff] [blame] | 118 | * intel_display_power_is_enabled - check for a power domain |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 119 | * @dev_priv: i915 device instance |
| 120 | * @domain: power domain to check |
| 121 | * |
| 122 | * This function can be used to check the hw power domain state. It is mostly |
| 123 | * used in hardware state readout functions. Everywhere else code should rely |
| 124 | * upon explicit power domain reference counting to ensure that the hardware |
| 125 | * block is powered up before accessing it. |
| 126 | * |
| 127 | * Callers must hold the relevant modesetting locks to ensure that concurrent |
| 128 | * threads can't disable the power well while the caller tries to read a few |
| 129 | * registers. |
| 130 | * |
| 131 | * Returns: |
| 132 | * True when the power domain is enabled, false otherwise. |
| 133 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 134 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 135 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 136 | { |
| 137 | struct i915_power_domains *power_domains; |
| 138 | bool ret; |
| 139 | |
| 140 | power_domains = &dev_priv->power_domains; |
| 141 | |
| 142 | mutex_lock(&power_domains->lock); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 143 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 144 | mutex_unlock(&power_domains->lock); |
| 145 | |
| 146 | return ret; |
| 147 | } |
| 148 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 149 | /** |
| 150 | * intel_display_set_init_power - set the initial power domain state |
| 151 | * @dev_priv: i915 device instance |
| 152 | * @enable: whether to enable or disable the initial power domain state |
| 153 | * |
| 154 | * For simplicity our driver load/unload and system suspend/resume code assumes |
| 155 | * that all power domains are always enabled. This functions controls the state |
| 156 | * of this little hack. While the initial power domain state is enabled runtime |
| 157 | * pm is effectively disabled. |
| 158 | */ |
Daniel Vetter | d9bc89d9 | 2014-09-30 10:56:40 +0200 | [diff] [blame] | 159 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
| 160 | bool enable) |
| 161 | { |
| 162 | if (dev_priv->power_domains.init_power_on == enable) |
| 163 | return; |
| 164 | |
| 165 | if (enable) |
| 166 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 167 | else |
| 168 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
| 169 | |
| 170 | dev_priv->power_domains.init_power_on = enable; |
| 171 | } |
| 172 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 173 | /* |
| 174 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 175 | * when not needed anymore. We have 4 registers that can request the power well |
| 176 | * to be enabled, and it will only be disabled if none of the registers is |
| 177 | * requesting it to be enabled. |
| 178 | */ |
| 179 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 180 | { |
| 181 | struct drm_device *dev = dev_priv->dev; |
| 182 | |
| 183 | /* |
| 184 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 185 | * we'll get unclaimed register interrupts. This stops after we write |
| 186 | * anything to the VGA MSR register. The vgacon module uses this |
| 187 | * register all the time, so if we unbind our driver and, as a |
| 188 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 189 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 190 | * sure vgacon can keep working normally without triggering interrupts |
| 191 | * and error messages. |
| 192 | */ |
| 193 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 194 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 195 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 196 | |
| 197 | if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) |
| 198 | gen8_irq_power_well_post_enable(dev_priv); |
| 199 | } |
| 200 | |
| 201 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
| 202 | struct i915_power_well *power_well, bool enable) |
| 203 | { |
| 204 | bool is_enabled, enable_requested; |
| 205 | uint32_t tmp; |
| 206 | |
| 207 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 208 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
| 209 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; |
| 210 | |
| 211 | if (enable) { |
| 212 | if (!enable_requested) |
| 213 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
| 214 | HSW_PWR_WELL_ENABLE_REQUEST); |
| 215 | |
| 216 | if (!is_enabled) { |
| 217 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 218 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
| 219 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
| 220 | DRM_ERROR("Timeout enabling power well\n"); |
Paulo Zanoni | 6d729bf | 2014-10-07 16:11:11 -0300 | [diff] [blame] | 221 | hsw_power_well_post_enable(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 222 | } |
| 223 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 224 | } else { |
| 225 | if (enable_requested) { |
| 226 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
| 227 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
| 228 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
| 229 | } |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 234 | struct i915_power_well *power_well) |
| 235 | { |
| 236 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 237 | |
| 238 | /* |
| 239 | * We're taking over the BIOS, so clear any requests made by it since |
| 240 | * the driver is in charge now. |
| 241 | */ |
| 242 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) |
| 243 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 244 | } |
| 245 | |
| 246 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, |
| 247 | struct i915_power_well *power_well) |
| 248 | { |
| 249 | hsw_set_power_well(dev_priv, power_well, true); |
| 250 | } |
| 251 | |
| 252 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, |
| 253 | struct i915_power_well *power_well) |
| 254 | { |
| 255 | hsw_set_power_well(dev_priv, power_well, false); |
| 256 | } |
| 257 | |
| 258 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
| 259 | struct i915_power_well *power_well) |
| 260 | { |
| 261 | } |
| 262 | |
| 263 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, |
| 264 | struct i915_power_well *power_well) |
| 265 | { |
| 266 | return true; |
| 267 | } |
| 268 | |
| 269 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
| 270 | struct i915_power_well *power_well, bool enable) |
| 271 | { |
| 272 | enum punit_power_well power_well_id = power_well->data; |
| 273 | u32 mask; |
| 274 | u32 state; |
| 275 | u32 ctrl; |
| 276 | |
| 277 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 278 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : |
| 279 | PUNIT_PWRGT_PWR_GATE(power_well_id); |
| 280 | |
| 281 | mutex_lock(&dev_priv->rps.hw_lock); |
| 282 | |
| 283 | #define COND \ |
| 284 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) |
| 285 | |
| 286 | if (COND) |
| 287 | goto out; |
| 288 | |
| 289 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); |
| 290 | ctrl &= ~mask; |
| 291 | ctrl |= state; |
| 292 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
| 293 | |
| 294 | if (wait_for(COND, 100)) |
| 295 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
| 296 | state, |
| 297 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
| 298 | |
| 299 | #undef COND |
| 300 | |
| 301 | out: |
| 302 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 303 | } |
| 304 | |
| 305 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 306 | struct i915_power_well *power_well) |
| 307 | { |
| 308 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 309 | } |
| 310 | |
| 311 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, |
| 312 | struct i915_power_well *power_well) |
| 313 | { |
| 314 | vlv_set_power_well(dev_priv, power_well, true); |
| 315 | } |
| 316 | |
| 317 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, |
| 318 | struct i915_power_well *power_well) |
| 319 | { |
| 320 | vlv_set_power_well(dev_priv, power_well, false); |
| 321 | } |
| 322 | |
| 323 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, |
| 324 | struct i915_power_well *power_well) |
| 325 | { |
| 326 | int power_well_id = power_well->data; |
| 327 | bool enabled = false; |
| 328 | u32 mask; |
| 329 | u32 state; |
| 330 | u32 ctrl; |
| 331 | |
| 332 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 333 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); |
| 334 | |
| 335 | mutex_lock(&dev_priv->rps.hw_lock); |
| 336 | |
| 337 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; |
| 338 | /* |
| 339 | * We only ever set the power-on and power-gate states, anything |
| 340 | * else is unexpected. |
| 341 | */ |
| 342 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && |
| 343 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); |
| 344 | if (state == ctrl) |
| 345 | enabled = true; |
| 346 | |
| 347 | /* |
| 348 | * A transient state at this point would mean some unexpected party |
| 349 | * is poking at the power controls too. |
| 350 | */ |
| 351 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; |
| 352 | WARN_ON(ctrl != state); |
| 353 | |
| 354 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 355 | |
| 356 | return enabled; |
| 357 | } |
| 358 | |
| 359 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
| 360 | struct i915_power_well *power_well) |
| 361 | { |
| 362 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 363 | |
| 364 | vlv_set_power_well(dev_priv, power_well, true); |
| 365 | |
| 366 | spin_lock_irq(&dev_priv->irq_lock); |
| 367 | valleyview_enable_display_irqs(dev_priv); |
| 368 | spin_unlock_irq(&dev_priv->irq_lock); |
| 369 | |
| 370 | /* |
| 371 | * During driver initialization/resume we can avoid restoring the |
| 372 | * part of the HW/SW state that will be inited anyway explicitly. |
| 373 | */ |
| 374 | if (dev_priv->power_domains.initializing) |
| 375 | return; |
| 376 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 377 | intel_hpd_init(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 378 | |
| 379 | i915_redisable_vga_power_on(dev_priv->dev); |
| 380 | } |
| 381 | |
| 382 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
| 383 | struct i915_power_well *power_well) |
| 384 | { |
| 385 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 386 | |
| 387 | spin_lock_irq(&dev_priv->irq_lock); |
| 388 | valleyview_disable_display_irqs(dev_priv); |
| 389 | spin_unlock_irq(&dev_priv->irq_lock); |
| 390 | |
| 391 | vlv_set_power_well(dev_priv, power_well, false); |
| 392 | |
| 393 | vlv_power_sequencer_reset(dev_priv); |
| 394 | } |
| 395 | |
| 396 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 397 | struct i915_power_well *power_well) |
| 398 | { |
| 399 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 400 | |
| 401 | /* |
| 402 | * Enable the CRI clock source so we can get at the |
| 403 | * display and the reference clock for VGA |
| 404 | * hotplug / manual detection. |
| 405 | */ |
| 406 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 407 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 408 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 409 | |
| 410 | vlv_set_power_well(dev_priv, power_well, true); |
| 411 | |
| 412 | /* |
| 413 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
| 414 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
| 415 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
| 416 | * b. The other bits such as sfr settings / modesel may all |
| 417 | * be set to 0. |
| 418 | * |
| 419 | * This should only be done on init and resume from S3 with |
| 420 | * both PLLs disabled, or we risk losing DPIO and PLL |
| 421 | * synchronization. |
| 422 | */ |
| 423 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
| 424 | } |
| 425 | |
| 426 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 427 | struct i915_power_well *power_well) |
| 428 | { |
| 429 | enum pipe pipe; |
| 430 | |
| 431 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 432 | |
| 433 | for_each_pipe(dev_priv, pipe) |
| 434 | assert_pll_disabled(dev_priv, pipe); |
| 435 | |
| 436 | /* Assert common reset */ |
| 437 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
| 438 | |
| 439 | vlv_set_power_well(dev_priv, power_well, false); |
| 440 | } |
| 441 | |
| 442 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 443 | struct i915_power_well *power_well) |
| 444 | { |
| 445 | enum dpio_phy phy; |
| 446 | |
| 447 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 448 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 449 | |
| 450 | /* |
| 451 | * Enable the CRI clock source so we can get at the |
| 452 | * display and the reference clock for VGA |
| 453 | * hotplug / manual detection. |
| 454 | */ |
| 455 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 456 | phy = DPIO_PHY0; |
| 457 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 458 | DPLL_REFA_CLK_ENABLE_VLV); |
| 459 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 460 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 461 | } else { |
| 462 | phy = DPIO_PHY1; |
| 463 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | |
| 464 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 465 | } |
| 466 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 467 | vlv_set_power_well(dev_priv, power_well, true); |
| 468 | |
| 469 | /* Poll for phypwrgood signal */ |
| 470 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
| 471 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
| 472 | |
| 473 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | |
| 474 | PHY_COM_LANE_RESET_DEASSERT(phy)); |
| 475 | } |
| 476 | |
| 477 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 478 | struct i915_power_well *power_well) |
| 479 | { |
| 480 | enum dpio_phy phy; |
| 481 | |
| 482 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 483 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 484 | |
| 485 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 486 | phy = DPIO_PHY0; |
| 487 | assert_pll_disabled(dev_priv, PIPE_A); |
| 488 | assert_pll_disabled(dev_priv, PIPE_B); |
| 489 | } else { |
| 490 | phy = DPIO_PHY1; |
| 491 | assert_pll_disabled(dev_priv, PIPE_C); |
| 492 | } |
| 493 | |
| 494 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & |
| 495 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); |
| 496 | |
| 497 | vlv_set_power_well(dev_priv, power_well, false); |
| 498 | } |
| 499 | |
| 500 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, |
| 501 | struct i915_power_well *power_well) |
| 502 | { |
| 503 | enum pipe pipe = power_well->data; |
| 504 | bool enabled; |
| 505 | u32 state, ctrl; |
| 506 | |
| 507 | mutex_lock(&dev_priv->rps.hw_lock); |
| 508 | |
| 509 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); |
| 510 | /* |
| 511 | * We only ever set the power-on and power-gate states, anything |
| 512 | * else is unexpected. |
| 513 | */ |
| 514 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); |
| 515 | enabled = state == DP_SSS_PWR_ON(pipe); |
| 516 | |
| 517 | /* |
| 518 | * A transient state at this point would mean some unexpected party |
| 519 | * is poking at the power controls too. |
| 520 | */ |
| 521 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); |
| 522 | WARN_ON(ctrl << 16 != state); |
| 523 | |
| 524 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 525 | |
| 526 | return enabled; |
| 527 | } |
| 528 | |
| 529 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, |
| 530 | struct i915_power_well *power_well, |
| 531 | bool enable) |
| 532 | { |
| 533 | enum pipe pipe = power_well->data; |
| 534 | u32 state; |
| 535 | u32 ctrl; |
| 536 | |
| 537 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); |
| 538 | |
| 539 | mutex_lock(&dev_priv->rps.hw_lock); |
| 540 | |
| 541 | #define COND \ |
| 542 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) |
| 543 | |
| 544 | if (COND) |
| 545 | goto out; |
| 546 | |
| 547 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 548 | ctrl &= ~DP_SSC_MASK(pipe); |
| 549 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
| 550 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
| 551 | |
| 552 | if (wait_for(COND, 100)) |
| 553 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
| 554 | state, |
| 555 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
| 556 | |
| 557 | #undef COND |
| 558 | |
| 559 | out: |
| 560 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 561 | } |
| 562 | |
| 563 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 564 | struct i915_power_well *power_well) |
| 565 | { |
| 566 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
| 567 | } |
| 568 | |
| 569 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
| 570 | struct i915_power_well *power_well) |
| 571 | { |
| 572 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 573 | power_well->data != PIPE_B && |
| 574 | power_well->data != PIPE_C); |
| 575 | |
| 576 | chv_set_pipe_power_well(dev_priv, power_well, true); |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 577 | |
| 578 | if (power_well->data == PIPE_A) { |
| 579 | spin_lock_irq(&dev_priv->irq_lock); |
| 580 | valleyview_enable_display_irqs(dev_priv); |
| 581 | spin_unlock_irq(&dev_priv->irq_lock); |
| 582 | |
| 583 | /* |
| 584 | * During driver initialization/resume we can avoid restoring the |
| 585 | * part of the HW/SW state that will be inited anyway explicitly. |
| 586 | */ |
| 587 | if (dev_priv->power_domains.initializing) |
| 588 | return; |
| 589 | |
| 590 | intel_hpd_init(dev_priv); |
| 591 | |
| 592 | i915_redisable_vga_power_on(dev_priv->dev); |
| 593 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
| 597 | struct i915_power_well *power_well) |
| 598 | { |
| 599 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 600 | power_well->data != PIPE_B && |
| 601 | power_well->data != PIPE_C); |
| 602 | |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 603 | if (power_well->data == PIPE_A) { |
| 604 | spin_lock_irq(&dev_priv->irq_lock); |
| 605 | valleyview_disable_display_irqs(dev_priv); |
| 606 | spin_unlock_irq(&dev_priv->irq_lock); |
| 607 | } |
| 608 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 609 | chv_set_pipe_power_well(dev_priv, power_well, false); |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 610 | |
| 611 | if (power_well->data == PIPE_A) |
| 612 | vlv_power_sequencer_reset(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 613 | } |
| 614 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 615 | /** |
| 616 | * intel_display_power_get - grab a power domain reference |
| 617 | * @dev_priv: i915 device instance |
| 618 | * @domain: power domain to reference |
| 619 | * |
| 620 | * This function grabs a power domain reference for @domain and ensures that the |
| 621 | * power domain and all its parents are powered up. Therefore users should only |
| 622 | * grab a reference to the innermost power domain they need. |
| 623 | * |
| 624 | * Any power domain reference obtained by this function must have a symmetric |
| 625 | * call to intel_display_power_put() to release the reference again. |
| 626 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 627 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 628 | enum intel_display_power_domain domain) |
| 629 | { |
| 630 | struct i915_power_domains *power_domains; |
| 631 | struct i915_power_well *power_well; |
| 632 | int i; |
| 633 | |
| 634 | intel_runtime_pm_get(dev_priv); |
| 635 | |
| 636 | power_domains = &dev_priv->power_domains; |
| 637 | |
| 638 | mutex_lock(&power_domains->lock); |
| 639 | |
| 640 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
| 641 | if (!power_well->count++) { |
| 642 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
| 643 | power_well->ops->enable(dev_priv, power_well); |
| 644 | power_well->hw_enabled = true; |
| 645 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 646 | } |
| 647 | |
| 648 | power_domains->domain_use_count[domain]++; |
| 649 | |
| 650 | mutex_unlock(&power_domains->lock); |
| 651 | } |
| 652 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 653 | /** |
| 654 | * intel_display_power_put - release a power domain reference |
| 655 | * @dev_priv: i915 device instance |
| 656 | * @domain: power domain to reference |
| 657 | * |
| 658 | * This function drops the power domain reference obtained by |
| 659 | * intel_display_power_get() and might power down the corresponding hardware |
| 660 | * block right away if this is the last reference. |
| 661 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 662 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 663 | enum intel_display_power_domain domain) |
| 664 | { |
| 665 | struct i915_power_domains *power_domains; |
| 666 | struct i915_power_well *power_well; |
| 667 | int i; |
| 668 | |
| 669 | power_domains = &dev_priv->power_domains; |
| 670 | |
| 671 | mutex_lock(&power_domains->lock); |
| 672 | |
| 673 | WARN_ON(!power_domains->domain_use_count[domain]); |
| 674 | power_domains->domain_use_count[domain]--; |
| 675 | |
| 676 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 677 | WARN_ON(!power_well->count); |
| 678 | |
| 679 | if (!--power_well->count && i915.disable_power_well) { |
| 680 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
| 681 | power_well->hw_enabled = false; |
| 682 | power_well->ops->disable(dev_priv, power_well); |
| 683 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 684 | } |
| 685 | |
| 686 | mutex_unlock(&power_domains->lock); |
| 687 | |
| 688 | intel_runtime_pm_put(dev_priv); |
| 689 | } |
| 690 | |
| 691 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 692 | |
| 693 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 694 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 695 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 696 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 697 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 698 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 699 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 700 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 701 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 702 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 703 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 704 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
| 705 | BIT(POWER_DOMAIN_PLLS) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 706 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 707 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 708 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 709 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 710 | BIT(POWER_DOMAIN_INIT)) |
| 711 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
| 712 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 713 | BIT(POWER_DOMAIN_INIT)) |
| 714 | |
| 715 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 716 | HSW_ALWAYS_ON_POWER_DOMAINS | \ |
| 717 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
| 718 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
| 719 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 720 | BIT(POWER_DOMAIN_INIT)) |
| 721 | |
| 722 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
| 723 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK |
| 724 | |
| 725 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 726 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 727 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 728 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 729 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 730 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 731 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 732 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 733 | BIT(POWER_DOMAIN_INIT)) |
| 734 | |
| 735 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
| 736 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 737 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 738 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 739 | BIT(POWER_DOMAIN_INIT)) |
| 740 | |
| 741 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
| 742 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 743 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 744 | BIT(POWER_DOMAIN_INIT)) |
| 745 | |
| 746 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
| 747 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 748 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 749 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 750 | BIT(POWER_DOMAIN_INIT)) |
| 751 | |
| 752 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
| 753 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 754 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 755 | BIT(POWER_DOMAIN_INIT)) |
| 756 | |
| 757 | #define CHV_PIPE_A_POWER_DOMAINS ( \ |
| 758 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 759 | BIT(POWER_DOMAIN_INIT)) |
| 760 | |
| 761 | #define CHV_PIPE_B_POWER_DOMAINS ( \ |
| 762 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 763 | BIT(POWER_DOMAIN_INIT)) |
| 764 | |
| 765 | #define CHV_PIPE_C_POWER_DOMAINS ( \ |
| 766 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 767 | BIT(POWER_DOMAIN_INIT)) |
| 768 | |
| 769 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 770 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 771 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 772 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 773 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 774 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 775 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 776 | BIT(POWER_DOMAIN_INIT)) |
| 777 | |
| 778 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
| 779 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 780 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 781 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 782 | BIT(POWER_DOMAIN_INIT)) |
| 783 | |
| 784 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ |
| 785 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 786 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 787 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 788 | BIT(POWER_DOMAIN_INIT)) |
| 789 | |
| 790 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ |
| 791 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 792 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 793 | BIT(POWER_DOMAIN_INIT)) |
| 794 | |
| 795 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
| 796 | .sync_hw = i9xx_always_on_power_well_noop, |
| 797 | .enable = i9xx_always_on_power_well_noop, |
| 798 | .disable = i9xx_always_on_power_well_noop, |
| 799 | .is_enabled = i9xx_always_on_power_well_enabled, |
| 800 | }; |
| 801 | |
| 802 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { |
| 803 | .sync_hw = chv_pipe_power_well_sync_hw, |
| 804 | .enable = chv_pipe_power_well_enable, |
| 805 | .disable = chv_pipe_power_well_disable, |
| 806 | .is_enabled = chv_pipe_power_well_enabled, |
| 807 | }; |
| 808 | |
| 809 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { |
| 810 | .sync_hw = vlv_power_well_sync_hw, |
| 811 | .enable = chv_dpio_cmn_power_well_enable, |
| 812 | .disable = chv_dpio_cmn_power_well_disable, |
| 813 | .is_enabled = vlv_power_well_enabled, |
| 814 | }; |
| 815 | |
| 816 | static struct i915_power_well i9xx_always_on_power_well[] = { |
| 817 | { |
| 818 | .name = "always-on", |
| 819 | .always_on = 1, |
| 820 | .domains = POWER_DOMAIN_MASK, |
| 821 | .ops = &i9xx_always_on_power_well_ops, |
| 822 | }, |
| 823 | }; |
| 824 | |
| 825 | static const struct i915_power_well_ops hsw_power_well_ops = { |
| 826 | .sync_hw = hsw_power_well_sync_hw, |
| 827 | .enable = hsw_power_well_enable, |
| 828 | .disable = hsw_power_well_disable, |
| 829 | .is_enabled = hsw_power_well_enabled, |
| 830 | }; |
| 831 | |
| 832 | static struct i915_power_well hsw_power_wells[] = { |
| 833 | { |
| 834 | .name = "always-on", |
| 835 | .always_on = 1, |
| 836 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, |
| 837 | .ops = &i9xx_always_on_power_well_ops, |
| 838 | }, |
| 839 | { |
| 840 | .name = "display", |
| 841 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
| 842 | .ops = &hsw_power_well_ops, |
| 843 | }, |
| 844 | }; |
| 845 | |
| 846 | static struct i915_power_well bdw_power_wells[] = { |
| 847 | { |
| 848 | .name = "always-on", |
| 849 | .always_on = 1, |
| 850 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, |
| 851 | .ops = &i9xx_always_on_power_well_ops, |
| 852 | }, |
| 853 | { |
| 854 | .name = "display", |
| 855 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
| 856 | .ops = &hsw_power_well_ops, |
| 857 | }, |
| 858 | }; |
| 859 | |
| 860 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
| 861 | .sync_hw = vlv_power_well_sync_hw, |
| 862 | .enable = vlv_display_power_well_enable, |
| 863 | .disable = vlv_display_power_well_disable, |
| 864 | .is_enabled = vlv_power_well_enabled, |
| 865 | }; |
| 866 | |
| 867 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
| 868 | .sync_hw = vlv_power_well_sync_hw, |
| 869 | .enable = vlv_dpio_cmn_power_well_enable, |
| 870 | .disable = vlv_dpio_cmn_power_well_disable, |
| 871 | .is_enabled = vlv_power_well_enabled, |
| 872 | }; |
| 873 | |
| 874 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
| 875 | .sync_hw = vlv_power_well_sync_hw, |
| 876 | .enable = vlv_power_well_enable, |
| 877 | .disable = vlv_power_well_disable, |
| 878 | .is_enabled = vlv_power_well_enabled, |
| 879 | }; |
| 880 | |
| 881 | static struct i915_power_well vlv_power_wells[] = { |
| 882 | { |
| 883 | .name = "always-on", |
| 884 | .always_on = 1, |
| 885 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 886 | .ops = &i9xx_always_on_power_well_ops, |
| 887 | }, |
| 888 | { |
| 889 | .name = "display", |
| 890 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 891 | .data = PUNIT_POWER_WELL_DISP2D, |
| 892 | .ops = &vlv_display_power_well_ops, |
| 893 | }, |
| 894 | { |
| 895 | .name = "dpio-tx-b-01", |
| 896 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 897 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 898 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 899 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 900 | .ops = &vlv_dpio_power_well_ops, |
| 901 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 902 | }, |
| 903 | { |
| 904 | .name = "dpio-tx-b-23", |
| 905 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 906 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 907 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 908 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 909 | .ops = &vlv_dpio_power_well_ops, |
| 910 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 911 | }, |
| 912 | { |
| 913 | .name = "dpio-tx-c-01", |
| 914 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 915 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 916 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 917 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 918 | .ops = &vlv_dpio_power_well_ops, |
| 919 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 920 | }, |
| 921 | { |
| 922 | .name = "dpio-tx-c-23", |
| 923 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 924 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 925 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 926 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 927 | .ops = &vlv_dpio_power_well_ops, |
| 928 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 929 | }, |
| 930 | { |
| 931 | .name = "dpio-common", |
| 932 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, |
| 933 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 934 | .ops = &vlv_dpio_cmn_power_well_ops, |
| 935 | }, |
| 936 | }; |
| 937 | |
| 938 | static struct i915_power_well chv_power_wells[] = { |
| 939 | { |
| 940 | .name = "always-on", |
| 941 | .always_on = 1, |
| 942 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 943 | .ops = &i9xx_always_on_power_well_ops, |
| 944 | }, |
| 945 | #if 0 |
| 946 | { |
| 947 | .name = "display", |
| 948 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 949 | .data = PUNIT_POWER_WELL_DISP2D, |
| 950 | .ops = &vlv_display_power_well_ops, |
| 951 | }, |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 952 | #endif |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 953 | { |
| 954 | .name = "pipe-a", |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 955 | /* |
| 956 | * FIXME: pipe A power well seems to be the new disp2d well. |
| 957 | * At least all registers seem to be housed there. Figure |
| 958 | * out if this a a temporary situation in pre-production |
| 959 | * hardware or a permanent state of affairs. |
| 960 | */ |
| 961 | .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 962 | .data = PIPE_A, |
| 963 | .ops = &chv_pipe_power_well_ops, |
| 964 | }, |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 965 | #if 0 |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 966 | { |
| 967 | .name = "pipe-b", |
| 968 | .domains = CHV_PIPE_B_POWER_DOMAINS, |
| 969 | .data = PIPE_B, |
| 970 | .ops = &chv_pipe_power_well_ops, |
| 971 | }, |
| 972 | { |
| 973 | .name = "pipe-c", |
| 974 | .domains = CHV_PIPE_C_POWER_DOMAINS, |
| 975 | .data = PIPE_C, |
| 976 | .ops = &chv_pipe_power_well_ops, |
| 977 | }, |
| 978 | #endif |
| 979 | { |
| 980 | .name = "dpio-common-bc", |
| 981 | /* |
| 982 | * XXX: cmnreset for one PHY seems to disturb the other. |
| 983 | * As a workaround keep both powered on at the same |
| 984 | * time for now. |
| 985 | */ |
| 986 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
| 987 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 988 | .ops = &chv_dpio_cmn_power_well_ops, |
| 989 | }, |
| 990 | { |
| 991 | .name = "dpio-common-d", |
| 992 | /* |
| 993 | * XXX: cmnreset for one PHY seems to disturb the other. |
| 994 | * As a workaround keep both powered on at the same |
| 995 | * time for now. |
| 996 | */ |
| 997 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
| 998 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
| 999 | .ops = &chv_dpio_cmn_power_well_ops, |
| 1000 | }, |
| 1001 | #if 0 |
| 1002 | { |
| 1003 | .name = "dpio-tx-b-01", |
| 1004 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1005 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
| 1006 | .ops = &vlv_dpio_power_well_ops, |
| 1007 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 1008 | }, |
| 1009 | { |
| 1010 | .name = "dpio-tx-b-23", |
| 1011 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1012 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
| 1013 | .ops = &vlv_dpio_power_well_ops, |
| 1014 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 1015 | }, |
| 1016 | { |
| 1017 | .name = "dpio-tx-c-01", |
| 1018 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1019 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1020 | .ops = &vlv_dpio_power_well_ops, |
| 1021 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 1022 | }, |
| 1023 | { |
| 1024 | .name = "dpio-tx-c-23", |
| 1025 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1026 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1027 | .ops = &vlv_dpio_power_well_ops, |
| 1028 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 1029 | }, |
| 1030 | { |
| 1031 | .name = "dpio-tx-d-01", |
| 1032 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
| 1033 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
| 1034 | .ops = &vlv_dpio_power_well_ops, |
| 1035 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, |
| 1036 | }, |
| 1037 | { |
| 1038 | .name = "dpio-tx-d-23", |
| 1039 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
| 1040 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
| 1041 | .ops = &vlv_dpio_power_well_ops, |
| 1042 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, |
| 1043 | }, |
| 1044 | #endif |
| 1045 | }; |
| 1046 | |
| 1047 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
| 1048 | enum punit_power_well power_well_id) |
| 1049 | { |
| 1050 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1051 | struct i915_power_well *power_well; |
| 1052 | int i; |
| 1053 | |
| 1054 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 1055 | if (power_well->data == power_well_id) |
| 1056 | return power_well; |
| 1057 | } |
| 1058 | |
| 1059 | return NULL; |
| 1060 | } |
| 1061 | |
| 1062 | #define set_power_wells(power_domains, __power_wells) ({ \ |
| 1063 | (power_domains)->power_wells = (__power_wells); \ |
| 1064 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ |
| 1065 | }) |
| 1066 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1067 | /** |
| 1068 | * intel_power_domains_init - initializes the power domain structures |
| 1069 | * @dev_priv: i915 device instance |
| 1070 | * |
| 1071 | * Initializes the power domain structures for @dev_priv depending upon the |
| 1072 | * supported platform. |
| 1073 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1074 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
| 1075 | { |
| 1076 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1077 | |
| 1078 | mutex_init(&power_domains->lock); |
| 1079 | |
| 1080 | /* |
| 1081 | * The enabling order will be from lower to higher indexed wells, |
| 1082 | * the disabling order is reversed. |
| 1083 | */ |
| 1084 | if (IS_HASWELL(dev_priv->dev)) { |
| 1085 | set_power_wells(power_domains, hsw_power_wells); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1086 | } else if (IS_BROADWELL(dev_priv->dev)) { |
| 1087 | set_power_wells(power_domains, bdw_power_wells); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1088 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1089 | set_power_wells(power_domains, chv_power_wells); |
| 1090 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 1091 | set_power_wells(power_domains, vlv_power_wells); |
| 1092 | } else { |
| 1093 | set_power_wells(power_domains, i9xx_always_on_power_well); |
| 1094 | } |
| 1095 | |
| 1096 | return 0; |
| 1097 | } |
| 1098 | |
Daniel Vetter | 41373cd | 2014-09-30 10:56:41 +0200 | [diff] [blame] | 1099 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
| 1100 | { |
| 1101 | struct drm_device *dev = dev_priv->dev; |
| 1102 | struct device *device = &dev->pdev->dev; |
| 1103 | |
| 1104 | if (!HAS_RUNTIME_PM(dev)) |
| 1105 | return; |
| 1106 | |
| 1107 | if (!intel_enable_rc6(dev)) |
| 1108 | return; |
| 1109 | |
| 1110 | /* Make sure we're not suspended first. */ |
| 1111 | pm_runtime_get_sync(device); |
| 1112 | pm_runtime_disable(device); |
| 1113 | } |
| 1114 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1115 | /** |
| 1116 | * intel_power_domains_fini - finalizes the power domain structures |
| 1117 | * @dev_priv: i915 device instance |
| 1118 | * |
| 1119 | * Finalizes the power domain structures for @dev_priv depending upon the |
| 1120 | * supported platform. This function also disables runtime pm and ensures that |
| 1121 | * the device stays powered up so that the driver can be reloaded. |
| 1122 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1123 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1124 | { |
Daniel Vetter | 41373cd | 2014-09-30 10:56:41 +0200 | [diff] [blame] | 1125 | intel_runtime_pm_disable(dev_priv); |
| 1126 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1127 | /* The i915.ko module is still not prepared to be loaded when |
| 1128 | * the power well is not enabled, so just enable it in case |
| 1129 | * we're going to unload/reload. */ |
| 1130 | intel_display_set_init_power(dev_priv, true); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1131 | } |
| 1132 | |
| 1133 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
| 1134 | { |
| 1135 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1136 | struct i915_power_well *power_well; |
| 1137 | int i; |
| 1138 | |
| 1139 | mutex_lock(&power_domains->lock); |
| 1140 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 1141 | power_well->ops->sync_hw(dev_priv, power_well); |
| 1142 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
| 1143 | power_well); |
| 1144 | } |
| 1145 | mutex_unlock(&power_domains->lock); |
| 1146 | } |
| 1147 | |
| 1148 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
| 1149 | { |
| 1150 | struct i915_power_well *cmn = |
| 1151 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1152 | struct i915_power_well *disp2d = |
| 1153 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); |
| 1154 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1155 | /* If the display might be already active skip this */ |
Ville Syrjälä | 5d93a6e | 2014-10-16 20:52:33 +0300 | [diff] [blame] | 1156 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
| 1157 | disp2d->ops->is_enabled(dev_priv, disp2d) && |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1158 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
| 1159 | return; |
| 1160 | |
| 1161 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); |
| 1162 | |
| 1163 | /* cmnlane needs DPLL registers */ |
| 1164 | disp2d->ops->enable(dev_priv, disp2d); |
| 1165 | |
| 1166 | /* |
| 1167 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: |
| 1168 | * Need to assert and de-assert PHY SB reset by gating the |
| 1169 | * common lane power, then un-gating it. |
| 1170 | * Simply ungating isn't enough to reset the PHY enough to get |
| 1171 | * ports and lanes running. |
| 1172 | */ |
| 1173 | cmn->ops->disable(dev_priv, cmn); |
| 1174 | } |
| 1175 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1176 | /** |
| 1177 | * intel_power_domains_init_hw - initialize hardware power domain state |
| 1178 | * @dev_priv: i915 device instance |
| 1179 | * |
| 1180 | * This function initializes the hardware power domain state and enables all |
| 1181 | * power domains using intel_display_set_init_power(). |
| 1182 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1183 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
| 1184 | { |
| 1185 | struct drm_device *dev = dev_priv->dev; |
| 1186 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1187 | |
| 1188 | power_domains->initializing = true; |
| 1189 | |
| 1190 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
| 1191 | mutex_lock(&power_domains->lock); |
| 1192 | vlv_cmnlane_wa(dev_priv); |
| 1193 | mutex_unlock(&power_domains->lock); |
| 1194 | } |
| 1195 | |
| 1196 | /* For now, we need the power well to be always enabled. */ |
| 1197 | intel_display_set_init_power(dev_priv, true); |
| 1198 | intel_power_domains_resume(dev_priv); |
| 1199 | power_domains->initializing = false; |
| 1200 | } |
| 1201 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1202 | /** |
| 1203 | * intel_aux_display_runtime_get - grab an auxilliary power domain reference |
| 1204 | * @dev_priv: i915 device instance |
| 1205 | * |
| 1206 | * This function grabs a power domain reference for the auxiliary power domain |
| 1207 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its |
| 1208 | * parents are powered up. Therefore users should only grab a reference to the |
| 1209 | * innermost power domain they need. |
| 1210 | * |
| 1211 | * Any power domain reference obtained by this function must have a symmetric |
| 1212 | * call to intel_aux_display_runtime_put() to release the reference again. |
| 1213 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1214 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
| 1215 | { |
| 1216 | intel_runtime_pm_get(dev_priv); |
| 1217 | } |
| 1218 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1219 | /** |
| 1220 | * intel_aux_display_runtime_put - release an auxilliary power domain reference |
| 1221 | * @dev_priv: i915 device instance |
| 1222 | * |
| 1223 | * This function drops the auxilliary power domain reference obtained by |
| 1224 | * intel_aux_display_runtime_get() and might power down the corresponding |
| 1225 | * hardware block right away if this is the last reference. |
| 1226 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1227 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
| 1228 | { |
| 1229 | intel_runtime_pm_put(dev_priv); |
| 1230 | } |
| 1231 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1232 | /** |
| 1233 | * intel_runtime_pm_get - grab a runtime pm reference |
| 1234 | * @dev_priv: i915 device instance |
| 1235 | * |
| 1236 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 1237 | * code to ensure the GTT or GT is on) and ensures that it is powered up. |
| 1238 | * |
| 1239 | * Any runtime pm reference obtained by this function must have a symmetric |
| 1240 | * call to intel_runtime_pm_put() to release the reference again. |
| 1241 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1242 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
| 1243 | { |
| 1244 | struct drm_device *dev = dev_priv->dev; |
| 1245 | struct device *device = &dev->pdev->dev; |
| 1246 | |
| 1247 | if (!HAS_RUNTIME_PM(dev)) |
| 1248 | return; |
| 1249 | |
| 1250 | pm_runtime_get_sync(device); |
| 1251 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); |
| 1252 | } |
| 1253 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1254 | /** |
| 1255 | * intel_runtime_pm_get_noresume - grab a runtime pm reference |
| 1256 | * @dev_priv: i915 device instance |
| 1257 | * |
| 1258 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 1259 | * code to ensure the GTT or GT is on). |
| 1260 | * |
| 1261 | * It will _not_ power up the device but instead only check that it's powered |
| 1262 | * on. Therefore it is only valid to call this functions from contexts where |
| 1263 | * the device is known to be powered up and where trying to power it up would |
| 1264 | * result in hilarity and deadlocks. That pretty much means only the system |
| 1265 | * suspend/resume code where this is used to grab runtime pm references for |
| 1266 | * delayed setup down in work items. |
| 1267 | * |
| 1268 | * Any runtime pm reference obtained by this function must have a symmetric |
| 1269 | * call to intel_runtime_pm_put() to release the reference again. |
| 1270 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1271 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
| 1272 | { |
| 1273 | struct drm_device *dev = dev_priv->dev; |
| 1274 | struct device *device = &dev->pdev->dev; |
| 1275 | |
| 1276 | if (!HAS_RUNTIME_PM(dev)) |
| 1277 | return; |
| 1278 | |
| 1279 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
| 1280 | pm_runtime_get_noresume(device); |
| 1281 | } |
| 1282 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1283 | /** |
| 1284 | * intel_runtime_pm_put - release a runtime pm reference |
| 1285 | * @dev_priv: i915 device instance |
| 1286 | * |
| 1287 | * This function drops the device-level runtime pm reference obtained by |
| 1288 | * intel_runtime_pm_get() and might power down the corresponding |
| 1289 | * hardware block right away if this is the last reference. |
| 1290 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1291 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
| 1292 | { |
| 1293 | struct drm_device *dev = dev_priv->dev; |
| 1294 | struct device *device = &dev->pdev->dev; |
| 1295 | |
| 1296 | if (!HAS_RUNTIME_PM(dev)) |
| 1297 | return; |
| 1298 | |
| 1299 | pm_runtime_mark_last_busy(device); |
| 1300 | pm_runtime_put_autosuspend(device); |
| 1301 | } |
| 1302 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1303 | /** |
| 1304 | * intel_runtime_pm_enable - enable runtime pm |
| 1305 | * @dev_priv: i915 device instance |
| 1306 | * |
| 1307 | * This function enables runtime pm at the end of the driver load sequence. |
| 1308 | * |
| 1309 | * Note that this function does currently not enable runtime pm for the |
| 1310 | * subordinate display power domains. That is only done on the first modeset |
| 1311 | * using intel_display_set_init_power(). |
| 1312 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1313 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1314 | { |
| 1315 | struct drm_device *dev = dev_priv->dev; |
| 1316 | struct device *device = &dev->pdev->dev; |
| 1317 | |
| 1318 | if (!HAS_RUNTIME_PM(dev)) |
| 1319 | return; |
| 1320 | |
| 1321 | pm_runtime_set_active(device); |
| 1322 | |
| 1323 | /* |
| 1324 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
| 1325 | * requirement. |
| 1326 | */ |
| 1327 | if (!intel_enable_rc6(dev)) { |
| 1328 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
| 1329 | return; |
| 1330 | } |
| 1331 | |
| 1332 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
| 1333 | pm_runtime_mark_last_busy(device); |
| 1334 | pm_runtime_use_autosuspend(device); |
| 1335 | |
| 1336 | pm_runtime_put_autosuspend(device); |
| 1337 | } |
| 1338 | |