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Laurent Pinchartf94859c2013-10-17 23:54:07 +02001* Renesas CPG Module Stop (MSTP) Clocks
2
3The CPG can gate SoC device clocks. The gates are organized in groups of up to
432 gates.
5
6This device tree binding describes a single 32 gate clocks group per node.
7Clocks are referenced by user nodes by the MSTP node phandle and the clock
8index in the group, from 0 to 31.
9
10Required Properties:
11
12 - compatible: Must be one of the following
13 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
14 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
15 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
16 - reg: Base address and length of the I/O mapped registers used by the MSTP
17 clocks. The first register is the clock control register and is mandatory.
18 The second register is the clock status register and is optional when not
19 implemented in hardware.
20 - clocks: Reference to the parent clocks, one per output clock. The parents
21 must appear in the same order as the output clocks.
22 - #clock-cells: Must be 1
23 - clock-output-names: The name of the clocks as free-form strings
Laurent Pinchart60480992014-02-19 18:13:24 +010024 - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
Laurent Pinchartf94859c2013-10-17 23:54:07 +020025
Laurent Pinchart60480992014-02-19 18:13:24 +010026The clocks, clock-output-names and renesas,clock-indices properties contain one
Laurent Pinchartf94859c2013-10-17 23:54:07 +020027entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
28gate clocks must not be declared.
29
30
31Example
32-------
33
34 #include <dt-bindings/clock/r8a7790-clock.h>
35
36 mstp3_clks: mstp3_clks@e615013c {
37 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
38 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
39 clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
40 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
41 <&mmc0_clk>;
42 #clock-cells = <1>;
43 clock-output-names =
44 "tpu0", "mmcif1", "sdhi3", "sdhi2",
45 "sdhi1", "sdhi0", "mmcif0";
46 renesas,clock-indices = <
47 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
48 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
49 R8A7790_CLK_MMCIF0
50 >;
51 };