Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra30-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 5 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 6 | #include "skeleton.dtsi" |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 7 | |
| 8 | / { |
| 9 | compatible = "nvidia,tegra30"; |
| 10 | interrupt-parent = <&intc>; |
| 11 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 12 | aliases { |
| 13 | serial0 = &uarta; |
| 14 | serial1 = &uartb; |
| 15 | serial2 = &uartc; |
| 16 | serial3 = &uartd; |
| 17 | serial4 = &uarte; |
| 18 | }; |
| 19 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 20 | pcie-controller@00003000 { |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 21 | compatible = "nvidia,tegra30-pcie"; |
| 22 | device_type = "pci"; |
| 23 | reg = <0x00003000 0x00000800 /* PADS registers */ |
| 24 | 0x00003800 0x00000200 /* AFI registers */ |
| 25 | 0x10000000 0x10000000>; /* configuration space */ |
| 26 | reg-names = "pads", "afi", "cs"; |
| 27 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ |
| 28 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| 29 | interrupt-names = "intr", "msi"; |
| 30 | |
| 31 | bus-range = <0x00 0xff>; |
| 32 | #address-cells = <3>; |
| 33 | #size-cells = <2>; |
| 34 | |
| 35 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ |
| 36 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ |
| 37 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ |
| 38 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ |
Jay Agarwal | d7283c1 | 2013-08-09 16:49:31 +0200 | [diff] [blame] | 39 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
| 40 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 41 | |
| 42 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, |
| 43 | <&tegra_car TEGRA30_CLK_AFI>, |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 44 | <&tegra_car TEGRA30_CLK_PLL_E>, |
| 45 | <&tegra_car TEGRA30_CLK_CML0>; |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 46 | clock-names = "pex", "afi", "pll_e", "cml"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 47 | resets = <&tegra_car 70>, |
| 48 | <&tegra_car 72>, |
| 49 | <&tegra_car 74>; |
| 50 | reset-names = "pex", "afi", "pcie_x"; |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 51 | status = "disabled"; |
| 52 | |
| 53 | pci@1,0 { |
| 54 | device_type = "pci"; |
| 55 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; |
| 56 | reg = <0x000800 0 0 0 0>; |
| 57 | status = "disabled"; |
| 58 | |
| 59 | #address-cells = <3>; |
| 60 | #size-cells = <2>; |
| 61 | ranges; |
| 62 | |
| 63 | nvidia,num-lanes = <2>; |
| 64 | }; |
| 65 | |
| 66 | pci@2,0 { |
| 67 | device_type = "pci"; |
| 68 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; |
| 69 | reg = <0x001000 0 0 0 0>; |
| 70 | status = "disabled"; |
| 71 | |
| 72 | #address-cells = <3>; |
| 73 | #size-cells = <2>; |
| 74 | ranges; |
| 75 | |
| 76 | nvidia,num-lanes = <2>; |
| 77 | }; |
| 78 | |
| 79 | pci@3,0 { |
| 80 | device_type = "pci"; |
| 81 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; |
| 82 | reg = <0x001800 0 0 0 0>; |
| 83 | status = "disabled"; |
| 84 | |
| 85 | #address-cells = <3>; |
| 86 | #size-cells = <2>; |
| 87 | ranges; |
| 88 | |
| 89 | nvidia,num-lanes = <2>; |
| 90 | }; |
| 91 | }; |
| 92 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 93 | host1x@50000000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 94 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
| 95 | reg = <0x50000000 0x00024000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 96 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 97 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 98 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 99 | resets = <&tegra_car 28>; |
| 100 | reset-names = "host1x"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 101 | |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <1>; |
| 104 | |
| 105 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 106 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 107 | mpe@54040000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 108 | compatible = "nvidia,tegra30-mpe"; |
| 109 | reg = <0x54040000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 110 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 111 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 112 | resets = <&tegra_car 60>; |
| 113 | reset-names = "mpe"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 116 | vi@54080000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 117 | compatible = "nvidia,tegra30-vi"; |
| 118 | reg = <0x54080000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 119 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 120 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 121 | resets = <&tegra_car 20>; |
| 122 | reset-names = "vi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 123 | }; |
| 124 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 125 | epp@540c0000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 126 | compatible = "nvidia,tegra30-epp"; |
| 127 | reg = <0x540c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 128 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 129 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 130 | resets = <&tegra_car 19>; |
| 131 | reset-names = "epp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 132 | }; |
| 133 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 134 | isp@54100000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 135 | compatible = "nvidia,tegra30-isp"; |
| 136 | reg = <0x54100000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 137 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 138 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 139 | resets = <&tegra_car 23>; |
| 140 | reset-names = "isp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 141 | }; |
| 142 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 143 | gr2d@54140000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 144 | compatible = "nvidia,tegra30-gr2d"; |
| 145 | reg = <0x54140000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 146 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 147 | resets = <&tegra_car 21>; |
| 148 | reset-names = "2d"; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 149 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 150 | }; |
| 151 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 152 | gr3d@54180000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 153 | compatible = "nvidia,tegra30-gr3d"; |
| 154 | reg = <0x54180000 0x00040000>; |
Thierry Reding | c71d390 | 2013-10-15 17:28:02 +0200 | [diff] [blame] | 155 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
| 156 | &tegra_car TEGRA30_CLK_GR3D2>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 157 | clock-names = "3d", "3d2"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 158 | resets = <&tegra_car 24>, |
| 159 | <&tegra_car 98>; |
| 160 | reset-names = "3d", "3d2"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | dc@54200000 { |
Thierry Reding | 05465f4 | 2013-10-15 17:27:51 +0200 | [diff] [blame] | 164 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 165 | reg = <0x54200000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 166 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 167 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
| 168 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 169 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 170 | resets = <&tegra_car 27>; |
| 171 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 172 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 173 | nvidia,head = <0>; |
| 174 | |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 175 | rgb { |
| 176 | status = "disabled"; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | dc@54240000 { |
| 181 | compatible = "nvidia,tegra30-dc"; |
| 182 | reg = <0x54240000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 183 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 184 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
| 185 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 186 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 187 | resets = <&tegra_car 26>; |
| 188 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 189 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 190 | nvidia,head = <1>; |
| 191 | |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 192 | rgb { |
| 193 | status = "disabled"; |
| 194 | }; |
| 195 | }; |
| 196 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 197 | hdmi@54280000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 198 | compatible = "nvidia,tegra30-hdmi"; |
| 199 | reg = <0x54280000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 200 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 201 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
| 202 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 203 | clock-names = "hdmi", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 204 | resets = <&tegra_car 51>; |
| 205 | reset-names = "hdmi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 206 | status = "disabled"; |
| 207 | }; |
| 208 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 209 | tvo@542c0000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 210 | compatible = "nvidia,tegra30-tvo"; |
| 211 | reg = <0x542c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 212 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 213 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 214 | status = "disabled"; |
| 215 | }; |
| 216 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 217 | dsi@54300000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 218 | compatible = "nvidia,tegra30-dsi"; |
| 219 | reg = <0x54300000 0x00040000>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 220 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 221 | resets = <&tegra_car 48>; |
| 222 | reset-names = "dsi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 223 | status = "disabled"; |
| 224 | }; |
| 225 | }; |
| 226 | |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 227 | timer@50004600 { |
| 228 | compatible = "arm,cortex-a9-twd-timer"; |
| 229 | reg = <0x50040600 0x20>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 230 | interrupts = <GIC_PPI 13 |
| 231 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 232 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 233 | }; |
| 234 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 235 | intc: interrupt-controller@50041000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 236 | compatible = "arm,cortex-a9-gic"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 237 | reg = <0x50041000 0x1000 |
| 238 | 0x50040100 0x0100>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 239 | interrupt-controller; |
| 240 | #interrupt-cells = <3>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 241 | }; |
| 242 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 243 | cache-controller@50043000 { |
Stephen Warren | bb2c1de | 2013-01-14 10:09:16 -0700 | [diff] [blame] | 244 | compatible = "arm,pl310-cache"; |
| 245 | reg = <0x50043000 0x1000>; |
| 246 | arm,data-latency = <6 6 2>; |
| 247 | arm,tag-latency = <5 5 2>; |
| 248 | cache-unified; |
| 249 | cache-level = <2>; |
| 250 | }; |
| 251 | |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 252 | timer@60005000 { |
| 253 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| 254 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 255 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 256 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 257 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 258 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 259 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 260 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 261 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 262 | }; |
| 263 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 264 | tegra_car: clock@60006000 { |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 265 | compatible = "nvidia,tegra30-car"; |
| 266 | reg = <0x60006000 0x1000>; |
| 267 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 268 | #reset-cells = <1>; |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 269 | }; |
| 270 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 271 | apbdma: dma@6000a000 { |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 272 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 273 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 274 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 275 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 276 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 277 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 278 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 279 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 280 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 281 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 282 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 283 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 284 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 285 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 286 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 287 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 288 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 289 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 290 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 291 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 292 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 293 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 294 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 295 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 296 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 297 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 298 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 299 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 300 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 301 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 302 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 303 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 305 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 306 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 307 | resets = <&tegra_car 34>; |
| 308 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 309 | #dma-cells = <1>; |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 310 | }; |
| 311 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 312 | ahb: ahb@6000c004 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 313 | compatible = "nvidia,tegra30-ahb"; |
| 314 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ |
| 315 | }; |
| 316 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 317 | gpio: gpio@6000d000 { |
Laxman Dewangan | 35f210e | 2012-12-19 20:27:12 +0530 | [diff] [blame] | 318 | compatible = "nvidia,tegra30-gpio"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 319 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 320 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 321 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 322 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 323 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 324 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 325 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 326 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 327 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 328 | #gpio-cells = <2>; |
| 329 | gpio-controller; |
| 330 | #interrupt-cells = <2>; |
| 331 | interrupt-controller; |
| 332 | }; |
| 333 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 334 | pinmux: pinmux@70000868 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 335 | compatible = "nvidia,tegra30-pinmux"; |
Pritesh Raithatha | 322337b | 2012-10-30 15:37:09 +0530 | [diff] [blame] | 336 | reg = <0x70000868 0xd4 /* Pad control registers */ |
| 337 | 0x70003000 0x3e4>; /* Mux registers */ |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 338 | }; |
| 339 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 340 | /* |
| 341 | * There are two serial driver i.e. 8250 based simple serial |
| 342 | * driver and APB DMA based serial driver for higher baudrate |
| 343 | * and performace. To enable the 8250 based driver, the compatible |
| 344 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable |
| 345 | * the APB DMA based serial driver, the comptible is |
| 346 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| 347 | */ |
| 348 | uarta: serial@70006000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 349 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 350 | reg = <0x70006000 0x40>; |
| 351 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 352 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 353 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 354 | resets = <&tegra_car 6>; |
| 355 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 356 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 357 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 358 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 359 | }; |
| 360 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 361 | uartb: serial@70006040 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 362 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 363 | reg = <0x70006040 0x40>; |
| 364 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 365 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 366 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 367 | resets = <&tegra_car 7>; |
| 368 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 369 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 370 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 371 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 372 | }; |
| 373 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 374 | uartc: serial@70006200 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 375 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 376 | reg = <0x70006200 0x100>; |
| 377 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 378 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 379 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 380 | resets = <&tegra_car 55>; |
| 381 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 382 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 383 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 384 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 385 | }; |
| 386 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 387 | uartd: serial@70006300 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 388 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 389 | reg = <0x70006300 0x100>; |
| 390 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 391 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 392 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 393 | resets = <&tegra_car 65>; |
| 394 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 395 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 396 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 397 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 398 | }; |
| 399 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 400 | uarte: serial@70006400 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 401 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 402 | reg = <0x70006400 0x100>; |
| 403 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 404 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 405 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 406 | resets = <&tegra_car 66>; |
| 407 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 408 | dmas = <&apbdma 20>, <&apbdma 20>; |
| 409 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 410 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 411 | }; |
| 412 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 413 | pwm: pwm@7000a000 { |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 414 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 415 | reg = <0x7000a000 0x100>; |
| 416 | #pwm-cells = <2>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 417 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 418 | resets = <&tegra_car 17>; |
| 419 | reset-names = "pwm"; |
Andrew Chew | b69cd98 | 2013-03-12 16:40:51 -0700 | [diff] [blame] | 420 | status = "disabled"; |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 421 | }; |
| 422 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 423 | rtc@7000e000 { |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 424 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 425 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 426 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 427 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 428 | }; |
| 429 | |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 430 | i2c@7000c000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 431 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 432 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 433 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 434 | #address-cells = <1>; |
| 435 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 436 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
| 437 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 438 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 439 | resets = <&tegra_car 12>; |
| 440 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 441 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 442 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 443 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | i2c@7000c400 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 447 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 448 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 449 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 450 | #address-cells = <1>; |
| 451 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 452 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
| 453 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 454 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 455 | resets = <&tegra_car 54>; |
| 456 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 457 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 458 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 459 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | i2c@7000c500 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 463 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 464 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 465 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 466 | #address-cells = <1>; |
| 467 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 468 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
| 469 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 470 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 471 | resets = <&tegra_car 67>; |
| 472 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 473 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 474 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 475 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 476 | }; |
| 477 | |
| 478 | i2c@7000c700 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 479 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 480 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 481 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 482 | #address-cells = <1>; |
| 483 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 484 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
| 485 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 486 | resets = <&tegra_car 103>; |
| 487 | reset-names = "i2c"; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 488 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 489 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 490 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 491 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 492 | }; |
| 493 | |
| 494 | i2c@7000d000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 495 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 496 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 497 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 498 | #address-cells = <1>; |
| 499 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 500 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
| 501 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 502 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 503 | resets = <&tegra_car 47>; |
| 504 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 505 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 506 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 507 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 508 | }; |
| 509 | |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 510 | spi@7000d400 { |
| 511 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 512 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 513 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 514 | #address-cells = <1>; |
| 515 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 516 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 517 | resets = <&tegra_car 41>; |
| 518 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 519 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 520 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
| 524 | spi@7000d600 { |
| 525 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 526 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 527 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 528 | #address-cells = <1>; |
| 529 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 530 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 531 | resets = <&tegra_car 44>; |
| 532 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 533 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 534 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 535 | status = "disabled"; |
| 536 | }; |
| 537 | |
| 538 | spi@7000d800 { |
| 539 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
Laxman Dewangan | 57471c8 | 2013-03-22 12:35:06 -0600 | [diff] [blame] | 540 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 541 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 542 | #address-cells = <1>; |
| 543 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 544 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 545 | resets = <&tegra_car 46>; |
| 546 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 547 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 548 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 549 | status = "disabled"; |
| 550 | }; |
| 551 | |
| 552 | spi@7000da00 { |
| 553 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 554 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 555 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 556 | #address-cells = <1>; |
| 557 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 558 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 559 | resets = <&tegra_car 68>; |
| 560 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 561 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 562 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | spi@7000dc00 { |
| 567 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 568 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 569 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 570 | #address-cells = <1>; |
| 571 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 572 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 573 | resets = <&tegra_car 104>; |
| 574 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 575 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 576 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 577 | status = "disabled"; |
| 578 | }; |
| 579 | |
| 580 | spi@7000de00 { |
| 581 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 582 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 583 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 584 | #address-cells = <1>; |
| 585 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 586 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 587 | resets = <&tegra_car 106>; |
| 588 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 589 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 590 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 591 | status = "disabled"; |
| 592 | }; |
| 593 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 594 | kbc@7000e200 { |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 595 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| 596 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 597 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 598 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 599 | resets = <&tegra_car 36>; |
| 600 | reset-names = "kbc"; |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 601 | status = "disabled"; |
| 602 | }; |
| 603 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 604 | pmc@7000e400 { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 605 | compatible = "nvidia,tegra30-pmc"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 606 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 607 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 608 | clock-names = "pclk", "clk32k_in"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 609 | }; |
| 610 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 611 | memory-controller@7000f000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 612 | compatible = "nvidia,tegra30-mc"; |
| 613 | reg = <0x7000f000 0x010 |
| 614 | 0x7000f03c 0x1b4 |
| 615 | 0x7000f200 0x028 |
| 616 | 0x7000f284 0x17c>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 617 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 618 | }; |
| 619 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 620 | iommu@7000f010 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 621 | compatible = "nvidia,tegra30-smmu"; |
| 622 | reg = <0x7000f010 0x02c |
| 623 | 0x7000f1f0 0x010 |
| 624 | 0x7000f228 0x05c>; |
| 625 | nvidia,#asids = <4>; /* # of ASIDs */ |
| 626 | dma-window = <0 0x40000000>; /* IOVA start & length */ |
| 627 | nvidia,ahb = <&ahb>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 628 | }; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 629 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 630 | ahub@70080000 { |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 631 | compatible = "nvidia,tegra30-ahub"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 632 | reg = <0x70080000 0x200 |
| 633 | 0x70080200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 634 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 635 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 636 | <&tegra_car TEGRA30_CLK_APBIF>; |
| 637 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 638 | resets = <&tegra_car 106>, /* d_audio */ |
| 639 | <&tegra_car 107>, /* apbif */ |
| 640 | <&tegra_car 30>, /* i2s0 */ |
| 641 | <&tegra_car 11>, /* i2s1 */ |
| 642 | <&tegra_car 18>, /* i2s2 */ |
| 643 | <&tegra_car 101>, /* i2s3 */ |
| 644 | <&tegra_car 102>, /* i2s4 */ |
| 645 | <&tegra_car 108>, /* dam0 */ |
| 646 | <&tegra_car 109>, /* dam1 */ |
| 647 | <&tegra_car 110>, /* dam2 */ |
| 648 | <&tegra_car 10>; /* spdif */ |
| 649 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 650 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 651 | "spdif"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 652 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 653 | <&apbdma 2>, <&apbdma 2>, |
| 654 | <&apbdma 3>, <&apbdma 3>, |
| 655 | <&apbdma 4>, <&apbdma 4>; |
| 656 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 657 | "rx3", "tx3"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 658 | ranges; |
| 659 | #address-cells = <1>; |
| 660 | #size-cells = <1>; |
| 661 | |
| 662 | tegra_i2s0: i2s@70080300 { |
| 663 | compatible = "nvidia,tegra30-i2s"; |
| 664 | reg = <0x70080300 0x100>; |
| 665 | nvidia,ahub-cif-ids = <4 4>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 666 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 667 | resets = <&tegra_car 30>; |
| 668 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 669 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 670 | }; |
| 671 | |
| 672 | tegra_i2s1: i2s@70080400 { |
| 673 | compatible = "nvidia,tegra30-i2s"; |
| 674 | reg = <0x70080400 0x100>; |
| 675 | nvidia,ahub-cif-ids = <5 5>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 676 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 677 | resets = <&tegra_car 11>; |
| 678 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 679 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 680 | }; |
| 681 | |
| 682 | tegra_i2s2: i2s@70080500 { |
| 683 | compatible = "nvidia,tegra30-i2s"; |
| 684 | reg = <0x70080500 0x100>; |
| 685 | nvidia,ahub-cif-ids = <6 6>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 686 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 687 | resets = <&tegra_car 18>; |
| 688 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 689 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 690 | }; |
| 691 | |
| 692 | tegra_i2s3: i2s@70080600 { |
| 693 | compatible = "nvidia,tegra30-i2s"; |
| 694 | reg = <0x70080600 0x100>; |
| 695 | nvidia,ahub-cif-ids = <7 7>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 696 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 697 | resets = <&tegra_car 101>; |
| 698 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 699 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 700 | }; |
| 701 | |
| 702 | tegra_i2s4: i2s@70080700 { |
| 703 | compatible = "nvidia,tegra30-i2s"; |
| 704 | reg = <0x70080700 0x100>; |
| 705 | nvidia,ahub-cif-ids = <8 8>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 706 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 707 | resets = <&tegra_car 102>; |
| 708 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 709 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 710 | }; |
| 711 | }; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 712 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 713 | sdhci@78000000 { |
| 714 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 715 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 716 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 717 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 718 | resets = <&tegra_car 14>; |
| 719 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 720 | status = "disabled"; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 721 | }; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 722 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 723 | sdhci@78000200 { |
| 724 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 725 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 726 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 727 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 728 | resets = <&tegra_car 9>; |
| 729 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 730 | status = "disabled"; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 731 | }; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 732 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 733 | sdhci@78000400 { |
| 734 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 735 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 736 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 737 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 738 | resets = <&tegra_car 69>; |
| 739 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 740 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 741 | }; |
| 742 | |
| 743 | sdhci@78000600 { |
| 744 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 745 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 746 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 747 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 748 | resets = <&tegra_car 15>; |
| 749 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 750 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 751 | }; |
| 752 | |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 753 | usb@7d000000 { |
| 754 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 755 | reg = <0x7d000000 0x4000>; |
| 756 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 757 | phy_type = "utmi"; |
| 758 | clocks = <&tegra_car TEGRA30_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 759 | resets = <&tegra_car 22>; |
| 760 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 761 | nvidia,needs-double-reset; |
| 762 | nvidia,phy = <&phy1>; |
| 763 | status = "disabled"; |
| 764 | }; |
| 765 | |
| 766 | phy1: usb-phy@7d000000 { |
| 767 | compatible = "nvidia,tegra30-usb-phy"; |
| 768 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 769 | phy_type = "utmi"; |
| 770 | clocks = <&tegra_car TEGRA30_CLK_USBD>, |
| 771 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 772 | <&tegra_car TEGRA30_CLK_USBD>; |
| 773 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 774 | nvidia,hssync-start-delay = <9>; |
| 775 | nvidia,idle-wait-delay = <17>; |
| 776 | nvidia,elastic-limit = <16>; |
| 777 | nvidia,term-range-adj = <6>; |
| 778 | nvidia,xcvr-setup = <51>; |
| 779 | nvidia.xcvr-setup-use-fuses; |
| 780 | nvidia,xcvr-lsfslew = <1>; |
| 781 | nvidia,xcvr-lsrslew = <1>; |
| 782 | nvidia,xcvr-hsslew = <32>; |
| 783 | nvidia,hssquelch-level = <2>; |
| 784 | nvidia,hsdiscon-level = <5>; |
| 785 | status = "disabled"; |
| 786 | }; |
| 787 | |
| 788 | usb@7d004000 { |
| 789 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 790 | reg = <0x7d004000 0x4000>; |
| 791 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 792 | phy_type = "utmi"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 793 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 794 | resets = <&tegra_car 58>; |
| 795 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 796 | nvidia,phy = <&phy2>; |
| 797 | status = "disabled"; |
| 798 | }; |
| 799 | |
| 800 | phy2: usb-phy@7d004000 { |
| 801 | compatible = "nvidia,tegra30-usb-phy"; |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 802 | reg = <0x7d004000 0x4000 0x7d000000 0x4000>; |
| 803 | phy_type = "utmi"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 804 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
| 805 | <&tegra_car TEGRA30_CLK_PLL_U>, |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 806 | <&tegra_car TEGRA30_CLK_USBD>; |
| 807 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 808 | nvidia,hssync-start-delay = <9>; |
| 809 | nvidia,idle-wait-delay = <17>; |
| 810 | nvidia,elastic-limit = <16>; |
| 811 | nvidia,term-range-adj = <6>; |
| 812 | nvidia,xcvr-setup = <51>; |
| 813 | nvidia.xcvr-setup-use-fuses; |
| 814 | nvidia,xcvr-lsfslew = <2>; |
| 815 | nvidia,xcvr-lsrslew = <2>; |
| 816 | nvidia,xcvr-hsslew = <32>; |
| 817 | nvidia,hssquelch-level = <2>; |
| 818 | nvidia,hsdiscon-level = <5>; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 819 | status = "disabled"; |
| 820 | }; |
| 821 | |
| 822 | usb@7d008000 { |
| 823 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 824 | reg = <0x7d008000 0x4000>; |
| 825 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 826 | phy_type = "utmi"; |
| 827 | clocks = <&tegra_car TEGRA30_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 828 | resets = <&tegra_car 59>; |
| 829 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 830 | nvidia,phy = <&phy3>; |
| 831 | status = "disabled"; |
| 832 | }; |
| 833 | |
| 834 | phy3: usb-phy@7d008000 { |
| 835 | compatible = "nvidia,tegra30-usb-phy"; |
| 836 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 837 | phy_type = "utmi"; |
| 838 | clocks = <&tegra_car TEGRA30_CLK_USB3>, |
| 839 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 840 | <&tegra_car TEGRA30_CLK_USBD>; |
| 841 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 842 | nvidia,hssync-start-delay = <0>; |
| 843 | nvidia,idle-wait-delay = <17>; |
| 844 | nvidia,elastic-limit = <16>; |
| 845 | nvidia,term-range-adj = <6>; |
| 846 | nvidia,xcvr-setup = <51>; |
| 847 | nvidia.xcvr-setup-use-fuses; |
| 848 | nvidia,xcvr-lsfslew = <2>; |
| 849 | nvidia,xcvr-lsrslew = <2>; |
| 850 | nvidia,xcvr-hsslew = <32>; |
| 851 | nvidia,hssquelch-level = <2>; |
| 852 | nvidia,hsdiscon-level = <5>; |
| 853 | status = "disabled"; |
| 854 | }; |
| 855 | |
Hiroshi Doyu | 7d19a34 | 2013-01-11 15:11:54 +0200 | [diff] [blame] | 856 | cpus { |
| 857 | #address-cells = <1>; |
| 858 | #size-cells = <0>; |
| 859 | |
| 860 | cpu@0 { |
| 861 | device_type = "cpu"; |
| 862 | compatible = "arm,cortex-a9"; |
| 863 | reg = <0>; |
| 864 | }; |
| 865 | |
| 866 | cpu@1 { |
| 867 | device_type = "cpu"; |
| 868 | compatible = "arm,cortex-a9"; |
| 869 | reg = <1>; |
| 870 | }; |
| 871 | |
| 872 | cpu@2 { |
| 873 | device_type = "cpu"; |
| 874 | compatible = "arm,cortex-a9"; |
| 875 | reg = <2>; |
| 876 | }; |
| 877 | |
| 878 | cpu@3 { |
| 879 | device_type = "cpu"; |
| 880 | compatible = "arm,cortex-a9"; |
| 881 | reg = <3>; |
| 882 | }; |
| 883 | }; |
| 884 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 885 | pmu { |
| 886 | compatible = "arm,cortex-a9-pmu"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 887 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 888 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 889 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 890 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 891 | }; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 892 | }; |