blob: a59788e83b8b377152ed5d70db86fbb7bc9fb805 [file] [log] [blame]
Gavin Shan29310e52013-06-20 13:21:13 +08001/*
2 * The file intends to implement the platform dependent EEH operations on
3 * powernv platform. Actually, the powernv was created in order to fully
4 * hypervisor support.
5 *
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/atomic.h>
15#include <linux/delay.h>
16#include <linux/export.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/msi.h>
20#include <linux/of.h>
21#include <linux/pci.h>
22#include <linux/proc_fs.h>
23#include <linux/rbtree.h>
24#include <linux/sched.h>
25#include <linux/seq_file.h>
26#include <linux/spinlock.h>
27
28#include <asm/eeh.h>
29#include <asm/eeh_event.h>
30#include <asm/firmware.h>
31#include <asm/io.h>
32#include <asm/iommu.h>
33#include <asm/machdep.h>
34#include <asm/msi_bitmap.h>
35#include <asm/opal.h>
36#include <asm/ppc-pci.h>
37
38#include "powernv.h"
39#include "pci.h"
40
41/**
42 * powernv_eeh_init - EEH platform dependent initialization
43 *
44 * EEH platform dependent initialization on powernv
45 */
46static int powernv_eeh_init(void)
47{
48 /* We require OPALv3 */
49 if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
50 pr_warning("%s: OPALv3 is required !\n", __func__);
51 return -EINVAL;
52 }
53
54 /* Set EEH probe mode */
55 eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
56
57 return 0;
58}
59
60/**
61 * powernv_eeh_post_init - EEH platform dependent post initialization
62 *
63 * EEH platform dependent post initialization on powernv. When
64 * the function is called, the EEH PEs and devices should have
65 * been built. If the I/O cache staff has been built, EEH is
66 * ready to supply service.
67 */
68static int powernv_eeh_post_init(void)
69{
70 struct pci_controller *hose;
71 struct pnv_phb *phb;
72 int ret = 0;
73
74 list_for_each_entry(hose, &hose_list, list_node) {
75 phb = hose->private_data;
76
77 if (phb->eeh_ops && phb->eeh_ops->post_init) {
78 ret = phb->eeh_ops->post_init(hose);
79 if (ret)
80 break;
81 }
82 }
83
84 return ret;
85}
86
87/**
88 * powernv_eeh_dev_probe - Do probe on PCI device
89 * @dev: PCI device
90 * @flag: unused
91 *
92 * When EEH module is installed during system boot, all PCI devices
93 * are checked one by one to see if it supports EEH. The function
94 * is introduced for the purpose. By default, EEH has been enabled
95 * on all PCI devices. That's to say, we only need do necessary
96 * initialization on the corresponding eeh device and create PE
97 * accordingly.
98 *
99 * It's notable that's unsafe to retrieve the EEH device through
100 * the corresponding PCI device. During the PCI device hotplug, which
101 * was possiblly triggered by EEH core, the binding between EEH device
102 * and the PCI device isn't built yet.
103 */
104static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
105{
106 struct pci_controller *hose = pci_bus_to_host(dev->bus);
107 struct pnv_phb *phb = hose->private_data;
108 struct device_node *dn = pci_device_to_OF_node(dev);
109 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
110
111 /*
112 * When probing the root bridge, which doesn't have any
113 * subordinate PCI devices. We don't have OF node for
114 * the root bridge. So it's not reasonable to continue
115 * the probing.
116 */
Gavin Shanf5c57712013-07-24 10:24:58 +0800117 if (!dn || !edev || edev->pe)
Gavin Shan29310e52013-06-20 13:21:13 +0800118 return 0;
119
120 /* Skip for PCI-ISA bridge */
121 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
122 return 0;
123
124 /* Initialize eeh device */
Gavin Shanab55d212013-07-24 10:25:01 +0800125 edev->class_code = dev->class;
126 edev->mode &= 0xFFFFFF00;
Gavin Shan4b83bd42013-07-24 10:24:59 +0800127 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
128 edev->mode |= EEH_DEV_BRIDGE;
129 if (pci_is_pcie(dev)) {
130 edev->pcie_cap = pci_pcie_cap(dev);
131
132 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
133 edev->mode |= EEH_DEV_ROOT_PORT;
134 else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
135 edev->mode |= EEH_DEV_DS_PORT;
136 }
137
Gavin Shan29310e52013-06-20 13:21:13 +0800138 edev->config_addr = ((dev->bus->number << 8) | dev->devfn);
139 edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff);
140
141 /* Create PE */
142 eeh_add_to_parent_pe(edev);
143
144 /*
145 * Enable EEH explicitly so that we will do EEH check
146 * while accessing I/O stuff
Gavin Shan29310e52013-06-20 13:21:13 +0800147 */
Gavin Shan2ec5a0a2014-02-12 15:24:55 +0800148 eeh_set_enable(true);
Gavin Shan29310e52013-06-20 13:21:13 +0800149
150 /* Save memory bars */
151 eeh_save_bars(edev);
152
153 return 0;
154}
155
156/**
157 * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
158 * @pe: EEH PE
159 * @option: operation to be issued
160 *
161 * The function is used to control the EEH functionality globally.
162 * Currently, following options are support according to PAPR:
163 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
164 */
165static int powernv_eeh_set_option(struct eeh_pe *pe, int option)
166{
167 struct pci_controller *hose = pe->phb;
168 struct pnv_phb *phb = hose->private_data;
169 int ret = -EEXIST;
170
171 /*
172 * What we need do is pass it down for hardware
173 * implementation to handle it.
174 */
175 if (phb->eeh_ops && phb->eeh_ops->set_option)
176 ret = phb->eeh_ops->set_option(pe, option);
177
178 return ret;
179}
180
181/**
182 * powernv_eeh_get_pe_addr - Retrieve PE address
183 * @pe: EEH PE
184 *
185 * Retrieve the PE address according to the given tranditional
186 * PCI BDF (Bus/Device/Function) address.
187 */
188static int powernv_eeh_get_pe_addr(struct eeh_pe *pe)
189{
190 return pe->addr;
191}
192
193/**
194 * powernv_eeh_get_state - Retrieve PE state
195 * @pe: EEH PE
196 * @delay: delay while PE state is temporarily unavailable
197 *
198 * Retrieve the state of the specified PE. For IODA-compitable
199 * platform, it should be retrieved from IODA table. Therefore,
200 * we prefer passing down to hardware implementation to handle
201 * it.
202 */
203static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay)
204{
205 struct pci_controller *hose = pe->phb;
206 struct pnv_phb *phb = hose->private_data;
207 int ret = EEH_STATE_NOT_SUPPORT;
208
209 if (phb->eeh_ops && phb->eeh_ops->get_state) {
210 ret = phb->eeh_ops->get_state(pe);
211
212 /*
213 * If the PE state is temporarily unavailable,
214 * to inform the EEH core delay for default
215 * period (1 second)
216 */
217 if (delay) {
218 *delay = 0;
219 if (ret & EEH_STATE_UNAVAILABLE)
220 *delay = 1000;
221 }
222 }
223
224 return ret;
225}
226
227/**
228 * powernv_eeh_reset - Reset the specified PE
229 * @pe: EEH PE
230 * @option: reset option
231 *
232 * Reset the specified PE
233 */
234static int powernv_eeh_reset(struct eeh_pe *pe, int option)
235{
236 struct pci_controller *hose = pe->phb;
237 struct pnv_phb *phb = hose->private_data;
238 int ret = -EEXIST;
239
240 if (phb->eeh_ops && phb->eeh_ops->reset)
241 ret = phb->eeh_ops->reset(pe, option);
242
243 return ret;
244}
245
246/**
247 * powernv_eeh_wait_state - Wait for PE state
248 * @pe: EEH PE
249 * @max_wait: maximal period in microsecond
250 *
251 * Wait for the state of associated PE. It might take some time
252 * to retrieve the PE's state.
253 */
254static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
255{
256 int ret;
257 int mwait;
258
259 while (1) {
260 ret = powernv_eeh_get_state(pe, &mwait);
261
262 /*
263 * If the PE's state is temporarily unavailable,
264 * we have to wait for the specified time. Otherwise,
265 * the PE's state will be returned immediately.
266 */
267 if (ret != EEH_STATE_UNAVAILABLE)
268 return ret;
269
270 max_wait -= mwait;
271 if (max_wait <= 0) {
272 pr_warning("%s: Timeout getting PE#%x's state (%d)\n",
273 __func__, pe->addr, max_wait);
274 return EEH_STATE_NOT_SUPPORT;
275 }
276
277 msleep(mwait);
278 }
279
280 return EEH_STATE_NOT_SUPPORT;
281}
282
283/**
284 * powernv_eeh_get_log - Retrieve error log
285 * @pe: EEH PE
286 * @severity: temporary or permanent error log
287 * @drv_log: driver log to be combined with retrieved error log
288 * @len: length of driver log
289 *
290 * Retrieve the temporary or permanent error from the PE.
291 */
292static int powernv_eeh_get_log(struct eeh_pe *pe, int severity,
293 char *drv_log, unsigned long len)
294{
295 struct pci_controller *hose = pe->phb;
296 struct pnv_phb *phb = hose->private_data;
297 int ret = -EEXIST;
298
299 if (phb->eeh_ops && phb->eeh_ops->get_log)
300 ret = phb->eeh_ops->get_log(pe, severity, drv_log, len);
301
302 return ret;
303}
304
305/**
306 * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
307 * @pe: EEH PE
308 *
309 * The function will be called to reconfigure the bridges included
310 * in the specified PE so that the mulfunctional PE would be recovered
311 * again.
312 */
313static int powernv_eeh_configure_bridge(struct eeh_pe *pe)
314{
315 struct pci_controller *hose = pe->phb;
316 struct pnv_phb *phb = hose->private_data;
317 int ret = 0;
318
319 if (phb->eeh_ops && phb->eeh_ops->configure_bridge)
320 ret = phb->eeh_ops->configure_bridge(pe);
321
322 return ret;
323}
324
325/**
Gavin Shan29310e52013-06-20 13:21:13 +0800326 * powernv_eeh_next_error - Retrieve next EEH error to handle
327 * @pe: Affected PE
328 *
329 * Using OPAL API, to retrieve next EEH error for EEH core to handle
330 */
331static int powernv_eeh_next_error(struct eeh_pe **pe)
332{
333 struct pci_controller *hose;
334 struct pnv_phb *phb = NULL;
335
336 list_for_each_entry(hose, &hose_list, list_node) {
337 phb = hose->private_data;
338 break;
339 }
340
341 if (phb && phb->eeh_ops->next_error)
342 return phb->eeh_ops->next_error(pe);
343
344 return -EEXIST;
345}
346
Gavin Shan9be3bec2014-01-03 17:47:13 +0800347static int powernv_eeh_restore_config(struct device_node *dn)
348{
349 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
350 struct pnv_phb *phb;
351 s64 ret;
352
353 if (!edev)
354 return -EEXIST;
355
356 phb = edev->phb->private_data;
357 ret = opal_pci_reinit(phb->opal_id,
358 OPAL_REINIT_PCI_DEV, edev->config_addr);
359 if (ret) {
360 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
361 __func__, edev->config_addr, ret);
362 return -EIO;
363 }
364
365 return 0;
366}
367
Gavin Shan29310e52013-06-20 13:21:13 +0800368static struct eeh_ops powernv_eeh_ops = {
369 .name = "powernv",
370 .init = powernv_eeh_init,
371 .post_init = powernv_eeh_post_init,
372 .of_probe = NULL,
373 .dev_probe = powernv_eeh_dev_probe,
374 .set_option = powernv_eeh_set_option,
375 .get_pe_addr = powernv_eeh_get_pe_addr,
376 .get_state = powernv_eeh_get_state,
377 .reset = powernv_eeh_reset,
378 .wait_state = powernv_eeh_wait_state,
379 .get_log = powernv_eeh_get_log,
380 .configure_bridge = powernv_eeh_configure_bridge,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800381 .read_config = pnv_pci_cfg_read,
382 .write_config = pnv_pci_cfg_write,
Gavin Shan1d350542014-01-03 17:47:12 +0800383 .next_error = powernv_eeh_next_error,
Gavin Shan9be3bec2014-01-03 17:47:13 +0800384 .restore_config = powernv_eeh_restore_config
Gavin Shan29310e52013-06-20 13:21:13 +0800385};
386
387/**
388 * eeh_powernv_init - Register platform dependent EEH operations
389 *
390 * EEH initialization on powernv platform. This function should be
391 * called before any EEH related functions.
392 */
393static int __init eeh_powernv_init(void)
394{
395 int ret = -EINVAL;
396
397 if (!machine_is(powernv))
398 return ret;
399
400 ret = eeh_ops_register(&powernv_eeh_ops);
401 if (!ret)
402 pr_info("EEH: PowerNV platform initialized\n");
403 else
404 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
405
406 return ret;
407}
408
409early_initcall(eeh_powernv_init);