| Marcelo Roberto Jimenez | fa87672 | 2010-10-18 22:41:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-sa1100/include/mach/nanoengine.h |
| 3 | * |
| 4 | * This file contains the hardware specific definitions for nanoEngine. |
| 5 | * Only include this file from SA1100-specific files. |
| 6 | * |
| 7 | * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | */ |
| 14 | #ifndef __ASM_ARCH_NANOENGINE_H |
| 15 | #define __ASM_ARCH_NANOENGINE_H |
| 16 | |
| Marcelo Roberto Jimenez | b080ac8 | 2010-12-16 21:34:51 +0100 | [diff] [blame] | 17 | #include <mach/irqs.h> |
| 18 | |
| Russell King | 7cf779c | 2012-01-13 23:05:12 +0000 | [diff] [blame] | 19 | #define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ |
| 20 | #define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ |
| 21 | #define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ |
| 22 | #define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ |
| Russell King | 76346a4 | 2012-01-18 12:37:20 +0000 | [diff] [blame] | 23 | #define GPIO_PC_RESET0 15 /* reset socket 0 */ |
| 24 | #define GPIO_PC_RESET1 16 /* reset socket 1 */ |
| Marcelo Roberto Jimenez | fa87672 | 2010-10-18 22:41:29 +0100 | [diff] [blame] | 25 | |
| Marcelo Roberto Jimenez | b080ac8 | 2010-12-16 21:34:51 +0100 | [diff] [blame] | 26 | #define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 |
| Marcelo Roberto Jimenez | fa87672 | 2010-10-18 22:41:29 +0100 | [diff] [blame] | 27 | #define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 |
| 28 | #define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 |
| 29 | #define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 |
| 30 | #define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 |
| 31 | |
| Marcelo Roberto Jimenez | b080ac8 | 2010-12-16 21:34:51 +0100 | [diff] [blame] | 32 | /* |
| 33 | * nanoEngine Memory Map: |
| 34 | * |
| 35 | * 0000.0000 - 003F.0000 - 4 MB Flash |
| 36 | * C000.0000 - C1FF.FFFF - 32 MB SDRAM |
| 37 | * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write |
| 38 | * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space |
| 39 | * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode |
| 40 | * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #define NANO_PCI_MEM_RW_PHYS 0x18600000 |
| 45 | #define NANO_PCI_MEM_RW_VIRT 0xf1000000 |
| 46 | #define NANO_PCI_MEM_RW_SIZE SZ_1M |
| 47 | #define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 |
| 48 | #define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 |
| 49 | #define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K |
| 50 | |
| Marcelo Roberto Jimenez | fa87672 | 2010-10-18 22:41:29 +0100 | [diff] [blame] | 51 | #endif |
| 52 | |