Blame - drivers/gpu/drm/radeon/r600d.h - kernel/msm-4.9

2009-09-08 10:10:24 +1000

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Dave Airlie

* Alex Deucher

* Jerome Glisse

*/

#ifndef R600D_H

#define R600D_H

#define CP_PACKET2 0x80000000

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#define PACKET2_PAD_SHIFT 0

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#define PACKET2_PAD_MASK (0x3fffffff << 0)

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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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#define R6XX_MAX_SH_GPRS 256

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#define R6XX_MAX_TEMP_GPRS 16

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#define R6XX_MAX_SH_THREADS 256

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#define R6XX_MAX_SH_STACK_ENTRIES 4096

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#define R6XX_MAX_BACKENDS 8

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#define R6XX_MAX_BACKENDS_MASK 0xff

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#define R6XX_MAX_SIMDS 8

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#define R6XX_MAX_SIMDS_MASK 0xff

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#define R6XX_MAX_PIPES 8

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#define R6XX_MAX_PIPES_MASK 0xff

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/* PTE flags */

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#define PTE_VALID (1 << 0)

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#define PTE_SYSTEM (1 << 1)

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#define PTE_SNOOPED (1 << 2)

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#define PTE_READABLE (1 << 5)

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#define PTE_WRITEABLE (1 << 6)

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/* tiling bits */

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#define ARRAY_LINEAR_GENERAL 0x00000000

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#define ARRAY_LINEAR_ALIGNED 0x00000001

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#define ARRAY_1D_TILED_THIN1 0x00000002

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#define ARRAY_2D_TILED_THIN1 0x00000004

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/* Registers */

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#define ARB_POP 0x2418

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#define ENABLE_TC128 (1 << 30)

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#define ARB_GDEC_RD_CNTL 0x246C

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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Marek Olšák

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#define R_028808_CB_COLOR_CONTROL 0x28808

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#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)

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#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)

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#define C_028808_SPECIAL_OP 0xFFFFFF8F

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#define V_028808_SPECIAL_NORMAL 0x00

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#define V_028808_SPECIAL_DISABLE 0x01

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#define V_028808_SPECIAL_RESOLVE_BOX 0x07

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#define CB_COLOR0_BASE 0x28040

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#define CB_COLOR1_BASE 0x28044

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#define CB_COLOR2_BASE 0x28048

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#define CB_COLOR3_BASE 0x2804C

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#define CB_COLOR4_BASE 0x28050

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#define CB_COLOR5_BASE 0x28054

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#define CB_COLOR6_BASE 0x28058

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#define CB_COLOR7_BASE 0x2805C

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#define CB_COLOR7_FRAG 0x280FC

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#define CB_COLOR0_SIZE 0x28060

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#define CB_COLOR0_VIEW 0x28080

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#define R_028080_CB_COLOR0_VIEW 0x028080

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#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)

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#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)

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#define C_028080_SLICE_START 0xFFFFF800

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#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)

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#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

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#define C_028080_SLICE_MAX 0xFF001FFF

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#define R_028084_CB_COLOR1_VIEW 0x028084

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#define R_028088_CB_COLOR2_VIEW 0x028088

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#define R_02808C_CB_COLOR3_VIEW 0x02808C

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#define R_028090_CB_COLOR4_VIEW 0x028090

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#define R_028094_CB_COLOR5_VIEW 0x028094

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#define R_028098_CB_COLOR6_VIEW 0x028098

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#define R_02809C_CB_COLOR7_VIEW 0x02809C

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#define R_028100_CB_COLOR0_MASK 0x028100

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#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)

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#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)

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#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000

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#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)

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#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)

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#define C_028100_FMASK_TILE_MAX 0x00000FFF

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#define R_028104_CB_COLOR1_MASK 0x028104

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#define R_028108_CB_COLOR2_MASK 0x028108

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#define R_02810C_CB_COLOR3_MASK 0x02810C

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#define R_028110_CB_COLOR4_MASK 0x028110

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#define R_028114_CB_COLOR5_MASK 0x028114

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#define R_028118_CB_COLOR6_MASK 0x028118

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#define R_02811C_CB_COLOR7_MASK 0x02811C

Jerome Glisse

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#define CB_COLOR0_INFO 0x280a0

Ilija Hadzic

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# define CB_FORMAT(x) ((x) << 2)

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# define CB_ARRAY_MODE(x) ((x) << 8)

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# define CB_SOURCE_FORMAT(x) ((x) << 27)

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# define CB_SF_EXPORT_FULL 0

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# define CB_SF_EXPORT_NORM 1

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#define CB_COLOR0_TILE 0x280c0

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#define CB_COLOR0_FRAG 0x280e0

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#define CB_COLOR0_MASK 0x28100

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#define SQ_ALU_CONST_CACHE_PS_0 0x28940

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#define SQ_ALU_CONST_CACHE_PS_1 0x28944

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#define SQ_ALU_CONST_CACHE_PS_2 0x28948

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#define SQ_ALU_CONST_CACHE_PS_3 0x2894c

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#define SQ_ALU_CONST_CACHE_PS_4 0x28950

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#define SQ_ALU_CONST_CACHE_PS_5 0x28954

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#define SQ_ALU_CONST_CACHE_PS_6 0x28958

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#define SQ_ALU_CONST_CACHE_PS_7 0x2895c

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#define SQ_ALU_CONST_CACHE_PS_8 0x28960

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#define SQ_ALU_CONST_CACHE_PS_9 0x28964

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#define SQ_ALU_CONST_CACHE_PS_10 0x28968

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#define SQ_ALU_CONST_CACHE_PS_11 0x2896c

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#define SQ_ALU_CONST_CACHE_PS_12 0x28970

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#define SQ_ALU_CONST_CACHE_PS_13 0x28974

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#define SQ_ALU_CONST_CACHE_PS_14 0x28978

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#define SQ_ALU_CONST_CACHE_PS_15 0x2897c

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#define SQ_ALU_CONST_CACHE_VS_0 0x28980

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#define SQ_ALU_CONST_CACHE_VS_1 0x28984

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#define SQ_ALU_CONST_CACHE_VS_2 0x28988

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#define SQ_ALU_CONST_CACHE_VS_3 0x2898c

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#define SQ_ALU_CONST_CACHE_VS_4 0x28990

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#define SQ_ALU_CONST_CACHE_VS_5 0x28994

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#define SQ_ALU_CONST_CACHE_VS_6 0x28998

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#define SQ_ALU_CONST_CACHE_VS_7 0x2899c

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#define SQ_ALU_CONST_CACHE_VS_8 0x289a0

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#define SQ_ALU_CONST_CACHE_VS_9 0x289a4

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#define SQ_ALU_CONST_CACHE_VS_10 0x289a8

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#define SQ_ALU_CONST_CACHE_VS_11 0x289ac

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#define SQ_ALU_CONST_CACHE_VS_12 0x289b0

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#define SQ_ALU_CONST_CACHE_VS_13 0x289b4

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#define SQ_ALU_CONST_CACHE_VS_14 0x289b8

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#define SQ_ALU_CONST_CACHE_VS_15 0x289bc

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#define SQ_ALU_CONST_CACHE_GS_0 0x289c0

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#define SQ_ALU_CONST_CACHE_GS_1 0x289c4

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#define SQ_ALU_CONST_CACHE_GS_2 0x289c8

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#define SQ_ALU_CONST_CACHE_GS_3 0x289cc

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#define SQ_ALU_CONST_CACHE_GS_4 0x289d0

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#define SQ_ALU_CONST_CACHE_GS_5 0x289d4

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#define SQ_ALU_CONST_CACHE_GS_6 0x289d8

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#define SQ_ALU_CONST_CACHE_GS_7 0x289dc

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#define SQ_ALU_CONST_CACHE_GS_8 0x289e0

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#define SQ_ALU_CONST_CACHE_GS_9 0x289e4

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#define SQ_ALU_CONST_CACHE_GS_10 0x289e8

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#define SQ_ALU_CONST_CACHE_GS_11 0x289ec

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#define SQ_ALU_CONST_CACHE_GS_12 0x289f0

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#define SQ_ALU_CONST_CACHE_GS_13 0x289f4

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#define SQ_ALU_CONST_CACHE_GS_14 0x289f8

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#define SQ_ALU_CONST_CACHE_GS_15 0x289fc

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#define CONFIG_MEMSIZE 0x5428

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#define CONFIG_CNTL 0x5424

Jerome Glisse

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#define CP_STALLED_STAT1 0x8674

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#define CP_STALLED_STAT2 0x8678

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#define CP_BUSY_STAT 0x867C

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#define CP_STAT 0x8680

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#define CP_COHER_BASE 0x85F8

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#define CP_DEBUG 0xC1FC

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#define R_0086D8_CP_ME_CNTL 0x86D8

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d3cb781

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#define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26)

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#define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF)

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#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)

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#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)

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#define CP_ME_RAM_DATA 0xC160

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#define CP_ME_RAM_RADDR 0xC158

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#define CP_ME_RAM_WADDR 0xC15C

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#define CP_MEQ_THRESHOLDS 0x8764

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#define MEQ_END(x) ((x) << 16)

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#define ROQ_END(x) ((x) << 24)

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#define CP_PERFMON_CNTL 0x87FC

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#define CP_PFP_UCODE_ADDR 0xC150

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#define CP_PFP_UCODE_DATA 0xC154

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#define CP_QUEUE_THRESHOLDS 0x8760

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#define ROQ_IB1_START(x) ((x) << 0)

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#define ROQ_IB2_START(x) ((x) << 8)

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#define CP_RB_BASE 0xC100

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#define CP_RB_CNTL 0xC104

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#define RB_BUFSZ(x) ((x) << 0)

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#define RB_BLKSZ(x) ((x) << 8)

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#define RB_NO_UPDATE (1 << 27)

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#define RB_RPTR_WR_ENA (1 << 31)

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#define BUF_SWAP_32BIT (2 << 16)

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#define CP_RB_RPTR 0x8700

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#define CP_RB_RPTR_ADDR 0xC10C

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#define RB_RPTR_SWAP(x) ((x) << 0)

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#define CP_RB_RPTR_ADDR_HI 0xC110

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#define CP_RB_RPTR_WR 0xC108

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#define CP_RB_WPTR 0xC114

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#define CP_RB_WPTR_ADDR 0xC118

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#define CP_RB_WPTR_ADDR_HI 0xC11C

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#define CP_RB_WPTR_DELAY 0x8704

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#define CP_ROQ_IB1_STAT 0x8784

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#define CP_ROQ_IB2_STAT 0x8788

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#define CP_SEM_WAIT_TIMER 0x85BC

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#define DB_DEBUG 0x9830

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#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)

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#define DB_DEPTH_BASE 0x2800C

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#define DB_HTILE_DATA_BASE 0x28014

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#define DB_HTILE_SURFACE 0x28D24

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#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)

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#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)

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#define C_028D24_HTILE_WIDTH 0xFFFFFFFE

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#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)

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#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)

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#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD

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#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)

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#define DB_WATERMARKS 0x9838

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#define DEPTH_FREE(x) ((x) << 0)

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#define DEPTH_FLUSH(x) ((x) << 5)

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#define DEPTH_PENDING_FREE(x) ((x) << 15)

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#define DEPTH_CACHELINE_FREE(x) ((x) << 20)

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#define DCP_TILING_CONFIG 0x6CA0

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#define PIPE_TILING(x) ((x) << 1)

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#define BANK_TILING(x) ((x) << 4)

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#define GROUP_SIZE(x) ((x) << 6)

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#define ROW_TILING(x) ((x) << 8)

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#define BANK_SWAPS(x) ((x) << 11)

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#define SAMPLE_SPLIT(x) ((x) << 14)

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#define BACKEND_MAP(x) ((x) << 16)

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#define GB_TILING_CONFIG 0x98F0

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2012-05-31 19:00:25 -0400

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#define PIPE_TILING__SHIFT 1

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#define PIPE_TILING__MASK 0x0000000e

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2009-09-08 10:10:24 +1000

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#define GC_USER_SHADER_PIPE_CONFIG 0x8954

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#define INACTIVE_QD_PIPES(x) ((x) << 8)

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#define INACTIVE_QD_PIPES_MASK 0x0000FF00

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#define INACTIVE_SIMDS(x) ((x) << 16)

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#define INACTIVE_SIMDS_MASK 0x00FF0000

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#define SQ_CONFIG 0x8c00

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# define VC_ENABLE (1 << 0)

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# define EXPORT_SRC_C (1 << 1)

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# define DX9_CONSTS (1 << 2)

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# define ALU_INST_PREFER_VECTOR (1 << 3)

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# define DX10_CLAMP (1 << 4)

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# define CLAUSE_SEQ_PRIO(x) ((x) << 8)

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# define PS_PRIO(x) ((x) << 24)

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# define VS_PRIO(x) ((x) << 26)

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# define GS_PRIO(x) ((x) << 28)

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# define ES_PRIO(x) ((x) << 30)

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#define SQ_GPR_RESOURCE_MGMT_1 0x8c04

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# define NUM_PS_GPRS(x) ((x) << 0)

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# define NUM_VS_GPRS(x) ((x) << 16)

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# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

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#define SQ_GPR_RESOURCE_MGMT_2 0x8c08

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# define NUM_GS_GPRS(x) ((x) << 0)

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# define NUM_ES_GPRS(x) ((x) << 16)

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#define SQ_THREAD_RESOURCE_MGMT 0x8c0c

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# define NUM_PS_THREADS(x) ((x) << 0)

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# define NUM_VS_THREADS(x) ((x) << 8)

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# define NUM_GS_THREADS(x) ((x) << 16)

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# define NUM_ES_THREADS(x) ((x) << 24)

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#define SQ_STACK_RESOURCE_MGMT_1 0x8c10

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# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

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#define SQ_STACK_RESOURCE_MGMT_2 0x8c14

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# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

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a39533b

2009-11-09 16:41:21 -0500

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#define SQ_ESGS_RING_BASE 0x8c40

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#define SQ_GSVS_RING_BASE 0x8c48

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#define SQ_ESTMP_RING_BASE 0x8c50

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#define SQ_GSTMP_RING_BASE 0x8c58

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#define SQ_VSTMP_RING_BASE 0x8c60

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#define SQ_PSTMP_RING_BASE 0x8c68

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#define SQ_FBUF_RING_BASE 0x8c70

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#define SQ_REDUC_RING_BASE 0x8c78

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2009-09-08 10:10:24 +1000

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#define GRBM_CNTL 0x8000

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# define GRBM_READ_TIMEOUT(x) ((x) << 0)

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#define GRBM_STATUS 0x8010

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#define CMDFIFO_AVAIL_MASK 0x0000001F

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#define GUI_ACTIVE (1<<31)

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#define GRBM_STATUS2 0x8014

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#define GRBM_SOFT_RESET 0x8020

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#define SOFT_RESET_CP (1<<0)

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21a8122

2010-07-02 12:58:16 -0400

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#define CG_THERMAL_STATUS 0x7F4

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#define ASIC_T(x) ((x) << 0)

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#define ASIC_T_MASK 0x1FF

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#define ASIC_T_SHIFT 0

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2009-09-08 10:10:24 +1000

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#define HDP_HOST_PATH_CNTL 0x2C00

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#define HDP_NONSURFACE_BASE 0x2C04

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#define HDP_NONSURFACE_INFO 0x2C08

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#define HDP_NONSURFACE_SIZE 0x2C0C

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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

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#define HDP_TILING_CONFIG 0x2F3C

Alex Deucher

812d046

2010-07-26 18:51:53 -0400

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#define HDP_DEBUG1 0x2F34

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2009-09-08 10:10:24 +1000

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#define MC_VM_AGP_TOP 0x2184

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#define MC_VM_AGP_BOT 0x2188

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#define MC_VM_AGP_BASE 0x218C

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#define MC_VM_FB_LOCATION 0x2180

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#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C

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#define ENABLE_L1_TLB (1 << 0)

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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

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#define ENABLE_L1_STRICT_ORDERING (1 << 2)

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#define SYSTEM_ACCESS_MODE_MASK 0x000000C0

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#define SYSTEM_ACCESS_MODE_SHIFT 6

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#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)

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#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)

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#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)

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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)

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#define ENABLE_SEMAPHORE_MODE (1 << 10)

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#define ENABLE_WAIT_L2_QUERY (1 << 11)

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#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)

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#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000

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#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12

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#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)

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#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000

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#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15

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#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0

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#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC

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#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204

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#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208

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#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C

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#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200

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#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4

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#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8

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#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210

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#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218

352

#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C

353

#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220

354

#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214

355

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190

356

#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF

357

#define LOGICAL_PAGE_NUMBER_SHIFT 0

358

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194

359

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198

360

361

#define PA_CL_ENHANCE 0x8A14

362

#define CLIP_VTX_REORDER_ENA (1 << 0)

363

#define NUM_CLIP_SEQ(x) ((x) << 1)

364

#define PA_SC_AA_CONFIG 0x28C04

365

#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40

366

#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44

367

#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48

368

#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C

369

#define S0_X(x) ((x) << 0)

370

#define S0_Y(x) ((x) << 4)

371

#define S1_X(x) ((x) << 8)

372

#define S1_Y(x) ((x) << 12)

373

#define S2_X(x) ((x) << 16)

374

#define S2_Y(x) ((x) << 20)

375

#define S3_X(x) ((x) << 24)

376

#define S3_Y(x) ((x) << 28)

377

#define S4_X(x) ((x) << 0)

378

#define S4_Y(x) ((x) << 4)

379

#define S5_X(x) ((x) << 8)

380

#define S5_Y(x) ((x) << 12)

381

#define S6_X(x) ((x) << 16)

382

#define S6_Y(x) ((x) << 20)

383

#define S7_X(x) ((x) << 24)

384

#define S7_Y(x) ((x) << 28)

385

#define PA_SC_CLIPRECT_RULE 0x2820c

386

#define PA_SC_ENHANCE 0x8BF0

387

#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

388

#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)

389

#define PA_SC_LINE_STIPPLE 0x28A0C

390

#define PA_SC_LINE_STIPPLE_STATE 0x8B10

391

#define PA_SC_MODE_CNTL 0x28A4C

392

#define PA_SC_MULTI_CHIP_CNTL 0x8B20

393

394

#define PA_SC_SCREEN_SCISSOR_TL 0x28030

395

#define PA_SC_GENERIC_SCISSOR_TL 0x28240

396

#define PA_SC_WINDOW_SCISSOR_TL 0x28204

397

398

#define PCIE_PORT_INDEX 0x0038

399

#define PCIE_PORT_DATA 0x003C

400

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

401

#define CHMAP 0x2004

402

#define NOOFCHAN_SHIFT 12

403

#define NOOFCHAN_MASK 0x00003000

404

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

405

#define RAMCFG 0x2408

406

#define NOOFBANK_SHIFT 0

407

#define NOOFBANK_MASK 0x00000001

408

#define NOOFRANK_SHIFT 1

409

#define NOOFRANK_MASK 0x00000002

410

#define NOOFROWS_SHIFT 2

411

#define NOOFROWS_MASK 0x0000001C

412

#define NOOFCOLS_SHIFT 5

413

#define NOOFCOLS_MASK 0x00000060

414

#define CHANSIZE_SHIFT 7

415

#define CHANSIZE_MASK 0x00000080

416

#define BURSTLENGTH_SHIFT 8

417

#define BURSTLENGTH_MASK 0x00000100

418

#define CHANSIZE_OVERRIDE (1 << 10)

419

420

#define SCRATCH_REG0 0x8500

421

#define SCRATCH_REG1 0x8504

422

#define SCRATCH_REG2 0x8508

423

#define SCRATCH_REG3 0x850C

424

#define SCRATCH_REG4 0x8510

425

#define SCRATCH_REG5 0x8514

426

#define SCRATCH_REG6 0x8518

427

#define SCRATCH_REG7 0x851C

428

#define SCRATCH_UMSK 0x8540

429

#define SCRATCH_ADDR 0x8544

430

431

#define SPI_CONFIG_CNTL 0x9100

432

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

433

#define DISABLE_INTERP_1 (1 << 5)

434

#define SPI_CONFIG_CNTL_1 0x913C

435

#define VTX_DONE_DELAY(x) ((x) << 0)

436

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

437

#define SPI_INPUT_Z 0x286D8

438

#define SPI_PS_IN_CONTROL_0 0x286CC

439

#define NUM_INTERP(x) ((x)<<0)

440

#define POSITION_ENA (1<<8)

441

#define POSITION_CENTROID (1<<9)

442

#define POSITION_ADDR(x) ((x)<<10)

443

#define PARAM_GEN(x) ((x)<<15)

444

#define PARAM_GEN_ADDR(x) ((x)<<19)

445

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

446

#define PERSP_GRADIENT_ENA (1<<28)

447

#define LINEAR_GRADIENT_ENA (1<<29)

448

#define POSITION_SAMPLE (1<<30)

449

#define BARYC_AT_SAMPLE_ENA (1<<31)

450

#define SPI_PS_IN_CONTROL_1 0x286D0

451

#define GEN_INDEX_PIX (1<<0)

452

#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)

453

#define FRONT_FACE_ENA (1<<8)

454

#define FRONT_FACE_CHAN(x) ((x)<<9)

455

#define FRONT_FACE_ALL_BITS (1<<11)

456

#define FRONT_FACE_ADDR(x) ((x)<<12)

457

#define FOG_ADDR(x) ((x)<<17)

458

#define FIXED_PT_POSITION_ENA (1<<24)

459

#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)

460

461

#define SQ_MS_FIFO_SIZES 0x8CF0

462

#define CACHE_FIFO_SIZE(x) ((x) << 0)

463

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

464

#define DONE_FIFO_HIWATER(x) ((x) << 16)

465

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

466

#define SQ_PGM_START_ES 0x28880

467

#define SQ_PGM_START_FS 0x28894

468

#define SQ_PGM_START_GS 0x2886C

469

#define SQ_PGM_START_PS 0x28840

470

#define SQ_PGM_RESOURCES_PS 0x28850

471

#define SQ_PGM_EXPORTS_PS 0x28854

472

#define SQ_PGM_CF_OFFSET_PS 0x288cc

473

#define SQ_PGM_START_VS 0x28858

474

#define SQ_PGM_RESOURCES_VS 0x28868

475

#define SQ_PGM_CF_OFFSET_VS 0x288d0

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

476

477

#define SQ_VTX_CONSTANT_WORD0_0 0x30000

478

#define SQ_VTX_CONSTANT_WORD1_0 0x30004

479

#define SQ_VTX_CONSTANT_WORD2_0 0x30008

480

# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)

481

# define SQ_VTXC_STRIDE(x) ((x) << 8)

482

# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)

483

# define SQ_ENDIAN_NONE 0

484

# define SQ_ENDIAN_8IN16 1

485

# define SQ_ENDIAN_8IN32 2

486

#define SQ_VTX_CONSTANT_WORD3_0 0x3000c

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

487

#define SQ_VTX_CONSTANT_WORD6_0 0x38018

488

#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)

489

#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)

490

#define SQ_TEX_VTX_INVALID_TEXTURE 0x0

491

#define SQ_TEX_VTX_INVALID_BUFFER 0x1

492

#define SQ_TEX_VTX_VALID_TEXTURE 0x2

493

#define SQ_TEX_VTX_VALID_BUFFER 0x3

494

495

496

#define SX_MISC 0x28350

Alex Deucher

a39533b

2009-11-09 16:41:21 -0500

[diff] [blame]

497

#define SX_MEMORY_EXPORT_BASE 0x9010

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

498

#define SX_DEBUG_1 0x9054

499

#define SMX_EVENT_RELEASE (1 << 0)

500

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

501

502

#define TA_CNTL_AUX 0x9508

503

#define DISABLE_CUBE_WRAP (1 << 0)

504

#define DISABLE_CUBE_ANISO (1 << 1)

505

#define SYNC_GRADIENT (1 << 24)

506

#define SYNC_WALKER (1 << 25)

507

#define SYNC_ALIGNER (1 << 26)

508

#define BILINEAR_PRECISION_6_BIT (0 << 31)

509

#define BILINEAR_PRECISION_8_BIT (1 << 31)

510

511

#define TC_CNTL 0x9608

512

#define TC_L2_SIZE(x) ((x)<<5)

513

#define L2_DISABLE_LATE_HIT (1<<9)

514

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

515

#define VC_ENHANCE 0x9714

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

516

517

#define VGT_CACHE_INVALIDATION 0x88C4

518

#define CACHE_INVALIDATION(x) ((x)<<0)

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define VGT_DMA_BASE 0x287E8

523

#define VGT_DMA_BASE_HI 0x287E4

524

#define VGT_ES_PER_GS 0x88CC

525

#define VGT_GS_PER_ES 0x88C8

526

#define VGT_GS_PER_VS 0x88E8

527

#define VGT_GS_VERTEX_REUSE 0x88D4

528

#define VGT_PRIMITIVE_TYPE 0x8958

529

#define VGT_NUM_INSTANCES 0x8974

530

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

531

#define DEALLOC_DIST_MASK 0x0000007F

532

#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10

533

#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14

534

#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18

535

#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c

536

#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44

537

#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48

538

#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c

539

#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50

540

#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8

541

#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8

542

#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8

543

#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08

544

#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC

545

#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC

546

#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC

547

#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

548

#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0

549

#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0

550

#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0

551

#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00

552

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

553

#define VGT_STRMOUT_EN 0x28AB0

554

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

555

#define VTX_REUSE_DEPTH_MASK 0x000000FF

556

#define VGT_EVENT_INITIATOR 0x28a90

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

557

# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

558

# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)

559

560

#define VM_CONTEXT0_CNTL 0x1410

561

#define ENABLE_CONTEXT (1 << 0)

562

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

563

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

564

#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490

565

#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0

566

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574

567

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594

568

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4

569

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554

570

#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470

571

#define REQUEST_TYPE(x) (((x) & 0xf) << 0)

572

#define RESPONSE_TYPE_MASK 0x000000F0

573

#define RESPONSE_TYPE_SHIFT 4

574

#define VM_L2_CNTL 0x1400

575

#define ENABLE_L2_CACHE (1 << 0)

576

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

577

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

578

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)

579

#define VM_L2_CNTL2 0x1404

580

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

581

#define INVALIDATE_L2_CACHE (1 << 1)

582

#define VM_L2_CNTL3 0x1408

583

#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)

584

#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)

585

#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)

586

#define VM_L2_STATUS 0x140C

587

#define L2_BUSY (1 << 0)

588

589

#define WAIT_UNTIL 0x8040

590

#define WAIT_2D_IDLE_bit (1 << 14)

591

#define WAIT_3D_IDLE_bit (1 << 15)

592

#define WAIT_2D_IDLECLEAN_bit (1 << 16)

593

#define WAIT_3D_IDLECLEAN_bit (1 << 17)

594

Alex Deucher

2012-09-27 15:08:35 -0400

[diff] [blame]

595

/* async DMA */

596

#define DMA_TILING_CONFIG 0x3ec4

597

#define DMA_CONFIG 0x3e4c

598

599

#define DMA_RB_CNTL 0xd000

600

# define DMA_RB_ENABLE (1 << 0)

601

# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */

602

# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */

603

# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)

604

# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */

605

# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */

606

#define DMA_RB_BASE 0xd004

607

#define DMA_RB_RPTR 0xd008

608

#define DMA_RB_WPTR 0xd00c

609

610

#define DMA_RB_RPTR_ADDR_HI 0xd01c

611

#define DMA_RB_RPTR_ADDR_LO 0xd020

612

613

#define DMA_IB_CNTL 0xd024

614

# define DMA_IB_ENABLE (1 << 0)

615

# define DMA_IB_SWAP_ENABLE (1 << 4)

616

#define DMA_IB_RPTR 0xd028

617

#define DMA_CNTL 0xd02c

618

# define TRAP_ENABLE (1 << 0)

619

# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)

620

# define SEM_WAIT_INT_ENABLE (1 << 2)

621

# define DATA_SWAP_ENABLE (1 << 3)

622

# define FENCE_SWAP_ENABLE (1 << 4)

623

# define CTXEMPTY_INT_ENABLE (1 << 28)

624

#define DMA_STATUS_REG 0xd034

625

# define DMA_IDLE (1 << 0)

626

#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044

627

#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048

628

#define DMA_MODE 0xd0bc

629

630

/* async DMA packets */

631

#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \

632

(((t) & 0x1) << 23) | \

633

(((s) & 0x1) << 22) | \

634

(((n) & 0xFFFF) << 0))

635

/* async DMA Packet types */

636

#define DMA_PACKET_WRITE 0x2

637

#define DMA_PACKET_COPY 0x3

638

#define DMA_PACKET_INDIRECT_BUFFER 0x4

639

#define DMA_PACKET_SEMAPHORE 0x5

640

#define DMA_PACKET_FENCE 0x6

641

#define DMA_PACKET_TRAP 0x7

642

#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */

643

#define DMA_PACKET_NOP 0xf

644

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

645

#define IH_RB_CNTL 0x3e00

646

# define IH_RB_ENABLE (1 << 0)

Alex Deucher

2012-09-27 15:08:35 -0400

[diff] [blame]

647

# define IH_RB_SIZE(x) ((x) << 1) /* log2 */

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

648

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

649

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

650

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

651

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

652

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

653

#define IH_RB_BASE 0x3e04

654

#define IH_RB_RPTR 0x3e08

655

#define IH_RB_WPTR 0x3e0c

656

# define RB_OVERFLOW (1 << 0)

657

# define WPTR_OFFSET_MASK 0x3fffc

658

#define IH_RB_WPTR_ADDR_HI 0x3e10

659

#define IH_RB_WPTR_ADDR_LO 0x3e14

660

#define IH_CNTL 0x3e18

661

# define ENABLE_INTR (1 << 0)

Alex Deucher

fcb857a

2011-07-06 19:52:27 +0000

[diff] [blame]

662

# define IH_MC_SWAP(x) ((x) << 1)

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

663

# define IH_MC_SWAP_NONE 0

664

# define IH_MC_SWAP_16BIT 1

665

# define IH_MC_SWAP_32BIT 2

666

# define IH_MC_SWAP_64BIT 3

667

# define RPTR_REARM (1 << 4)

668

# define MC_WRREQ_CREDIT(x) ((x) << 15)

669

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

670

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

671

#define RLC_CNTL 0x3f00

672

# define RLC_ENABLE (1 << 0)

673

#define RLC_HB_BASE 0x3f10

674

#define RLC_HB_CNTL 0x3f0c

675

#define RLC_HB_RPTR 0x3f20

676

#define RLC_HB_WPTR 0x3f1c

677

#define RLC_HB_WPTR_LSB_ADDR 0x3f14

678

#define RLC_HB_WPTR_MSB_ADDR 0x3f18

Marek Olšák

6759a0a

2012-08-09 16:34:17 +0200

[diff] [blame]

679

#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38

680

#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c

681

#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

682

#define RLC_MC_CNTL 0x3f44

683

#define RLC_UCODE_CNTL 0x3f48

684

#define RLC_UCODE_ADDR 0x3f2c

685

#define RLC_UCODE_DATA 0x3f30

686

Alex Deucher

c420c74

2012-03-20 17:18:39 -0400

[diff] [blame]

687

/* new for TN */

688

#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10

689

#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20

690

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

691

#define SRBM_SOFT_RESET 0xe60

Alex Deucher

2012-09-27 15:08:35 -0400

[diff] [blame]

692

# define SOFT_RESET_DMA (1 << 12)

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

693

# define SOFT_RESET_RLC (1 << 13)

Alex Deucher

2012-09-27 15:08:35 -0400

[diff] [blame]

694

# define RV770_SOFT_RESET_DMA (1 << 20)

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

695

696

#define CP_INT_CNTL 0xc124

697

# define CNTX_BUSY_INT_ENABLE (1 << 19)

698

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

699

# define SCRATCH_INT_ENABLE (1 << 25)

700

# define TIME_STAMP_INT_ENABLE (1 << 26)

701

# define IB2_INT_ENABLE (1 << 29)

702

# define IB1_INT_ENABLE (1 << 30)

703

# define RB_INT_ENABLE (1 << 31)

704

#define CP_INT_STATUS 0xc128

705

# define SCRATCH_INT_STAT (1 << 25)

706

# define TIME_STAMP_INT_STAT (1 << 26)

707

# define IB2_INT_STAT (1 << 29)

708

# define IB1_INT_STAT (1 << 30)

709

# define RB_INT_STAT (1 << 31)

710

711

#define GRBM_INT_CNTL 0x8060

712

# define RDERR_INT_ENABLE (1 << 0)

713

# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)

714

# define GUI_IDLE_INT_ENABLE (1 << 19)

715

716

#define INTERRUPT_CNTL 0x5468

717

# define IH_DUMMY_RD_OVERRIDE (1 << 0)

718

# define IH_DUMMY_RD_EN (1 << 1)

719

# define IH_REQ_NONSNOOP_EN (1 << 3)

720

# define GEN_IH_INT_EN (1 << 8)

721

#define INTERRUPT_CNTL2 0x546c

722

723

#define D1MODE_VBLANK_STATUS 0x6534

724

#define D2MODE_VBLANK_STATUS 0x6d34

725

# define DxMODE_VBLANK_OCCURRED (1 << 0)

726

# define DxMODE_VBLANK_ACK (1 << 4)

727

# define DxMODE_VBLANK_STAT (1 << 12)

728

# define DxMODE_VBLANK_INTERRUPT (1 << 16)

729

# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)

730

#define D1MODE_VLINE_STATUS 0x653c

731

#define D2MODE_VLINE_STATUS 0x6d3c

732

# define DxMODE_VLINE_OCCURRED (1 << 0)

733

# define DxMODE_VLINE_ACK (1 << 4)

734

# define DxMODE_VLINE_STAT (1 << 12)

735

# define DxMODE_VLINE_INTERRUPT (1 << 16)

736

# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)

737

#define DxMODE_INT_MASK 0x6540

738

# define D1MODE_VBLANK_INT_MASK (1 << 0)

739

# define D1MODE_VLINE_INT_MASK (1 << 4)

740

# define D2MODE_VBLANK_INT_MASK (1 << 8)

741

# define D2MODE_VLINE_INT_MASK (1 << 12)

742

#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc

743

# define DC_HPD1_INTERRUPT (1 << 18)

744

# define DC_HPD2_INTERRUPT (1 << 19)

745

#define DISP_INTERRUPT_STATUS 0x7edc

746

# define LB_D1_VLINE_INTERRUPT (1 << 2)

747

# define LB_D2_VLINE_INTERRUPT (1 << 3)

748

# define LB_D1_VBLANK_INTERRUPT (1 << 4)

749

# define LB_D2_VBLANK_INTERRUPT (1 << 5)

750

# define DACA_AUTODETECT_INTERRUPT (1 << 16)

751

# define DACB_AUTODETECT_INTERRUPT (1 << 17)

752

# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)

753

# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)

754

# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)

755

# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

756

#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

757

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8

758

# define DC_HPD4_INTERRUPT (1 << 14)

759

# define DC_HPD4_RX_INTERRUPT (1 << 15)

760

# define DC_HPD3_INTERRUPT (1 << 28)

761

# define DC_HPD1_RX_INTERRUPT (1 << 29)

762

# define DC_HPD2_RX_INTERRUPT (1 << 30)

763

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec

764

# define DC_HPD3_RX_INTERRUPT (1 << 0)

765

# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)

766

# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)

767

# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)

768

# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)

769

# define AUX1_SW_DONE_INTERRUPT (1 << 5)

770

# define AUX1_LS_DONE_INTERRUPT (1 << 6)

771

# define AUX2_SW_DONE_INTERRUPT (1 << 7)

772

# define AUX2_LS_DONE_INTERRUPT (1 << 8)

773

# define AUX3_SW_DONE_INTERRUPT (1 << 9)

774

# define AUX3_LS_DONE_INTERRUPT (1 << 10)

775

# define AUX4_SW_DONE_INTERRUPT (1 << 11)

776

# define AUX4_LS_DONE_INTERRUPT (1 << 12)

777

# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)

778

# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)

779

/* DCE 3.2 */

780

# define AUX5_SW_DONE_INTERRUPT (1 << 15)

781

# define AUX5_LS_DONE_INTERRUPT (1 << 16)

782

# define AUX6_SW_DONE_INTERRUPT (1 << 17)

783

# define AUX6_LS_DONE_INTERRUPT (1 << 18)

784

# define DC_HPD5_INTERRUPT (1 << 19)

785

# define DC_HPD5_RX_INTERRUPT (1 << 20)

786

# define DC_HPD6_INTERRUPT (1 << 21)

787

# define DC_HPD6_RX_INTERRUPT (1 << 22)

788

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

789

#define DACA_AUTO_DETECT_CONTROL 0x7828

790

#define DACB_AUTO_DETECT_CONTROL 0x7a28

791

#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028

792

#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128

793

# define DACx_AUTODETECT_MODE(x) ((x) << 0)

794

# define DACx_AUTODETECT_MODE_NONE 0

795

# define DACx_AUTODETECT_MODE_CONNECT 1

796

# define DACx_AUTODETECT_MODE_DISCONNECT 2

797

# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)

798

/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */

799

# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)

800

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

801

#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038

802

#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138

803

#define DACA_AUTODETECT_INT_CONTROL 0x7838

804

#define DACB_AUTODETECT_INT_CONTROL 0x7a38

805

# define DACx_AUTODETECT_ACK (1 << 0)

806

# define DACx_AUTODETECT_INT_ENABLE (1 << 16)

807

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

808

#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00

809

#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10

810

#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24

811

# define DC_HOT_PLUG_DETECTx_EN (1 << 0)

812

813

#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04

814

#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14

815

#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28

816

# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)

817

# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)

818

819

/* DCE 3.0 */

820

#define DC_HPD1_INT_STATUS 0x7d00

821

#define DC_HPD2_INT_STATUS 0x7d0c

822

#define DC_HPD3_INT_STATUS 0x7d18

823

#define DC_HPD4_INT_STATUS 0x7d24

824

/* DCE 3.2 */

825

#define DC_HPD5_INT_STATUS 0x7dc0

826

#define DC_HPD6_INT_STATUS 0x7df4

827

# define DC_HPDx_INT_STATUS (1 << 0)

828

# define DC_HPDx_SENSE (1 << 1)

829

# define DC_HPDx_RX_INT_STATUS (1 << 8)

830

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

831

#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08

832

#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18

833

#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c

834

# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)

835

# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)

836

# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

837

/* DCE 3.0 */

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

838

#define DC_HPD1_INT_CONTROL 0x7d04

839

#define DC_HPD2_INT_CONTROL 0x7d10

840

#define DC_HPD3_INT_CONTROL 0x7d1c

841

#define DC_HPD4_INT_CONTROL 0x7d28

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

842

/* DCE 3.2 */

843

#define DC_HPD5_INT_CONTROL 0x7dc4

844

#define DC_HPD6_INT_CONTROL 0x7df8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

845

# define DC_HPDx_INT_ACK (1 << 0)

846

# define DC_HPDx_INT_POLARITY (1 << 8)

847

# define DC_HPDx_INT_EN (1 << 16)

848

# define DC_HPDx_RX_INT_ACK (1 << 20)

849

# define DC_HPDx_RX_INT_EN (1 << 24)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

850

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

851

/* DCE 3.0 */

852

#define DC_HPD1_CONTROL 0x7d08

853

#define DC_HPD2_CONTROL 0x7d14

854

#define DC_HPD3_CONTROL 0x7d20

855

#define DC_HPD4_CONTROL 0x7d2c

856

/* DCE 3.2 */

857

#define DC_HPD5_CONTROL 0x7dc8

858

#define DC_HPD6_CONTROL 0x7dfc

859

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

860

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

861

/* DCE 3.2 */

862

# define DC_HPDx_EN (1 << 28)

863

Alex Deucher

6f34be5

2010-11-21 10:59:01 -0500

[diff] [blame]

864

#define D1GRPH_INTERRUPT_STATUS 0x6158

865

#define D2GRPH_INTERRUPT_STATUS 0x6958

866

# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)

867

# define DxGRPH_PFLIP_INT_CLEAR (1 << 8)

868

#define D1GRPH_INTERRUPT_CONTROL 0x615c

869

#define D2GRPH_INTERRUPT_CONTROL 0x695c

870

# define DxGRPH_PFLIP_INT_MASK (1 << 0)

871

# define DxGRPH_PFLIP_INT_TYPE (1 << 8)

872

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

873

/* PCIE link stuff */

874

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

875

# define LC_POINT_7_PLUS_EN (1 << 6)

876

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

877

# define LC_LINK_WIDTH_SHIFT 0

878

# define LC_LINK_WIDTH_MASK 0x7

879

# define LC_LINK_WIDTH_X0 0

880

# define LC_LINK_WIDTH_X1 1

881

# define LC_LINK_WIDTH_X2 2

882

# define LC_LINK_WIDTH_X4 3

883

# define LC_LINK_WIDTH_X8 4

884

# define LC_LINK_WIDTH_X16 6

885

# define LC_LINK_WIDTH_RD_SHIFT 4

886

# define LC_LINK_WIDTH_RD_MASK 0x70

887

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

888

# define LC_RECONFIG_NOW (1 << 8)

889

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

890

# define LC_RENEGOTIATE_EN (1 << 10)

891

# define LC_SHORT_RECONFIG_EN (1 << 11)

892

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

893

# define LC_UPCONFIGURE_DIS (1 << 13)

894

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

895

# define LC_GEN2_EN_STRAP (1 << 0)

896

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

897

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

898

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

899

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

900

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

901

# define LC_CURRENT_DATA_RATE (1 << 11)

902

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

903

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

904

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

905

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

906

#define MM_CFGREGS_CNTL 0x544c

907

# define MM_WR_TO_CFG_EN (1 << 3)

908

#define LINK_CNTL2 0x88 /* F0 */

909

# define TARGET_LINK_SPEED_MASK (0xf << 0)

910

# define SELECTABLE_DEEMPHASIS (1 << 6)

911

Alex Deucher

3a2a67a

2012-03-28 13:19:06 -0400

[diff] [blame]

912

/* Audio clocks */

913

#define DCCG_AUDIO_DTO0_PHASE 0x0514

914

#define DCCG_AUDIO_DTO0_MODULE 0x0518

915

#define DCCG_AUDIO_DTO0_LOAD 0x051c

916

# define DTO_LOAD (1 << 31)

917

#define DCCG_AUDIO_DTO0_CNTL 0x0520

918

919

#define DCCG_AUDIO_DTO1_PHASE 0x0524

920

#define DCCG_AUDIO_DTO1_MODULE 0x0528

921

#define DCCG_AUDIO_DTO1_LOAD 0x052c

922

#define DCCG_AUDIO_DTO1_CNTL 0x0530

923

924

#define DCCG_AUDIO_DTO_SELECT 0x0534

925

926

/* digital blocks */

927

#define TMDSA_CNTL 0x7880

928

# define TMDSA_HDMI_EN (1 << 2)

929

#define LVTMA_CNTL 0x7a80

930

# define LVTMA_HDMI_EN (1 << 2)

931

#define DDIA_CNTL 0x7200

932

# define DDIA_HDMI_EN (1 << 2)

933

#define DIG0_CNTL 0x75a0

934

# define DIG_MODE(x) (((x) & 7) << 8)

935

# define DIG_MODE_DP 0

936

# define DIG_MODE_LVDS 1

937

# define DIG_MODE_TMDS_DVI 2

938

# define DIG_MODE_TMDS_HDMI 3

939

# define DIG_MODE_SDVO 4

940

#define DIG1_CNTL 0x79a0

941

942

/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one

943

* instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly

944

* different due to the new DIG blocks, but also have 2 instances.

945

* DCE 3.0 HDMI blocks are part of each DIG encoder.

946

*/

947

948

/* rs6xx/rs740/r6xx/dce3 */

949

#define HDMI0_CONTROL 0x7400

950

/* rs6xx/rs740/r6xx */

951

# define HDMI0_ENABLE (1 << 0)

952

# define HDMI0_STREAM(x) (((x) & 3) << 2)

953

# define HDMI0_STREAM_TMDSA 0

954

# define HDMI0_STREAM_LVTMA 1

955

# define HDMI0_STREAM_DVOA 2

956

# define HDMI0_STREAM_DDIA 3

957

/* rs6xx/r6xx/dce3 */

958

# define HDMI0_ERROR_ACK (1 << 8)

959

# define HDMI0_ERROR_MASK (1 << 9)

960

#define HDMI0_STATUS 0x7404

961

# define HDMI0_ACTIVE_AVMUTE (1 << 0)

962

# define HDMI0_AUDIO_ENABLE (1 << 4)

963

# define HDMI0_AZ_FORMAT_WTRIG (1 << 28)

964

# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)

965

#define HDMI0_AUDIO_PACKET_CONTROL 0x7408

966

# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)

967

# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)

968

# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)

969

# define HDMI0_AUDIO_TEST_EN (1 << 12)

970

# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)

971

# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)

972

# define HDMI0_60958_CS_UPDATE (1 << 26)

973

# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)

974

# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)

975

#define HDMI0_AUDIO_CRC_CONTROL 0x740c

976

# define HDMI0_AUDIO_CRC_EN (1 << 0)

977

#define HDMI0_VBI_PACKET_CONTROL 0x7410

978

# define HDMI0_NULL_SEND (1 << 0)

979

# define HDMI0_GC_SEND (1 << 4)

980

# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */

981

#define HDMI0_INFOFRAME_CONTROL0 0x7414

982

# define HDMI0_AVI_INFO_SEND (1 << 0)

983

# define HDMI0_AVI_INFO_CONT (1 << 1)

984

# define HDMI0_AUDIO_INFO_SEND (1 << 4)

985

# define HDMI0_AUDIO_INFO_CONT (1 << 5)

986

# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */

987

# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)

988

# define HDMI0_MPEG_INFO_SEND (1 << 8)

989

# define HDMI0_MPEG_INFO_CONT (1 << 9)

990

# define HDMI0_MPEG_INFO_UPDATE (1 << 10)

991

#define HDMI0_INFOFRAME_CONTROL1 0x7418

992

# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)

993

# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)

994

# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)

995

#define HDMI0_GENERIC_PACKET_CONTROL 0x741c

996

# define HDMI0_GENERIC0_SEND (1 << 0)

997

# define HDMI0_GENERIC0_CONT (1 << 1)

998

# define HDMI0_GENERIC0_UPDATE (1 << 2)

999

# define HDMI0_GENERIC1_SEND (1 << 4)

1000

# define HDMI0_GENERIC1_CONT (1 << 5)

1001

# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)

1002

# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)

1003

#define HDMI0_GC 0x7428

1004

# define HDMI0_GC_AVMUTE (1 << 0)

1005

#define HDMI0_AVI_INFO0 0x7454

1006

# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

1007

# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)

1008

# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)

1009

# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)

1010

# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)

1011

# define HDMI0_AVI_INFO_Y_RGB 0

1012

# define HDMI0_AVI_INFO_Y_YCBCR422 1

1013

# define HDMI0_AVI_INFO_Y_YCBCR444 2

1014

# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)

1015

# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)

1016

# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)

1017

# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)

1018

# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)

1019

# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)

1020

# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)

1021

#define HDMI0_AVI_INFO1 0x7458

1022

# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

1023

# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

1024

# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)

1025

#define HDMI0_AVI_INFO2 0x745c

1026

# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)

1027

# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)

1028

#define HDMI0_AVI_INFO3 0x7460

1029

# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)

1030

# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)

1031

#define HDMI0_MPEG_INFO0 0x7464

1032

# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

1033

# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)

1034

# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)

1035

# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)

1036

#define HDMI0_MPEG_INFO1 0x7468

1037

# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)

1038

# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)

1039

# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)

1040

#define HDMI0_GENERIC0_HDR 0x746c

1041

#define HDMI0_GENERIC0_0 0x7470

1042

#define HDMI0_GENERIC0_1 0x7474

1043

#define HDMI0_GENERIC0_2 0x7478

1044

#define HDMI0_GENERIC0_3 0x747c

1045

#define HDMI0_GENERIC0_4 0x7480

1046

#define HDMI0_GENERIC0_5 0x7484

1047

#define HDMI0_GENERIC0_6 0x7488

1048

#define HDMI0_GENERIC1_HDR 0x748c

1049

#define HDMI0_GENERIC1_0 0x7490

1050

#define HDMI0_GENERIC1_1 0x7494

1051

#define HDMI0_GENERIC1_2 0x7498

1052

#define HDMI0_GENERIC1_3 0x749c

1053

#define HDMI0_GENERIC1_4 0x74a0

1054

#define HDMI0_GENERIC1_5 0x74a4

1055

#define HDMI0_GENERIC1_6 0x74a8

1056

#define HDMI0_ACR_32_0 0x74ac

1057

# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)

1058

#define HDMI0_ACR_32_1 0x74b0

1059

# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)

1060

#define HDMI0_ACR_44_0 0x74b4

1061

# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)

1062

#define HDMI0_ACR_44_1 0x74b8

1063

# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)

1064

#define HDMI0_ACR_48_0 0x74bc

1065

# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)

1066

#define HDMI0_ACR_48_1 0x74c0

1067

# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)

1068

#define HDMI0_ACR_STATUS_0 0x74c4

1069

#define HDMI0_ACR_STATUS_1 0x74c8

1070

#define HDMI0_AUDIO_INFO0 0x74cc

1071

# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

1072

# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)

1073

#define HDMI0_AUDIO_INFO1 0x74d0

1074

# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)

1075

# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)

1076

# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)

1077

# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

1078

#define HDMI0_60958_0 0x74d4

1079

# define HDMI0_60958_CS_A(x) (((x) & 1) << 0)

1080

# define HDMI0_60958_CS_B(x) (((x) & 1) << 1)

1081

# define HDMI0_60958_CS_C(x) (((x) & 1) << 2)

1082

# define HDMI0_60958_CS_D(x) (((x) & 3) << 3)

1083

# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)

1084

# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)

1085

# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)

1086

# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)

1087

# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

1088

# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)

1089

#define HDMI0_60958_1 0x74d8

1090

# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)

1091

# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)

1092

# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)

1093

# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)

1094

# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)

1095

#define HDMI0_ACR_PACKET_CONTROL 0x74dc

1096

# define HDMI0_ACR_SEND (1 << 0)

1097

# define HDMI0_ACR_CONT (1 << 1)

1098

# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)

1099

# define HDMI0_ACR_HW 0

1100

# define HDMI0_ACR_32 1

1101

# define HDMI0_ACR_44 2

1102

# define HDMI0_ACR_48 3

1103

# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */

1104

# define HDMI0_ACR_AUTO_SEND (1 << 12)

1105

#define HDMI0_RAMP_CONTROL0 0x74e0

1106

# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)

1107

#define HDMI0_RAMP_CONTROL1 0x74e4

1108

# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)

1109

#define HDMI0_RAMP_CONTROL2 0x74e8

1110

# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)

1111

#define HDMI0_RAMP_CONTROL3 0x74ec

1112

# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)

1113

/* HDMI0_60958_2 is r7xx only */

1114

#define HDMI0_60958_2 0x74f0

1115

# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)

1116

# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)

1117

# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)

1118

# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)

1119

# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)

1120

# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)

1121

/* r6xx only; second instance starts at 0x7700 */

1122

#define HDMI1_CONTROL 0x7700

1123

#define HDMI1_STATUS 0x7704

1124

#define HDMI1_AUDIO_PACKET_CONTROL 0x7708

1125

/* DCE3; second instance starts at 0x7800 NOT 0x7700 */

1126

#define DCE3_HDMI1_CONTROL 0x7800

1127

#define DCE3_HDMI1_STATUS 0x7804

1128

#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808

1129

/* DCE3.2 (for interrupts) */

1130

#define AFMT_STATUS 0x7600

1131

# define AFMT_AUDIO_ENABLE (1 << 4)

1132

# define AFMT_AZ_FORMAT_WTRIG (1 << 28)

1133

# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)

1134

# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)

1135

#define AFMT_AUDIO_PACKET_CONTROL 0x7604

1136

# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)

1137

# define AFMT_AUDIO_TEST_EN (1 << 12)

1138

# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)

1139

# define AFMT_60958_CS_UPDATE (1 << 26)

1140

# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

1141

# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)

1142

# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)

1143

# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)

Rafał Miłecki

c6543a6

2012-04-28 23:35:24 +0200

[diff] [blame]

1144

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1145

/*

1146

* PM4

1147

*/

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1148

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1149

(((reg) >> 2) & 0xFFFF) | \

1150

((n) & 0x3FFF) << 16)

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1151

#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1152

(((op) & 0xFF) << 8) | \

1153

((n) & 0x3FFF) << 16)

1154

1155

/* Packet 3 types */

1156

#define PACKET3_NOP 0x10

1157

#define PACKET3_INDIRECT_BUFFER_END 0x17

1158

#define PACKET3_SET_PREDICATION 0x20

1159

#define PACKET3_REG_RMW 0x21

1160

#define PACKET3_COND_EXEC 0x22

1161

#define PACKET3_PRED_EXEC 0x23

1162

#define PACKET3_START_3D_CMDBUF 0x24

1163

#define PACKET3_DRAW_INDEX_2 0x27

1164

#define PACKET3_CONTEXT_CONTROL 0x28

1165

#define PACKET3_DRAW_INDEX_IMMD_BE 0x29

1166

#define PACKET3_INDEX_TYPE 0x2A

1167

#define PACKET3_DRAW_INDEX 0x2B

1168

#define PACKET3_DRAW_INDEX_AUTO 0x2D

1169

#define PACKET3_DRAW_INDEX_IMMD 0x2E

1170

#define PACKET3_NUM_INSTANCES 0x2F

1171

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

1172

#define PACKET3_INDIRECT_BUFFER_MP 0x38

1173

#define PACKET3_MEM_SEMAPHORE 0x39

Christian König

0be7043

2012-03-07 11:28:57 +0100

[diff] [blame]

1174

# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)

Christian König

15d3332

2011-09-15 19:02:22 +0200

[diff] [blame]

1175

# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)

1176

# define PACKET3_SEM_SEL_WAIT (0x7 << 29)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1177

#define PACKET3_MPEG_INDEX 0x3A

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

1178

#define PACKET3_COPY_DW 0x3B

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1179

#define PACKET3_WAIT_REG_MEM 0x3C

1180

#define PACKET3_MEM_WRITE 0x3D

1181

#define PACKET3_INDIRECT_BUFFER 0x32

Alex Deucher

b997a8b

2012-12-03 18:07:25 -0500

[diff] [blame]

1182

#define PACKET3_CP_DMA 0x41

1183

/* 1. header

1184

* 2. SRC_ADDR_LO [31:0]

1185

* 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]

1186

* 4. DST_ADDR_LO [31:0]

1187

* 5. DST_ADDR_HI [7:0]

1188

* 6. COMMAND [29:22] | BYTE_COUNT [20:0]

1189

*/

1190

# define PACKET3_CP_DMA_CP_SYNC (1 << 31)

1191

/* COMMAND */

1192

# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_SAS (1 << 26)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_DAS (1 << 27)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)

1213

# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1214

#define PACKET3_SURFACE_SYNC 0x43

1215

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

1216

# define PACKET3_TC_ACTION_ENA (1 << 23)

1217

# define PACKET3_VC_ACTION_ENA (1 << 24)

1218

# define PACKET3_CB_ACTION_ENA (1 << 25)

1219

# define PACKET3_DB_ACTION_ENA (1 << 26)

1220

# define PACKET3_SH_ACTION_ENA (1 << 27)

1221

# define PACKET3_SMX_ACTION_ENA (1 << 28)

1222

#define PACKET3_ME_INITIALIZE 0x44

1223

#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

1224

#define PACKET3_COND_WRITE 0x45

1225

#define PACKET3_EVENT_WRITE 0x46

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

1226

#define EVENT_TYPE(x) ((x) << 0)

1227

#define EVENT_INDEX(x) ((x) << 8)

1228

/* 0 - any non-TS event

1229

* 1 - ZPASS_DONE

1230

* 2 - SAMPLE_PIPELINESTAT

1231

* 3 - SAMPLE_STREAMOUTSTAT*

1232

* 4 - *S_PARTIAL_FLUSH

1233

* 5 - TS events

1234

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1235

#define PACKET3_EVENT_WRITE_EOP 0x47

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

1236

#define DATA_SEL(x) ((x) << 29)

1237

/* 0 - discard

1238

* 1 - send low 32bit data

1239

* 2 - send 64bit data

1240

* 3 - send 64bit counter value

1241

*/

1242

#define INT_SEL(x) ((x) << 24)

1243

/* 0 - none

1244

* 1 - interrupt only (DATA_SEL = 0)

1245

* 2 - interrupt when data write is confirmed

1246

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1247

#define PACKET3_ONE_REG_WRITE 0x57

1248

#define PACKET3_SET_CONFIG_REG 0x68

1249

#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000

1250

#define PACKET3_SET_CONFIG_REG_END 0x0000ac00

1251

#define PACKET3_SET_CONTEXT_REG 0x69

1252

#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000

1253

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

1254

#define PACKET3_SET_ALU_CONST 0x6A

1255

#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000

1256

#define PACKET3_SET_ALU_CONST_END 0x00032000

1257

#define PACKET3_SET_BOOL_CONST 0x6B

1258

#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380

1259

#define PACKET3_SET_BOOL_CONST_END 0x00040000

1260

#define PACKET3_SET_LOOP_CONST 0x6C

1261

#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200

1262

#define PACKET3_SET_LOOP_CONST_END 0x0003e380

1263

#define PACKET3_SET_RESOURCE 0x6D

1264

#define PACKET3_SET_RESOURCE_OFFSET 0x00038000

1265

#define PACKET3_SET_RESOURCE_END 0x0003c000

1266

#define PACKET3_SET_SAMPLER 0x6E

1267

#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000

1268

#define PACKET3_SET_SAMPLER_END 0x0003cff0

1269

#define PACKET3_SET_CTL_CONST 0x6F

1270

#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0

1271

#define PACKET3_SET_CTL_CONST_END 0x0003e200

Alex Deucher

7c77bf2

2012-06-14 22:06:37 +0200

[diff] [blame]

1272

#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1273

#define PACKET3_SURFACE_BASE_UPDATE 0x73

1274

1275

1276

#define R_008020_GRBM_SOFT_RESET 0x8020

1277

#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)

1278

#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)

1279

#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)

1280

#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)

1281

#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)

1282

#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)

1283

#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)

1284

#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)

1285

#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)

1286

#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)

1287

#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)

1288

#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)

1289

#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)

1290

#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)

1291

#define R_008010_GRBM_STATUS 0x8010

1292

#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)

1293

#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)

1294

#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)

1295

#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)

1296

#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)

1297

#define S_008010_VC_BUSY(x) (((x) & 1) << 11)

1298

#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)

1299

#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)

1300

#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)

1301

#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)

1302

#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)

1303

#define S_008010_TC_BUSY(x) (((x) & 1) << 19)

1304

#define S_008010_SX_BUSY(x) (((x) & 1) << 20)

1305

#define S_008010_SH_BUSY(x) (((x) & 1) << 21)

1306

#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)

1307

#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)

1308

#define S_008010_SC_BUSY(x) (((x) & 1) << 24)

1309

#define S_008010_PA_BUSY(x) (((x) & 1) << 25)

1310

#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)

1311

#define S_008010_CR_BUSY(x) (((x) & 1) << 27)

1312

#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)

1313

#define S_008010_CP_BUSY(x) (((x) & 1) << 29)

1314

#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)

1315

#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)

1316

#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)

1317

#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)

1318

#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)

1319

#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)

1320

#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)

1321

#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)

1322

#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)

1323

#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)

Alex Deucher

f13f773

2013-01-18 18:12:22 -0500

[diff] [blame]

1324

#define G_008010_TA_BUSY(x) (((x) >> 14) & 1)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1325

#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)

1326

#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)

1327

#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)

1328

#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)

1329

#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)

1330

#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)

1331

#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)

1332

#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)

1333

#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)

1334

#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)

1335

#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)

1336

#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)

1337

#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)

1338

#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)

1339

#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)

1340

#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)

1341

#define R_008014_GRBM_STATUS2 0x8014

1342

#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)

1343

#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)

1344

#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)

1345

#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)

1346

#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)

1347

#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)

1348

#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)

1349

#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)

1350

#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)

1351

#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)

1352

#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)

1353

#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)

1354

#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)

1355

#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)

1356

#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)

1357

#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)

1358

#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)

1359

#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)

1360

#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)

1361

#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)

1362

#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)

1363

#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)

1364

#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)

1365

#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)

1366

#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)

1367

#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)

1368

#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)

1369

#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)

1370

#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)

1371

#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)

1372

#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)

1373

#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)

1374

#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)

1375

#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)

1376

#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)

1377

#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)

1378

#define R_000E50_SRBM_STATUS 0x0E50

1379

#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)

1380

#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)

1381

#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)

1382

#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)

1383

#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)

1384

#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)

1385

#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)

1386

#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)

1387

#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)

1388

#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)

1389

#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)

1390

#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)

1391

#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)

Alex Deucher

f13f773

2013-01-18 18:12:22 -0500

[diff] [blame]

1392

#define G_000E50_IH_BUSY(x) (((x) >> 17) & 1)

Jerome Glisse

1a029b7

2009-10-06 19:04:30 +0200

[diff] [blame]

1393

#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1394

#define R_000E60_SRBM_SOFT_RESET 0x0E60

1395

#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)

1396

#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)

1397

#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)

1398

#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)

1399

#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)

1400

#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)

1401

#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)

1402

#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)

1403

#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)

1404

#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)

1405

#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)

1406

#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)

1407

#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)

1408

#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)

1409

Dave Airlie

23956df

2009-11-23 12:01:09 +1000

[diff] [blame]

1410

#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1411

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1412

#define R_028C04_PA_SC_AA_CONFIG 0x028C04

1413

#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)

1414

#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)

1415

#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC

1416

#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)

1417

#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)

1418

#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF

1419

#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)

1420

#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)

1421

#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1422

#define R_0280E0_CB_COLOR0_FRAG 0x0280E0

1423

#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1424

#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1425

#define C_0280E0_BASE_256B 0x00000000

1426

#define R_0280E4_CB_COLOR1_FRAG 0x0280E4

1427

#define R_0280E8_CB_COLOR2_FRAG 0x0280E8

1428

#define R_0280EC_CB_COLOR3_FRAG 0x0280EC

1429

#define R_0280F0_CB_COLOR4_FRAG 0x0280F0

1430

#define R_0280F4_CB_COLOR5_FRAG 0x0280F4

1431

#define R_0280F8_CB_COLOR6_FRAG 0x0280F8

1432

#define R_0280FC_CB_COLOR7_FRAG 0x0280FC

1433

#define R_0280C0_CB_COLOR0_TILE 0x0280C0

1434

#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1435

#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1436

#define C_0280C0_BASE_256B 0x00000000

1437

#define R_0280C4_CB_COLOR1_TILE 0x0280C4

1438

#define R_0280C8_CB_COLOR2_TILE 0x0280C8

1439

#define R_0280CC_CB_COLOR3_TILE 0x0280CC

1440

#define R_0280D0_CB_COLOR4_TILE 0x0280D0

1441

#define R_0280D4_CB_COLOR5_TILE 0x0280D4

1442

#define R_0280D8_CB_COLOR6_TILE 0x0280D8

1443

#define R_0280DC_CB_COLOR7_TILE 0x0280DC

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1444

#define R_0280A0_CB_COLOR0_INFO 0x0280A0

1445

#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)

1446

#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)

1447

#define C_0280A0_ENDIAN 0xFFFFFFFC

1448

#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)

1449

#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)

1450

#define C_0280A0_FORMAT 0xFFFFFF03

1451

#define V_0280A0_COLOR_INVALID 0x00000000

1452

#define V_0280A0_COLOR_8 0x00000001

1453

#define V_0280A0_COLOR_4_4 0x00000002

1454

#define V_0280A0_COLOR_3_3_2 0x00000003

1455

#define V_0280A0_COLOR_16 0x00000005

1456

#define V_0280A0_COLOR_16_FLOAT 0x00000006

1457

#define V_0280A0_COLOR_8_8 0x00000007

1458

#define V_0280A0_COLOR_5_6_5 0x00000008

1459

#define V_0280A0_COLOR_6_5_5 0x00000009

1460

#define V_0280A0_COLOR_1_5_5_5 0x0000000A

1461

#define V_0280A0_COLOR_4_4_4_4 0x0000000B

1462

#define V_0280A0_COLOR_5_5_5_1 0x0000000C

1463

#define V_0280A0_COLOR_32 0x0000000D

1464

#define V_0280A0_COLOR_32_FLOAT 0x0000000E

1465

#define V_0280A0_COLOR_16_16 0x0000000F

1466

#define V_0280A0_COLOR_16_16_FLOAT 0x00000010

1467

#define V_0280A0_COLOR_8_24 0x00000011

1468

#define V_0280A0_COLOR_8_24_FLOAT 0x00000012

1469

#define V_0280A0_COLOR_24_8 0x00000013

1470

#define V_0280A0_COLOR_24_8_FLOAT 0x00000014

1471

#define V_0280A0_COLOR_10_11_11 0x00000015

1472

#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016

1473

#define V_0280A0_COLOR_11_11_10 0x00000017

1474

#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018

1475

#define V_0280A0_COLOR_2_10_10_10 0x00000019

1476

#define V_0280A0_COLOR_8_8_8_8 0x0000001A

1477

#define V_0280A0_COLOR_10_10_10_2 0x0000001B

1478

#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C

1479

#define V_0280A0_COLOR_32_32 0x0000001D

1480

#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E

1481

#define V_0280A0_COLOR_16_16_16_16 0x0000001F

1482

#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020

1483

#define V_0280A0_COLOR_32_32_32_32 0x00000022

1484

#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023

1485

#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)

1486

#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)

1487

#define C_0280A0_ARRAY_MODE 0xFFFFF0FF

1488

#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000

1489

#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001

1490

#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002

1491

#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004

1492

#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)

1493

#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)

1494

#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF

1495

#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)

1496

#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)

1497

#define C_0280A0_READ_SIZE 0xFFFF7FFF

1498

#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)

1499

#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)

1500

#define C_0280A0_COMP_SWAP 0xFFFCFFFF

1501

#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)

1502

#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)

1503

#define C_0280A0_TILE_MODE 0xFFF3FFFF

Marek Olšák

c116cc9

2012-08-19 02:22:09 +0200

[diff] [blame]

1504

#define V_0280A0_TILE_DISABLE 0

1505

#define V_0280A0_CLEAR_ENABLE 1

1506

#define V_0280A0_FRAG_ENABLE 2

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1507

#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)

1508

#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)

1509

#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF

1510

#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)

1511

#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)

1512

#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF

1513

#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)

1514

#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)

1515

#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF

1516

#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)

1517

#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)

1518

#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF

1519

#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)

1520

#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)

1521

#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF

1522

#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)

1523

#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)

1524

#define C_0280A0_ROUND_MODE 0xFDFFFFFF

1525

#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)

1526

#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1527

#define C_0280A0_TILE_COMPACT 0xFBFFFFFF

1528

#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)

1529

#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)

1530

#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF

1531

#define R_0280A4_CB_COLOR1_INFO 0x0280A4

1532

#define R_0280A8_CB_COLOR2_INFO 0x0280A8

1533

#define R_0280AC_CB_COLOR3_INFO 0x0280AC

1534

#define R_0280B0_CB_COLOR4_INFO 0x0280B0

1535

#define R_0280B4_CB_COLOR5_INFO 0x0280B4

1536

#define R_0280B8_CB_COLOR6_INFO 0x0280B8

1537

#define R_0280BC_CB_COLOR7_INFO 0x0280BC

1538

#define R_028060_CB_COLOR0_SIZE 0x028060

1539

#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1540

#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1541

#define C_028060_PITCH_TILE_MAX 0xFFFFFC00

1542

#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1543

#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1544

#define C_028060_SLICE_TILE_MAX 0xC00003FF

1545

#define R_028064_CB_COLOR1_SIZE 0x028064

1546

#define R_028068_CB_COLOR2_SIZE 0x028068

1547

#define R_02806C_CB_COLOR3_SIZE 0x02806C

1548

#define R_028070_CB_COLOR4_SIZE 0x028070

1549

#define R_028074_CB_COLOR5_SIZE 0x028074

1550

#define R_028078_CB_COLOR6_SIZE 0x028078

1551

#define R_02807C_CB_COLOR7_SIZE 0x02807C

1552

#define R_028238_CB_TARGET_MASK 0x028238

1553

#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)

1554

#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)

1555

#define C_028238_TARGET0_ENABLE 0xFFFFFFF0

1556

#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)

1557

#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)

1558

#define C_028238_TARGET1_ENABLE 0xFFFFFF0F

1559

#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)

1560

#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)

1561

#define C_028238_TARGET2_ENABLE 0xFFFFF0FF

1562

#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)

1563

#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)

1564

#define C_028238_TARGET3_ENABLE 0xFFFF0FFF

1565

#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)

1566

#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)

1567

#define C_028238_TARGET4_ENABLE 0xFFF0FFFF

1568

#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)

1569

#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)

1570

#define C_028238_TARGET5_ENABLE 0xFF0FFFFF

1571

#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)

1572

#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)

1573

#define C_028238_TARGET6_ENABLE 0xF0FFFFFF

1574

#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)

1575

#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)

1576

#define C_028238_TARGET7_ENABLE 0x0FFFFFFF

1577

#define R_02823C_CB_SHADER_MASK 0x02823C

1578

#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)

1579

#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)

1580

#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0

1581

#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)

1582

#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)

1583

#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F

1584

#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)

1585

#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)

1586

#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF

1587

#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)

1588

#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)

1589

#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF

1590

#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)

1591

#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)

1592

#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF

1593

#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)

1594

#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)

1595

#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF

1596

#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)

1597

#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)

1598

#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF

1599

#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)

1600

#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)

1601

#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF

1602

#define R_028AB0_VGT_STRMOUT_EN 0x028AB0

1603

#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)

1604

#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)

1605

#define C_028AB0_STREAMOUT 0xFFFFFFFE

1606

#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20

1607

#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)

1608

#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)

1609

#define C_028B20_BUFFER_0_EN 0xFFFFFFFE

1610

#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)

1611

#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)

1612

#define C_028B20_BUFFER_1_EN 0xFFFFFFFD

1613

#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)

1614

#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)

1615

#define C_028B20_BUFFER_2_EN 0xFFFFFFFB

1616

#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)

1617

#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)

1618

#define C_028B20_BUFFER_3_EN 0xFFFFFFF7

1619

#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1620

#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1621

#define C_028B20_SIZE 0x00000000

1622

#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000

1623

#define S_038000_DIM(x) (((x) & 0x7) << 0)

1624

#define G_038000_DIM(x) (((x) >> 0) & 0x7)

1625

#define C_038000_DIM 0xFFFFFFF8

1626

#define V_038000_SQ_TEX_DIM_1D 0x00000000

1627

#define V_038000_SQ_TEX_DIM_2D 0x00000001

1628

#define V_038000_SQ_TEX_DIM_3D 0x00000002

1629

#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003

1630

#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004

1631

#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005

1632

#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006

1633

#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007

1634

#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)

1635

#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)

1636

#define C_038000_TILE_MODE 0xFFFFFF87

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1637

#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000

1638

#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001

1639

#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002

1640

#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1641

#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)

1642

#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)

1643

#define C_038000_TILE_TYPE 0xFFFFFF7F

1644

#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)

1645

#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)

1646

#define C_038000_PITCH 0xFFF800FF

1647

#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)

1648

#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)

1649

#define C_038000_TEX_WIDTH 0x0007FFFF

1650

#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004

1651

#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)

1652

#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)

1653

#define C_038004_TEX_HEIGHT 0xFFFFE000

1654

#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)

1655

#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)

1656

#define C_038004_TEX_DEPTH 0xFC001FFF

1657

#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)

1658

#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)

1659

#define C_038004_DATA_FORMAT 0x03FFFFFF

1660

#define V_038004_COLOR_INVALID 0x00000000

1661

#define V_038004_COLOR_8 0x00000001

1662

#define V_038004_COLOR_4_4 0x00000002

1663

#define V_038004_COLOR_3_3_2 0x00000003

1664

#define V_038004_COLOR_16 0x00000005

1665

#define V_038004_COLOR_16_FLOAT 0x00000006

1666

#define V_038004_COLOR_8_8 0x00000007

1667

#define V_038004_COLOR_5_6_5 0x00000008

1668

#define V_038004_COLOR_6_5_5 0x00000009

1669

#define V_038004_COLOR_1_5_5_5 0x0000000A

1670

#define V_038004_COLOR_4_4_4_4 0x0000000B

1671

#define V_038004_COLOR_5_5_5_1 0x0000000C

1672

#define V_038004_COLOR_32 0x0000000D

1673

#define V_038004_COLOR_32_FLOAT 0x0000000E

1674

#define V_038004_COLOR_16_16 0x0000000F

1675

#define V_038004_COLOR_16_16_FLOAT 0x00000010

1676

#define V_038004_COLOR_8_24 0x00000011

1677

#define V_038004_COLOR_8_24_FLOAT 0x00000012

1678

#define V_038004_COLOR_24_8 0x00000013

1679

#define V_038004_COLOR_24_8_FLOAT 0x00000014

1680

#define V_038004_COLOR_10_11_11 0x00000015

1681

#define V_038004_COLOR_10_11_11_FLOAT 0x00000016

1682

#define V_038004_COLOR_11_11_10 0x00000017

1683

#define V_038004_COLOR_11_11_10_FLOAT 0x00000018

1684

#define V_038004_COLOR_2_10_10_10 0x00000019

1685

#define V_038004_COLOR_8_8_8_8 0x0000001A

1686

#define V_038004_COLOR_10_10_10_2 0x0000001B

1687

#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C

1688

#define V_038004_COLOR_32_32 0x0000001D

1689

#define V_038004_COLOR_32_32_FLOAT 0x0000001E

1690

#define V_038004_COLOR_16_16_16_16 0x0000001F

1691

#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020

1692

#define V_038004_COLOR_32_32_32_32 0x00000022

1693

#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023

1694

#define V_038004_FMT_1 0x00000025

1695

#define V_038004_FMT_GB_GR 0x00000027

1696

#define V_038004_FMT_BG_RG 0x00000028

1697

#define V_038004_FMT_32_AS_8 0x00000029

1698

#define V_038004_FMT_32_AS_8_8 0x0000002A

1699

#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B

1700

#define V_038004_FMT_8_8_8 0x0000002C

1701

#define V_038004_FMT_16_16_16 0x0000002D

1702

#define V_038004_FMT_16_16_16_FLOAT 0x0000002E

1703

#define V_038004_FMT_32_32_32 0x0000002F

1704

#define V_038004_FMT_32_32_32_FLOAT 0x00000030

Dave Airlie

60b212f

2011-02-18 05:51:58 +0000

[diff] [blame]

1705

#define V_038004_FMT_BC1 0x00000031

1706

#define V_038004_FMT_BC2 0x00000032

1707

#define V_038004_FMT_BC3 0x00000033

1708

#define V_038004_FMT_BC4 0x00000034

1709

#define V_038004_FMT_BC5 0x00000035

Marek Olšák

fe6f0bd

2011-05-07 01:09:57 +0200

[diff] [blame]

1710

#define V_038004_FMT_BC6 0x00000036

1711

#define V_038004_FMT_BC7 0x00000037

1712

#define V_038004_FMT_32_AS_32_32_32_32 0x00000038

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1713

#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010

1714

#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)

1715

#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)

1716

#define C_038010_FORMAT_COMP_X 0xFFFFFFFC

1717

#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)

1718

#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)

1719

#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3

1720

#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)

1721

#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)

1722

#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF

1723

#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)

1724

#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)

1725

#define C_038010_FORMAT_COMP_W 0xFFFFFF3F

1726

#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)

1727

#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)

1728

#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF

1729

#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)

1730

#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)

1731

#define C_038010_SRF_MODE_ALL 0xFFFFFBFF

1732

#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)

1733

#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)

1734

#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF

1735

#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)

1736

#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)

1737

#define C_038010_ENDIAN_SWAP 0xFFFFCFFF

1738

#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)

1739

#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)

1740

#define C_038010_REQUEST_SIZE 0xFFFF3FFF

1741

#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)

1742

#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)

1743

#define C_038010_DST_SEL_X 0xFFF8FFFF

1744

#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)

1745

#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)

1746

#define C_038010_DST_SEL_Y 0xFFC7FFFF

1747

#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)

1748

#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)

1749

#define C_038010_DST_SEL_Z 0xFE3FFFFF

1750

#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)

1751

#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)

1752

#define C_038010_DST_SEL_W 0xF1FFFFFF

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

# define SQ_SEL_X 0

# define SQ_SEL_Y 1

# define SQ_SEL_Z 2

# define SQ_SEL_W 3

# define SQ_SEL_0 4

# define SQ_SEL_1 5

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1759

#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)

1760

#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)

1761

#define C_038010_BASE_LEVEL 0x0FFFFFFF

1762

#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014

1763

#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)

1764

#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)

1765

#define C_038014_LAST_LEVEL 0xFFFFFFF0

1766

#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)

1767

#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)

1768

#define C_038014_BASE_ARRAY 0xFFFE000F

1769

#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)

1770

#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)

1771

#define C_038014_LAST_ARRAY 0xC001FFFF

1772

#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8

1773

#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1774

#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1775

#define C_0288A8_ITEMSIZE 0xFFFF8000

1776

#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44

1777

#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1778

#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1779

#define C_008C44_MEM_SIZE 0x00000000

1780

#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0

1781

#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1782

#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1783

#define C_0288B0_ITEMSIZE 0xFFFF8000

1784

#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54

1785

#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1786

#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1787

#define C_008C54_MEM_SIZE 0x00000000

1788

#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0

1789

#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1790

#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1791

#define C_0288C0_ITEMSIZE 0xFFFF8000

1792

#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74

1793

#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1794

#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1795

#define C_008C74_MEM_SIZE 0x00000000

1796

#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4

1797

#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1798

#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1799

#define C_0288B4_ITEMSIZE 0xFFFF8000

1800

#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C

1801

#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1802

#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1803

#define C_008C5C_MEM_SIZE 0x00000000

1804

#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC

1805

#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1806

#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1807

#define C_0288AC_ITEMSIZE 0xFFFF8000

1808

#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C

1809

#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1810

#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1811

#define C_008C4C_MEM_SIZE 0x00000000

1812

#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC

1813

#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1814

#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1815

#define C_0288BC_ITEMSIZE 0xFFFF8000

1816

#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C

1817

#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1818

#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1819

#define C_008C6C_MEM_SIZE 0x00000000

1820

#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4

1821

#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1822

#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1823

#define C_0288C4_ITEMSIZE 0xFFFF8000

1824

#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C

1825

#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1826

#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1827

#define C_008C7C_MEM_SIZE 0x00000000

1828

#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8

1829

#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1830

#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1831

#define C_0288B8_ITEMSIZE 0xFFFF8000

1832

#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64

1833

#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1834

#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1835

#define C_008C64_MEM_SIZE 0x00000000

1836

#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8

1837

#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1838

#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1839

#define C_0288C8_ITEMSIZE 0xFFFF8000

1840

#define R_028010_DB_DEPTH_INFO 0x028010

1841

#define S_028010_FORMAT(x) (((x) & 0x7) << 0)

1842

#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)

1843

#define C_028010_FORMAT 0xFFFFFFF8

1844

#define V_028010_DEPTH_INVALID 0x00000000

1845

#define V_028010_DEPTH_16 0x00000001

1846

#define V_028010_DEPTH_X8_24 0x00000002

1847

#define V_028010_DEPTH_8_24 0x00000003

1848

#define V_028010_DEPTH_X8_24_FLOAT 0x00000004

1849

#define V_028010_DEPTH_8_24_FLOAT 0x00000005

1850

#define V_028010_DEPTH_32_FLOAT 0x00000006

1851

#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007

1852

#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)

1853

#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)

1854

#define C_028010_READ_SIZE 0xFFFFFFF7

1855

#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)

1856

#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)

1857

#define C_028010_ARRAY_MODE 0xFFF87FFF

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1858

#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002

1859

#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1860

#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)

1861

#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)

1862

#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF

1863

#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)

1864

#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1865

#define C_028010_TILE_COMPACT 0xFBFFFFFF

1866

#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)

1867

#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)

1868

#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF

1869

#define R_028000_DB_DEPTH_SIZE 0x028000

1870

#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1871

#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1872

#define C_028000_PITCH_TILE_MAX 0xFFFFFC00

1873

#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1874

#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1875

#define C_028000_SLICE_TILE_MAX 0xC00003FF

1876

#define R_028004_DB_DEPTH_VIEW 0x028004

1877

#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)

1878

#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)

1879

#define C_028004_SLICE_START 0xFFFFF800

1880

#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1881

#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1882

#define C_028004_SLICE_MAX 0xFF001FFF

1883

#define R_028800_DB_DEPTH_CONTROL 0x028800

1884

#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)

1885

#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)

1886

#define C_028800_STENCIL_ENABLE 0xFFFFFFFE

1887

#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)

1888

#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)

1889

#define C_028800_Z_ENABLE 0xFFFFFFFD

1890

#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)

1891

#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)

1892

#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB

1893

#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)

1894

#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)

1895

#define C_028800_ZFUNC 0xFFFFFF8F

1896

#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)

1897

#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)

1898

#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F

1899

#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)

1900

#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)

1901

#define C_028800_STENCILFUNC 0xFFFFF8FF

1902

#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)

1903

#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)

1904

#define C_028800_STENCILFAIL 0xFFFFC7FF

1905

#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)

1906

#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)

1907

#define C_028800_STENCILZPASS 0xFFFE3FFF

1908

#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)

1909

#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)

1910

#define C_028800_STENCILZFAIL 0xFFF1FFFF

1911

#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)

1912

#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)

1913

#define C_028800_STENCILFUNC_BF 0xFF8FFFFF

1914

#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)

1915

#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)

1916

#define C_028800_STENCILFAIL_BF 0xFC7FFFFF

1917

#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)

1918

#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)

1919

#define C_028800_STENCILZPASS_BF 0xE3FFFFFF

1920

#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)

1921

#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)

1922

#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1923

Jerome Glisse