Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SH64_PGTABLE_H |
| 2 | #define __ASM_SH64_PGTABLE_H |
| 3 | |
| 4 | #include <asm-generic/4level-fixup.h> |
| 5 | |
| 6 | /* |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | * |
| 11 | * include/asm-sh64/pgtable.h |
| 12 | * |
| 13 | * Copyright (C) 2000, 2001 Paolo Alberelli |
| 14 | * Copyright (C) 2003, 2004 Paul Mundt |
| 15 | * Copyright (C) 2003, 2004 Richard Curnow |
| 16 | * |
| 17 | * This file contains the functions and defines necessary to modify and use |
| 18 | * the SuperH page table tree. |
| 19 | */ |
| 20 | |
| 21 | #ifndef __ASSEMBLY__ |
| 22 | #include <asm/processor.h> |
| 23 | #include <asm/page.h> |
| 24 | #include <linux/threads.h> |
| 25 | #include <linux/config.h> |
| 26 | |
Tim Schmielau | 8c65b4a | 2005-11-07 00:59:43 -0800 | [diff] [blame] | 27 | struct vm_area_struct; |
| 28 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | extern void paging_init(void); |
| 30 | |
| 31 | /* We provide our own get_unmapped_area to avoid cache synonym issue */ |
| 32 | #define HAVE_ARCH_UNMAPPED_AREA |
| 33 | |
| 34 | /* |
| 35 | * Basically we have the same two-level (which is the logical three level |
| 36 | * Linux page table layout folded) page tables as the i386. |
| 37 | */ |
| 38 | |
| 39 | /* |
| 40 | * ZERO_PAGE is a global shared page that is always zero: used |
| 41 | * for zero-mapped memory areas etc.. |
| 42 | */ |
| 43 | extern unsigned char empty_zero_page[PAGE_SIZE]; |
| 44 | #define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page)) |
| 45 | |
| 46 | #endif /* !__ASSEMBLY__ */ |
| 47 | |
| 48 | /* |
| 49 | * NEFF and NPHYS related defines. |
| 50 | * FIXME : These need to be model-dependent. For now this is OK, SH5-101 and SH5-103 |
| 51 | * implement 32 bits effective and 32 bits physical. But future implementations may |
| 52 | * extend beyond this. |
| 53 | */ |
| 54 | #define NEFF 32 |
| 55 | #define NEFF_SIGN (1LL << (NEFF - 1)) |
| 56 | #define NEFF_MASK (-1LL << NEFF) |
| 57 | |
| 58 | #define NPHYS 32 |
| 59 | #define NPHYS_SIGN (1LL << (NPHYS - 1)) |
| 60 | #define NPHYS_MASK (-1LL << NPHYS) |
| 61 | |
| 62 | /* Typically 2-level is sufficient up to 32 bits of virtual address space, beyond |
| 63 | that 3-level would be appropriate. */ |
| 64 | #if defined(CONFIG_SH64_PGTABLE_2_LEVEL) |
| 65 | /* For 4k pages, this contains 512 entries, i.e. 9 bits worth of address. */ |
| 66 | #define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long)) |
| 67 | #define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */ |
| 68 | #define PTE_SHIFT PAGE_SHIFT |
| 69 | #define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE) |
| 70 | |
| 71 | /* top level: PMD. */ |
| 72 | #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) |
| 73 | #define PGD_BITS (NEFF - PGDIR_SHIFT) |
| 74 | #define PTRS_PER_PGD (1<<PGD_BITS) |
| 75 | |
| 76 | /* middle level: PMD. This doesn't do anything for the 2-level case. */ |
| 77 | #define PTRS_PER_PMD (1) |
| 78 | |
| 79 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
| 80 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
| 81 | #define PMD_SHIFT PGDIR_SHIFT |
| 82 | #define PMD_SIZE PGDIR_SIZE |
| 83 | #define PMD_MASK PGDIR_MASK |
| 84 | |
| 85 | #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL) |
| 86 | /* |
| 87 | * three-level asymmetric paging structure: PGD is top level. |
| 88 | * The asymmetry comes from 32-bit pointers and 64-bit PTEs. |
| 89 | */ |
| 90 | /* bottom level: PTE. It's 9 bits = 512 pointers */ |
| 91 | #define PTRS_PER_PTE ((1<<PAGE_SHIFT)/sizeof(unsigned long long)) |
| 92 | #define PTE_MAGNITUDE 3 /* sizeof(unsigned long long) magnit. */ |
| 93 | #define PTE_SHIFT PAGE_SHIFT |
| 94 | #define PTE_BITS (PAGE_SHIFT - PTE_MAGNITUDE) |
| 95 | |
| 96 | /* middle level: PMD. It's 10 bits = 1024 pointers */ |
| 97 | #define PTRS_PER_PMD ((1<<PAGE_SHIFT)/sizeof(unsigned long long *)) |
| 98 | #define PMD_MAGNITUDE 2 /* sizeof(unsigned long long *) magnit. */ |
| 99 | #define PMD_SHIFT (PTE_SHIFT + PTE_BITS) |
| 100 | #define PMD_BITS (PAGE_SHIFT - PMD_MAGNITUDE) |
| 101 | |
| 102 | /* top level: PMD. It's 1 bit = 2 pointers */ |
| 103 | #define PGDIR_SHIFT (PMD_SHIFT + PMD_BITS) |
| 104 | #define PGD_BITS (NEFF - PGDIR_SHIFT) |
| 105 | #define PTRS_PER_PGD (1<<PGD_BITS) |
| 106 | |
| 107 | #define PMD_SIZE (1UL << PMD_SHIFT) |
| 108 | #define PMD_MASK (~(PMD_SIZE-1)) |
| 109 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
| 110 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
| 111 | |
| 112 | #else |
| 113 | #error "No defined number of page table levels" |
| 114 | #endif |
| 115 | |
| 116 | /* |
| 117 | * Error outputs. |
| 118 | */ |
| 119 | #define pte_ERROR(e) \ |
| 120 | printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) |
| 121 | #define pmd_ERROR(e) \ |
| 122 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) |
| 123 | #define pgd_ERROR(e) \ |
| 124 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) |
| 125 | |
| 126 | /* |
| 127 | * Table setting routines. Used within arch/mm only. |
| 128 | */ |
| 129 | #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) |
| 130 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) |
| 131 | |
| 132 | static __inline__ void set_pte(pte_t *pteptr, pte_t pteval) |
| 133 | { |
| 134 | unsigned long long x = ((unsigned long long) pteval.pte); |
| 135 | unsigned long long *xp = (unsigned long long *) pteptr; |
| 136 | /* |
| 137 | * Sign-extend based on NPHYS. |
| 138 | */ |
| 139 | *(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x; |
| 140 | } |
| 141 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) |
| 142 | |
| 143 | static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep) |
| 144 | { |
| 145 | pmd_val(*pmdp) = (unsigned long) ptep; |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * PGD defines. Top level. |
| 150 | */ |
| 151 | |
| 152 | /* To find an entry in a generic PGD. */ |
| 153 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
| 154 | #define __pgd_offset(address) pgd_index(address) |
| 155 | #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) |
| 156 | |
| 157 | /* To find an entry in a kernel PGD. */ |
| 158 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
| 159 | |
| 160 | /* |
| 161 | * PGD level access routines. |
| 162 | * |
| 163 | * Note1: |
| 164 | * There's no need to use physical addresses since the tree walk is all |
| 165 | * in performed in software, until the PTE translation. |
| 166 | * |
| 167 | * Note 2: |
| 168 | * A PGD entry can be uninitialized (_PGD_UNUSED), generically bad, |
| 169 | * clear (_PGD_EMPTY), present. When present, lower 3 nibbles contain |
| 170 | * _KERNPG_TABLE. Being a kernel virtual pointer also bit 31 must |
| 171 | * be 1. Assuming an arbitrary clear value of bit 31 set to 0 and |
| 172 | * lower 3 nibbles set to 0xFFF (_PGD_EMPTY) any other value is a |
| 173 | * bad pgd that must be notified via printk(). |
| 174 | * |
| 175 | */ |
| 176 | #define _PGD_EMPTY 0x0 |
| 177 | |
| 178 | #if defined(CONFIG_SH64_PGTABLE_2_LEVEL) |
| 179 | static inline int pgd_none(pgd_t pgd) { return 0; } |
| 180 | static inline int pgd_bad(pgd_t pgd) { return 0; } |
| 181 | #define pgd_present(pgd) ((pgd_val(pgd) & _PAGE_PRESENT) ? 1 : 0) |
| 182 | #define pgd_clear(xx) do { } while(0) |
| 183 | |
| 184 | #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL) |
| 185 | #define pgd_present(pgd_entry) (1) |
| 186 | #define pgd_none(pgd_entry) (pgd_val((pgd_entry)) == _PGD_EMPTY) |
| 187 | /* TODO: Think later about what a useful definition of 'bad' would be now. */ |
| 188 | #define pgd_bad(pgd_entry) (0) |
| 189 | #define pgd_clear(pgd_entry_p) (set_pgd((pgd_entry_p), __pgd(_PGD_EMPTY))) |
| 190 | |
| 191 | #endif |
| 192 | |
| 193 | |
| 194 | #define pgd_page(pgd_entry) ((unsigned long) (pgd_val(pgd_entry) & PAGE_MASK)) |
| 195 | |
| 196 | /* |
| 197 | * PMD defines. Middle level. |
| 198 | */ |
| 199 | |
| 200 | /* PGD to PMD dereferencing */ |
| 201 | #if defined(CONFIG_SH64_PGTABLE_2_LEVEL) |
| 202 | static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) |
| 203 | { |
| 204 | return (pmd_t *) dir; |
| 205 | } |
| 206 | #elif defined(CONFIG_SH64_PGTABLE_3_LEVEL) |
| 207 | #define __pmd_offset(address) \ |
| 208 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) |
| 209 | #define pmd_offset(dir, addr) \ |
| 210 | ((pmd_t *) ((pgd_val(*(dir))) & PAGE_MASK) + __pmd_offset((addr))) |
| 211 | #endif |
| 212 | |
| 213 | /* |
| 214 | * PMD level access routines. Same notes as above. |
| 215 | */ |
| 216 | #define _PMD_EMPTY 0x0 |
| 217 | /* Either the PMD is empty or present, it's not paged out */ |
| 218 | #define pmd_present(pmd_entry) (pmd_val(pmd_entry) & _PAGE_PRESENT) |
| 219 | #define pmd_clear(pmd_entry_p) (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY))) |
| 220 | #define pmd_none(pmd_entry) (pmd_val((pmd_entry)) == _PMD_EMPTY) |
| 221 | #define pmd_bad(pmd_entry) ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE) |
| 222 | |
| 223 | #define pmd_page_kernel(pmd_entry) \ |
| 224 | ((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK)) |
| 225 | |
| 226 | #define pmd_page(pmd) \ |
| 227 | (virt_to_page(pmd_val(pmd))) |
| 228 | |
| 229 | /* PMD to PTE dereferencing */ |
| 230 | #define pte_index(address) \ |
| 231 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |
| 232 | |
| 233 | #define pte_offset_kernel(dir, addr) \ |
| 234 | ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr))) |
| 235 | |
| 236 | #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr) |
| 237 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr) |
| 238 | #define pte_unmap(pte) do { } while (0) |
| 239 | #define pte_unmap_nested(pte) do { } while (0) |
| 240 | |
| 241 | /* Round it up ! */ |
| 242 | #define USER_PTRS_PER_PGD ((TASK_SIZE+PGDIR_SIZE-1)/PGDIR_SIZE) |
Hugh Dickins | d455a36 | 2005-04-19 13:29:23 -0700 | [diff] [blame] | 243 | #define FIRST_USER_ADDRESS 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | |
| 245 | #ifndef __ASSEMBLY__ |
| 246 | #define VMALLOC_END 0xff000000 |
| 247 | #define VMALLOC_START 0xf0000000 |
| 248 | #define VMALLOC_VMADDR(x) ((unsigned long)(x)) |
| 249 | |
| 250 | #define IOBASE_VADDR 0xff000000 |
| 251 | #define IOBASE_END 0xffffffff |
| 252 | |
| 253 | /* |
| 254 | * PTEL coherent flags. |
| 255 | * See Chapter 17 ST50 CPU Core Volume 1, Architecture. |
| 256 | */ |
| 257 | /* The bits that are required in the SH-5 TLB are placed in the h/w-defined |
| 258 | positions, to avoid expensive bit shuffling on every refill. The remaining |
| 259 | bits are used for s/w purposes and masked out on each refill. |
| 260 | |
| 261 | Note, the PTE slots are used to hold data of type swp_entry_t when a page is |
| 262 | swapped out. Only the _PAGE_PRESENT flag is significant when the page is |
| 263 | swapped out, and it must be placed so that it doesn't overlap either the |
| 264 | type or offset fields of swp_entry_t. For x86, offset is at [31:8] and type |
| 265 | at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t. This |
| 266 | scheme doesn't map to SH-5 because bit [0] controls cacheability. So bit |
| 267 | [2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split |
| 268 | into 2 pieces. That is handled by SWP_ENTRY and SWP_TYPE below. */ |
| 269 | #define _PAGE_WT 0x001 /* CB0: if cacheable, 1->write-thru, 0->write-back */ |
| 270 | #define _PAGE_DEVICE 0x001 /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */ |
| 271 | #define _PAGE_CACHABLE 0x002 /* CB1: uncachable/cachable */ |
| 272 | #define _PAGE_PRESENT 0x004 /* software: page referenced */ |
| 273 | #define _PAGE_FILE 0x004 /* software: only when !present */ |
| 274 | #define _PAGE_SIZE0 0x008 /* SZ0-bit : size of page */ |
| 275 | #define _PAGE_SIZE1 0x010 /* SZ1-bit : size of page */ |
| 276 | #define _PAGE_SHARED 0x020 /* software: reflects PTEH's SH */ |
| 277 | #define _PAGE_READ 0x040 /* PR0-bit : read access allowed */ |
| 278 | #define _PAGE_EXECUTE 0x080 /* PR1-bit : execute access allowed */ |
| 279 | #define _PAGE_WRITE 0x100 /* PR2-bit : write access allowed */ |
| 280 | #define _PAGE_USER 0x200 /* PR3-bit : user space access allowed */ |
| 281 | #define _PAGE_DIRTY 0x400 /* software: page accessed in write */ |
| 282 | #define _PAGE_ACCESSED 0x800 /* software: page referenced */ |
| 283 | |
| 284 | /* Mask which drops software flags */ |
| 285 | #define _PAGE_FLAGS_HARDWARE_MASK 0xfffffffffffff3dbLL |
| 286 | |
| 287 | /* |
| 288 | * HugeTLB support |
| 289 | */ |
| 290 | #if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) |
| 291 | #define _PAGE_SZHUGE (_PAGE_SIZE0) |
| 292 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) |
| 293 | #define _PAGE_SZHUGE (_PAGE_SIZE1) |
| 294 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB) |
| 295 | #define _PAGE_SZHUGE (_PAGE_SIZE0 | _PAGE_SIZE1) |
| 296 | #endif |
| 297 | |
| 298 | /* |
| 299 | * Default flags for a Kernel page. |
| 300 | * This is fundametally also SHARED because the main use of this define |
| 301 | * (other than for PGD/PMD entries) is for the VMALLOC pool which is |
| 302 | * contextless. |
| 303 | * |
| 304 | * _PAGE_EXECUTE is required for modules |
| 305 | * |
| 306 | */ |
| 307 | #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
| 308 | _PAGE_EXECUTE | \ |
| 309 | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \ |
| 310 | _PAGE_SHARED) |
| 311 | |
| 312 | /* Default flags for a User page */ |
| 313 | #define _PAGE_TABLE (_KERNPG_TABLE | _PAGE_USER) |
| 314 | |
| 315 | #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) |
| 316 | |
| 317 | #define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED) |
| 318 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
| 319 | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_USER | \ |
| 320 | _PAGE_SHARED) |
| 321 | /* We need to include PAGE_EXECUTE in PAGE_COPY because it is the default |
| 322 | * protection mode for the stack. */ |
| 323 | #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \ |
| 324 | _PAGE_ACCESSED | _PAGE_USER | _PAGE_EXECUTE) |
| 325 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHABLE | \ |
| 326 | _PAGE_ACCESSED | _PAGE_USER) |
| 327 | #define PAGE_KERNEL __pgprot(_KERNPG_TABLE) |
| 328 | |
| 329 | |
| 330 | /* |
| 331 | * In ST50 we have full permissions (Read/Write/Execute/Shared). |
| 332 | * Just match'em all. These are for mmap(), therefore all at least |
| 333 | * User/Cachable/Present/Accessed. No point in making Fault on Write. |
| 334 | */ |
| 335 | #define __MMAP_COMMON (_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED) |
| 336 | /* sxwr */ |
| 337 | #define __P000 __pgprot(__MMAP_COMMON) |
| 338 | #define __P001 __pgprot(__MMAP_COMMON | _PAGE_READ) |
| 339 | #define __P010 __pgprot(__MMAP_COMMON) |
| 340 | #define __P011 __pgprot(__MMAP_COMMON | _PAGE_READ) |
| 341 | #define __P100 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE) |
| 342 | #define __P101 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ) |
| 343 | #define __P110 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE) |
| 344 | #define __P111 __pgprot(__MMAP_COMMON | _PAGE_EXECUTE | _PAGE_READ) |
| 345 | |
| 346 | #define __S000 __pgprot(__MMAP_COMMON | _PAGE_SHARED) |
| 347 | #define __S001 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ) |
| 348 | #define __S010 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_WRITE) |
| 349 | #define __S011 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_READ | _PAGE_WRITE) |
| 350 | #define __S100 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE) |
| 351 | #define __S101 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ) |
| 352 | #define __S110 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_WRITE) |
| 353 | #define __S111 __pgprot(__MMAP_COMMON | _PAGE_SHARED | _PAGE_EXECUTE | _PAGE_READ | _PAGE_WRITE) |
| 354 | |
| 355 | /* Make it a device mapping for maximum safety (e.g. for mapping device |
| 356 | registers into user-space via /dev/map). */ |
| 357 | #define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE) |
| 358 | #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) |
| 359 | |
| 360 | /* |
| 361 | * Handling allocation failures during page table setup. |
| 362 | */ |
| 363 | extern void __handle_bad_pmd_kernel(pmd_t * pmd); |
| 364 | #define __handle_bad_pmd(x) __handle_bad_pmd_kernel(x) |
| 365 | |
| 366 | /* |
| 367 | * PTE level access routines. |
| 368 | * |
| 369 | * Note1: |
| 370 | * It's the tree walk leaf. This is physical address to be stored. |
| 371 | * |
| 372 | * Note 2: |
| 373 | * Regarding the choice of _PTE_EMPTY: |
| 374 | |
| 375 | We must choose a bit pattern that cannot be valid, whether or not the page |
| 376 | is present. bit[2]==1 => present, bit[2]==0 => swapped out. If swapped |
| 377 | out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is |
| 378 | left for us to select. If we force bit[7]==0 when swapped out, we could use |
| 379 | the combination bit[7,2]=2'b10 to indicate an empty PTE. Alternatively, if |
| 380 | we force bit[7]==1 when swapped out, we can use all zeroes to indicate |
| 381 | empty. This is convenient, because the page tables get cleared to zero |
| 382 | when they are allocated. |
| 383 | |
| 384 | */ |
| 385 | #define _PTE_EMPTY 0x0 |
| 386 | #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) |
| 387 | #define pte_clear(mm,addr,xp) (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY))) |
| 388 | #define pte_none(x) (pte_val(x) == _PTE_EMPTY) |
| 389 | |
| 390 | /* |
| 391 | * Some definitions to translate between mem_map, PTEs, and page |
| 392 | * addresses: |
| 393 | */ |
| 394 | |
| 395 | /* |
| 396 | * Given a PTE, return the index of the mem_map[] entry corresponding |
| 397 | * to the page frame the PTE. Get the absolute physical address, make |
| 398 | * a relative physical address and translate it to an index. |
| 399 | */ |
| 400 | #define pte_pagenr(x) (((unsigned long) (pte_val(x)) - \ |
| 401 | __MEMORY_START) >> PAGE_SHIFT) |
| 402 | |
| 403 | /* |
| 404 | * Given a PTE, return the "struct page *". |
| 405 | */ |
| 406 | #define pte_page(x) (mem_map + pte_pagenr(x)) |
| 407 | |
| 408 | /* |
| 409 | * Return number of (down rounded) MB corresponding to x pages. |
| 410 | */ |
| 411 | #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) |
| 412 | |
| 413 | |
| 414 | /* |
| 415 | * The following have defined behavior only work if pte_present() is true. |
| 416 | */ |
| 417 | static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } |
| 418 | static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXECUTE; } |
| 419 | static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; } |
| 420 | static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; } |
| 421 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } |
| 422 | static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_WRITE; } |
| 423 | |
Adrian Bunk | ca5ed2f | 2006-01-09 20:54:47 -0800 | [diff] [blame^] | 424 | static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_READ)); return pte; } |
| 425 | static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; } |
| 426 | static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_EXECUTE)); return pte; } |
| 427 | static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } |
| 428 | static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | |
Adrian Bunk | ca5ed2f | 2006-01-09 20:54:47 -0800 | [diff] [blame^] | 430 | static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_READ)); return pte; } |
| 431 | static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; } |
| 432 | static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); return pte; } |
| 433 | static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; } |
| 434 | static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; } |
| 435 | static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; } |
David Gibson | 63551ae | 2005-06-21 17:14:44 -0700 | [diff] [blame] | 436 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
| 438 | /* |
| 439 | * Conversion functions: convert a page and protection to a page entry. |
| 440 | * |
| 441 | * extern pte_t mk_pte(struct page *page, pgprot_t pgprot) |
| 442 | */ |
| 443 | #define mk_pte(page,pgprot) \ |
| 444 | ({ \ |
| 445 | pte_t __pte; \ |
| 446 | \ |
| 447 | set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) | \ |
| 448 | __MEMORY_START | pgprot_val((pgprot)))); \ |
| 449 | __pte; \ |
| 450 | }) |
| 451 | |
| 452 | /* |
| 453 | * This takes a (absolute) physical page address that is used |
| 454 | * by the remapping functions |
| 455 | */ |
| 456 | #define mk_pte_phys(physpage, pgprot) \ |
| 457 | ({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; }) |
| 458 | |
Adrian Bunk | ca5ed2f | 2006-01-09 20:54:47 -0800 | [diff] [blame^] | 459 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; } |
| 461 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | typedef pte_t *pte_addr_t; |
| 463 | #define pgtable_cache_init() do { } while (0) |
| 464 | |
| 465 | extern void update_mmu_cache(struct vm_area_struct * vma, |
| 466 | unsigned long address, pte_t pte); |
| 467 | |
| 468 | /* Encode and decode a swap entry */ |
| 469 | #define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c)) |
| 470 | #define __swp_offset(x) ((x).val >> 8) |
| 471 | #define __swp_entry(type, offset) ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) }) |
| 472 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
| 473 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) |
| 474 | |
| 475 | /* Encode and decode a nonlinear file mapping entry */ |
| 476 | #define PTE_FILE_MAX_BITS 29 |
| 477 | #define pte_to_pgoff(pte) (pte_val(pte)) |
| 478 | #define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE }) |
| 479 | |
| 480 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ |
| 481 | #define PageSkip(page) (0) |
| 482 | #define kern_addr_valid(addr) (1) |
| 483 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ |
| 485 | remap_pfn_range(vma, vaddr, pfn, size, prot) |
| 486 | |
| 487 | #define MK_IOSPACE_PFN(space, pfn) (pfn) |
| 488 | #define GET_IOSPACE(pfn) 0 |
| 489 | #define GET_PFN(pfn) (pfn) |
| 490 | |
| 491 | #endif /* !__ASSEMBLY__ */ |
| 492 | |
| 493 | /* |
| 494 | * No page table caches to initialise |
| 495 | */ |
| 496 | #define pgtable_cache_init() do { } while (0) |
| 497 | |
| 498 | #define pte_pfn(x) (((unsigned long)((x).pte)) >> PAGE_SHIFT) |
| 499 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) |
| 500 | #define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) |
| 501 | |
| 502 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
| 503 | |
| 504 | #include <asm-generic/pgtable.h> |
| 505 | |
| 506 | #endif /* __ASM_SH64_PGTABLE_H */ |