Blame - arch/mips/sibyte/Kconfig - kernel/msm-4.9

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Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	1	config SIBYTE_SB1250
				2	bool
				3	select HW_HAS_PCI
				4	select SIBYTE_HAS_LDT
				5	select SIBYTE_SB1xxx_SOC
Ralf Baechle	e73ea27	2006-06-04 11:51:46 +0100	[diff] [blame]	6	select SYS_SUPPORTS_SMP
Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	7
				8	config SIBYTE_BCM1120
				9	bool
				10	select SIBYTE_BCM112X
				11	select SIBYTE_SB1xxx_SOC
				12
				13	config SIBYTE_BCM1125
				14	bool
				15	select HW_HAS_PCI
				16	select SIBYTE_BCM112X
				17	select SIBYTE_SB1xxx_SOC
				18
				19	config SIBYTE_BCM1125H
				20	bool
				21	select HW_HAS_PCI
				22	select SIBYTE_BCM112X
				23	select SIBYTE_HAS_LDT
				24	select SIBYTE_SB1xxx_SOC
				25
				26	config SIBYTE_BCM112X
				27	bool
				28	select SIBYTE_SB1xxx_SOC
				29
Andrew Isaacson	f137e46	2005-10-19 23:56:38 -0700	[diff] [blame]	30	config SIBYTE_BCM1x80
				31	bool
				32	select HW_HAS_PCI
				33	select SIBYTE_SB1xxx_SOC
Ralf Baechle	e73ea27	2006-06-04 11:51:46 +0100	[diff] [blame]	34	select SYS_SUPPORTS_SMP
Andrew Isaacson	f137e46	2005-10-19 23:56:38 -0700	[diff] [blame]	35
				36	config SIBYTE_BCM1x55
				37	bool
				38	select HW_HAS_PCI
				39	select SIBYTE_SB1xxx_SOC
Ralf Baechle	e73ea27	2006-06-04 11:51:46 +0100	[diff] [blame]	40	select SYS_SUPPORTS_SMP
Andrew Isaacson	f137e46	2005-10-19 23:56:38 -0700	[diff] [blame]	41
Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	42	config SIBYTE_SB1xxx_SOC
				43	bool
				44	depends on EXPERIMENTAL
				45	select DMA_COHERENT
				46	select SIBYTE_CFE
				47	select SWAP_IO_SPACE
				48	select SYS_SUPPORTS_32BIT_KERNEL
				49	select SYS_SUPPORTS_64BIT_KERNEL
				50
				51	choice
				52	prompt "SiByte SOC Stepping"
				53	depends on SIBYTE_SB1xxx_SOC
				54
				55	config CPU_SB1_PASS_1
				56	bool "1250 Pass1"
				57	depends on SIBYTE_SB1250
				58	select CPU_HAS_PREFETCH
				59
				60	config CPU_SB1_PASS_2_1250
				61	bool "1250 An"
				62	depends on SIBYTE_SB1250
				63	select CPU_SB1_PASS_2
				64	help
				65	Also called BCM1250 Pass 2
				66
				67	config CPU_SB1_PASS_2_2
				68	bool "1250 Bn"
				69	depends on SIBYTE_SB1250
				70	select CPU_HAS_PREFETCH
				71	help
				72	Also called BCM1250 Pass 2.2
				73
				74	config CPU_SB1_PASS_4
				75	bool "1250 Cn"
				76	depends on SIBYTE_SB1250
				77	select CPU_HAS_PREFETCH
				78	help
				79	Also called BCM1250 Pass 3
				80
				81	config CPU_SB1_PASS_2_112x
				82	bool "112x Hybrid"
				83	depends on SIBYTE_BCM112X
				84	select CPU_SB1_PASS_2
				85
				86	config CPU_SB1_PASS_3
				87	bool "112x An"
				88	depends on SIBYTE_BCM112X
				89	select CPU_HAS_PREFETCH
				90
				91	endchoice
				92
				93	config CPU_SB1_PASS_2
				94	bool
				95
				96	config SIBYTE_HAS_LDT
				97	bool
				98	depends on PCI && (SIBYTE_SB1250 \|\| SIBYTE_BCM1125H)
				99	default y
				100
				101	config SIMULATION
				102	bool "Running under simulation"
				103	depends on SIBYTE_SB1xxx_SOC
				104	help
				105	Build a kernel suitable for running under the GDB simulator.
				106	Primarily adjusts the kernel's notion of time.
				107
Ralf Baechle	7760763	2005-11-10 16:32:14 +0000	[diff] [blame]	108	config SB1_CEX_ALWAYS_FATAL
Andrew Isaacson	a4b5bd9	2005-10-19 23:57:40 -0700	[diff] [blame]	109	bool "All cache exceptions considered fatal (no recovery attempted)"
				110	depends on SIBYTE_SB1xxx_SOC
				111
Ralf Baechle	7760763	2005-11-10 16:32:14 +0000	[diff] [blame]	112	config SB1_CERR_STALL
Andrew Isaacson	a4b5bd9	2005-10-19 23:57:40 -0700	[diff] [blame]	113	bool "Stall (rather than panic) on fatal cache error"
				114	depends on SIBYTE_SB1xxx_SOC
				115
Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	116	config SIBYTE_CFE
				117	bool "Booting from CFE"
				118	depends on SIBYTE_SB1xxx_SOC
Ralf Baechle	36a8853	2007-03-01 11:56:43 +0000	[diff] [blame]	119	select SYS_HAS_EARLY_PRINTK
Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	120	help
				121	Make use of the CFE API for enumerating available memory,
				122	controlling secondary CPUs, and possibly console output.
				123
				124	config SIBYTE_CFE_CONSOLE
				125	bool "Use firmware console"
				126	depends on SIBYTE_CFE
				127	help
				128	Use the CFE API's console write routines during boot. Other console
				129	options (VT console, sb1250 duart console, etc.) should not be
				130	configured.
				131
				132	config SIBYTE_STANDALONE
				133	bool
				134	depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
Ralf Baechle	36a8853	2007-03-01 11:56:43 +0000	[diff] [blame]	135	select SYS_HAS_EARLY_PRINTK
Ralf Baechle	38b18f72	2005-02-03 14:28:23 +0000	[diff] [blame]	136	default y
				137
				138	config SIBYTE_STANDALONE_RAM_SIZE
				139	int "Memory size (in megabytes)"
				140	depends on SIBYTE_STANDALONE
				141	default "32"
				142
				143	config SIBYTE_BUS_WATCHER
				144	bool "Support for Bus Watcher statistics"
				145	depends on SIBYTE_SB1xxx_SOC
				146	help
				147	Handle and keep statistics on the bus error interrupts (COR_ECC,
				148	BAD_ECC, IO_BUS).
				149
				150	config SIBYTE_BW_TRACE
				151	bool "Capture bus trace before bus error"
				152	depends on SIBYTE_BUS_WATCHER
				153	help
				154	Run a continuous bus trace, dumping the raw data as soon as
				155	a ZBbus error is detected. Cannot work if ZBbus profiling
				156	is turned on, and also will interfere with JTAG-based trace
				157	buffer activity. Raw buffer data is dumped to console, and
				158	must be processed off-line.
				159
				160	config SIBYTE_SB1250_PROF
				161	bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
				162	depends on SIBYTE_SB1xxx_SOC
				163
				164	config SIBYTE_TBPROF
				165	bool "Support for ZBbus profiling"
				166	depends on SIBYTE_SB1xxx_SOC