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gerrit-public.fairphone.software / kernel / msm-4.9 / f137e463b50aadba91bd116f99c59ccb9c15a12f / . / arch / mips / sibyte / Kconfig
blob: 6a5a08f5e212701c8aec453c1760c582b1b642f8 [file] [log] [blame]
Ralf Baechle38b18f722005-02-03 14:28:23 +0000[diff] [blame]1config SIBYTE_SB1250
2 bool
3 select HW_HAS_PCI
4 select SIBYTE_HAS_LDT
5 select SIBYTE_SB1xxx_SOC
6
7config SIBYTE_BCM1120
8 bool
9 select SIBYTE_BCM112X
10 select SIBYTE_SB1xxx_SOC
11
12config SIBYTE_BCM1125
13 bool
14 select HW_HAS_PCI
15 select SIBYTE_BCM112X
16 select SIBYTE_SB1xxx_SOC
17
18config SIBYTE_BCM1125H
19 bool
20 select HW_HAS_PCI
21 select SIBYTE_BCM112X
22 select SIBYTE_HAS_LDT
23 select SIBYTE_SB1xxx_SOC
24
25config SIBYTE_BCM112X
26 bool
27 select SIBYTE_SB1xxx_SOC
28
Andrew Isaacsonf137e462005-10-19 23:56:38 -0700[diff] [blame^]29config SIBYTE_BCM1x80
30 bool
31 select HW_HAS_PCI
32 select SIBYTE_SB1xxx_SOC
33
34config SIBYTE_BCM1x55
35 bool
36 select HW_HAS_PCI
37 select SIBYTE_SB1xxx_SOC
38
Ralf Baechle38b18f722005-02-03 14:28:23 +0000[diff] [blame]39config SIBYTE_SB1xxx_SOC
40 bool
41 depends on EXPERIMENTAL
42 select DMA_COHERENT
43 select SIBYTE_CFE
44 select SWAP_IO_SPACE
45 select SYS_SUPPORTS_32BIT_KERNEL
46 select SYS_SUPPORTS_64BIT_KERNEL
47
48choice
49 prompt "SiByte SOC Stepping"
50 depends on SIBYTE_SB1xxx_SOC
51
52config CPU_SB1_PASS_1
53 bool "1250 Pass1"
54 depends on SIBYTE_SB1250
55 select CPU_HAS_PREFETCH
56
57config CPU_SB1_PASS_2_1250
58 bool "1250 An"
59 depends on SIBYTE_SB1250
60 select CPU_SB1_PASS_2
61 help
62 Also called BCM1250 Pass 2
63
64config CPU_SB1_PASS_2_2
65 bool "1250 Bn"
66 depends on SIBYTE_SB1250
67 select CPU_HAS_PREFETCH
68 help
69 Also called BCM1250 Pass 2.2
70
71config CPU_SB1_PASS_4
72 bool "1250 Cn"
73 depends on SIBYTE_SB1250
74 select CPU_HAS_PREFETCH
75 help
76 Also called BCM1250 Pass 3
77
78config CPU_SB1_PASS_2_112x
79 bool "112x Hybrid"
80 depends on SIBYTE_BCM112X
81 select CPU_SB1_PASS_2
82
83config CPU_SB1_PASS_3
84 bool "112x An"
85 depends on SIBYTE_BCM112X
86 select CPU_HAS_PREFETCH
87
88endchoice
89
90config CPU_SB1_PASS_2
91 bool
92
93config SIBYTE_HAS_LDT
94 bool
95 depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
96 default y
97
98config SIMULATION
99 bool "Running under simulation"
100 depends on SIBYTE_SB1xxx_SOC
101 help
102 Build a kernel suitable for running under the GDB simulator.
103 Primarily adjusts the kernel's notion of time.
104
105config SIBYTE_CFE
106 bool "Booting from CFE"
107 depends on SIBYTE_SB1xxx_SOC
108 help
109 Make use of the CFE API for enumerating available memory,
110 controlling secondary CPUs, and possibly console output.
111
112config SIBYTE_CFE_CONSOLE
113 bool "Use firmware console"
114 depends on SIBYTE_CFE
115 help
116 Use the CFE API's console write routines during boot. Other console
117 options (VT console, sb1250 duart console, etc.) should not be
118 configured.
119
120config SIBYTE_STANDALONE
121 bool
122 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
123 default y
124
125config SIBYTE_STANDALONE_RAM_SIZE
126 int "Memory size (in megabytes)"
127 depends on SIBYTE_STANDALONE
128 default "32"
129
130config SIBYTE_BUS_WATCHER
131 bool "Support for Bus Watcher statistics"
132 depends on SIBYTE_SB1xxx_SOC
133 help
134 Handle and keep statistics on the bus error interrupts (COR_ECC,
135 BAD_ECC, IO_BUS).
136
137config SIBYTE_BW_TRACE
138 bool "Capture bus trace before bus error"
139 depends on SIBYTE_BUS_WATCHER
140 help
141 Run a continuous bus trace, dumping the raw data as soon as
142 a ZBbus error is detected. Cannot work if ZBbus profiling
143 is turned on, and also will interfere with JTAG-based trace
144 buffer activity. Raw buffer data is dumped to console, and
145 must be processed off-line.
146
147config SIBYTE_SB1250_PROF
148 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
149 depends on SIBYTE_SB1xxx_SOC
150
151config SIBYTE_TBPROF
152 bool "Support for ZBbus profiling"
153 depends on SIBYTE_SB1xxx_SOC