Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010 Broadcom Corporation |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <typedefs.h> |
| 18 | #include <bcmdefs.h> |
| 19 | #include <osl.h> |
| 20 | #include <bcmutils.h> |
| 21 | #include <siutils.h> |
| 22 | #include <bcmdevs.h> |
| 23 | #include <hndsoc.h> |
| 24 | #include <sbchipc.h> |
| 25 | #include <hndpmu.h> |
| 26 | #include "siutils_priv.h" |
| 27 | |
| 28 | #define PMU_ERROR(args) |
| 29 | |
| 30 | #ifdef BCMDBG |
| 31 | #define PMU_MSG(args) printf args |
| 32 | #else |
| 33 | #define PMU_MSG(args) |
| 34 | #endif /* BCMDBG */ |
| 35 | |
| 36 | /* To check in verbose debugging messages not intended |
| 37 | * to be on except on private builds. |
| 38 | */ |
| 39 | #define PMU_NONE(args) |
| 40 | |
| 41 | /* PLL controls/clocks */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 42 | static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 43 | uint32 xtal); |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 44 | static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); |
| 45 | static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 46 | |
| 47 | /* PMU resources */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 48 | static bool si_pmu_res_depfltr_bb(si_t *sih); |
| 49 | static bool si_pmu_res_depfltr_ncb(si_t *sih); |
| 50 | static bool si_pmu_res_depfltr_paldo(si_t *sih); |
| 51 | static bool si_pmu_res_depfltr_npaldo(si_t *sih); |
| 52 | static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 53 | uint32 rsrcs, bool all); |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 54 | static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 55 | uint8 rsrc); |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 56 | static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax); |
| 57 | static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, |
| 58 | osl_t *osh, uint8 spuravoid); |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 59 | |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 60 | static void si_pmu_set_4330_plldivs(si_t *sih); |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 61 | |
| 62 | /* FVCO frequency */ |
| 63 | #define FVCO_880 880000 /* 880MHz */ |
| 64 | #define FVCO_1760 1760000 /* 1760MHz */ |
| 65 | #define FVCO_1440 1440000 /* 1440MHz */ |
| 66 | #define FVCO_960 960000 /* 960MHz */ |
| 67 | |
| 68 | /* Read/write a chipcontrol reg */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 69 | uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 70 | { |
| 71 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0, |
| 72 | reg); |
| 73 | return si_corereg(sih, SI_CC_IDX, |
| 74 | OFFSETOF(chipcregs_t, chipcontrol_data), mask, val); |
| 75 | } |
| 76 | |
| 77 | /* Read/write a regcontrol reg */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 78 | uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 79 | { |
| 80 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), ~0, |
| 81 | reg); |
| 82 | return si_corereg(sih, SI_CC_IDX, |
| 83 | OFFSETOF(chipcregs_t, regcontrol_data), mask, val); |
| 84 | } |
| 85 | |
| 86 | /* Read/write a pllcontrol reg */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 87 | uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 88 | { |
| 89 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pllcontrol_addr), ~0, |
| 90 | reg); |
| 91 | return si_corereg(sih, SI_CC_IDX, |
| 92 | OFFSETOF(chipcregs_t, pllcontrol_data), mask, val); |
| 93 | } |
| 94 | |
| 95 | /* PMU PLL update */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 96 | void si_pmu_pllupd(si_t *sih) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 97 | { |
| 98 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pmucontrol), |
| 99 | PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD); |
| 100 | } |
| 101 | |
| 102 | /* Setup switcher voltage */ |
| 103 | void |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 104 | BCMATTACHFN(si_pmu_set_switcher_voltage) (si_t *sih, osl_t *osh, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 105 | uint8 bb_voltage, uint8 rf_voltage) { |
| 106 | chipcregs_t *cc; |
| 107 | uint origidx; |
| 108 | |
| 109 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 110 | |
| 111 | /* Remember original core before switch to chipc */ |
| 112 | origidx = si_coreidx(sih); |
| 113 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 114 | ASSERT(cc != NULL); |
| 115 | |
| 116 | W_REG(osh, &cc->regcontrol_addr, 0x01); |
| 117 | W_REG(osh, &cc->regcontrol_data, (uint32) (bb_voltage & 0x1f) << 22); |
| 118 | |
| 119 | W_REG(osh, &cc->regcontrol_addr, 0x00); |
| 120 | W_REG(osh, &cc->regcontrol_data, (uint32) (rf_voltage & 0x1f) << 14); |
| 121 | |
| 122 | /* Return to original core */ |
| 123 | si_setcoreidx(sih, origidx); |
| 124 | } |
| 125 | |
| 126 | void |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 127 | BCMATTACHFN(si_pmu_set_ldo_voltage) (si_t *sih, osl_t *osh, uint8 ldo, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 128 | uint8 voltage) { |
| 129 | uint8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0; |
| 130 | uint8 addr = 0; |
| 131 | |
| 132 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 133 | |
| 134 | switch (CHIPID(sih->chip)) { |
| 135 | case BCM4336_CHIP_ID: |
| 136 | switch (ldo) { |
| 137 | case SET_LDO_VOLTAGE_CLDO_PWM: |
| 138 | addr = 4; |
| 139 | rc_shift = 1; |
| 140 | mask = 0xf; |
| 141 | break; |
| 142 | case SET_LDO_VOLTAGE_CLDO_BURST: |
| 143 | addr = 4; |
| 144 | rc_shift = 5; |
| 145 | mask = 0xf; |
| 146 | break; |
| 147 | case SET_LDO_VOLTAGE_LNLDO1: |
| 148 | addr = 4; |
| 149 | rc_shift = 17; |
| 150 | mask = 0xf; |
| 151 | break; |
| 152 | default: |
| 153 | ASSERT(FALSE); |
| 154 | return; |
| 155 | } |
| 156 | break; |
| 157 | case BCM4330_CHIP_ID: |
| 158 | switch (ldo) { |
| 159 | case SET_LDO_VOLTAGE_CBUCK_PWM: |
| 160 | addr = 3; |
| 161 | rc_shift = 0; |
| 162 | mask = 0x1f; |
| 163 | break; |
| 164 | default: |
| 165 | ASSERT(FALSE); |
| 166 | break; |
| 167 | } |
| 168 | break; |
| 169 | default: |
| 170 | ASSERT(FALSE); |
| 171 | return; |
| 172 | } |
| 173 | |
| 174 | shift = sr_cntl_shift + rc_shift; |
| 175 | |
| 176 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), |
| 177 | ~0, addr); |
| 178 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_data), |
| 179 | mask << shift, (voltage & mask) << shift); |
| 180 | } |
| 181 | |
| 182 | /* d11 slow to fast clock transition time in slow clock cycles */ |
| 183 | #define D11SCC_SLOW2FAST_TRANSITION 2 |
| 184 | |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 185 | uint16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh) |
| 186 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 187 | uint delay = PMU_MAX_TRANSITION_DLY; |
| 188 | chipcregs_t *cc; |
| 189 | uint origidx; |
| 190 | #ifdef BCMDBG |
| 191 | char chn[8]; |
| 192 | chn[0] = 0; /* to suppress compile error */ |
| 193 | #endif |
| 194 | |
| 195 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 196 | |
| 197 | /* Remember original core before switch to chipc */ |
| 198 | origidx = si_coreidx(sih); |
| 199 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 200 | ASSERT(cc != NULL); |
| 201 | |
| 202 | switch (CHIPID(sih->chip)) { |
| 203 | case BCM43224_CHIP_ID: |
| 204 | case BCM43225_CHIP_ID: |
| 205 | case BCM43421_CHIP_ID: |
| 206 | case BCM43235_CHIP_ID: |
| 207 | case BCM43236_CHIP_ID: |
| 208 | case BCM43238_CHIP_ID: |
| 209 | case BCM4331_CHIP_ID: |
| 210 | case BCM6362_CHIP_ID: |
| 211 | case BCM4313_CHIP_ID: |
| 212 | delay = ISSIM_ENAB(sih) ? 70 : 3700; |
| 213 | break; |
| 214 | case BCM4329_CHIP_ID: |
| 215 | if (ISSIM_ENAB(sih)) |
| 216 | delay = 70; |
| 217 | else { |
| 218 | uint32 ilp = si_ilp_clock(sih); |
| 219 | delay = |
| 220 | (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) + |
| 221 | D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - |
| 222 | 1) / ilp); |
| 223 | delay = (11 * delay) / 10; |
| 224 | } |
| 225 | break; |
| 226 | case BCM4319_CHIP_ID: |
| 227 | delay = ISSIM_ENAB(sih) ? 70 : 3700; |
| 228 | break; |
| 229 | case BCM4336_CHIP_ID: |
| 230 | if (ISSIM_ENAB(sih)) |
| 231 | delay = 70; |
| 232 | else { |
| 233 | uint32 ilp = si_ilp_clock(sih); |
| 234 | delay = |
| 235 | (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) + |
| 236 | D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - |
| 237 | 1) / ilp); |
| 238 | delay = (11 * delay) / 10; |
| 239 | } |
| 240 | break; |
| 241 | case BCM4330_CHIP_ID: |
| 242 | if (ISSIM_ENAB(sih)) |
| 243 | delay = 70; |
| 244 | else { |
| 245 | uint32 ilp = si_ilp_clock(sih); |
| 246 | delay = |
| 247 | (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) + |
| 248 | D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - |
| 249 | 1) / ilp); |
| 250 | delay = (11 * delay) / 10; |
| 251 | } |
| 252 | break; |
| 253 | default: |
| 254 | break; |
| 255 | } |
| 256 | /* Return to original core */ |
| 257 | si_setcoreidx(sih, origidx); |
| 258 | |
| 259 | return (uint16) delay; |
| 260 | } |
| 261 | |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 262 | uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) |
| 263 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 264 | chipcregs_t *cc; |
| 265 | uint origidx; |
| 266 | uint32 oldpmucontrol; |
| 267 | |
| 268 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 269 | |
| 270 | /* Remember original core before switch to chipc */ |
| 271 | origidx = si_coreidx(sih); |
| 272 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 273 | ASSERT(cc != NULL); |
| 274 | |
| 275 | oldpmucontrol = R_REG(osh, &cc->pmucontrol); |
| 276 | if (force) |
| 277 | W_REG(osh, &cc->pmucontrol, oldpmucontrol & |
| 278 | ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); |
| 279 | else |
| 280 | W_REG(osh, &cc->pmucontrol, oldpmucontrol | |
| 281 | (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); |
| 282 | |
| 283 | /* Return to original core */ |
| 284 | si_setcoreidx(sih, origidx); |
| 285 | |
| 286 | return oldpmucontrol; |
| 287 | } |
| 288 | |
| 289 | /* Setup resource up/down timers */ |
| 290 | typedef struct { |
| 291 | uint8 resnum; |
| 292 | uint16 updown; |
| 293 | } pmu_res_updown_t; |
| 294 | |
| 295 | /* Change resource dependancies masks */ |
| 296 | typedef struct { |
| 297 | uint32 res_mask; /* resources (chip specific) */ |
| 298 | int8 action; /* action */ |
| 299 | uint32 depend_mask; /* changes to the dependancies mask */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 300 | bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */ |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 301 | } pmu_res_depend_t; |
| 302 | |
| 303 | /* Resource dependancies mask change action */ |
| 304 | #define RES_DEPEND_SET 0 /* Override the dependancies mask */ |
| 305 | #define RES_DEPEND_ADD 1 /* Add to the dependancies mask */ |
| 306 | #define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */ |
| 307 | |
| 308 | static const pmu_res_updown_t BCMATTACHDATA(bcm4328a0_res_updown)[] = |
| 309 | { |
| 310 | { |
| 311 | RES4328_EXT_SWITCHER_PWM, 0x0101}, { |
| 312 | RES4328_BB_SWITCHER_PWM, 0x1f01}, { |
| 313 | RES4328_BB_SWITCHER_BURST, 0x010f}, { |
| 314 | RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, { |
| 315 | RES4328_ILP_REQUEST, 0x0202}, { |
| 316 | RES4328_RADIO_SWITCHER_PWM, 0x0f01}, { |
| 317 | RES4328_RADIO_SWITCHER_BURST, 0x0f01}, { |
| 318 | RES4328_ROM_SWITCH, 0x0101}, { |
| 319 | RES4328_PA_REF_LDO, 0x0f01}, { |
| 320 | RES4328_RADIO_LDO, 0x0f01}, { |
| 321 | RES4328_AFE_LDO, 0x0f01}, { |
| 322 | RES4328_PLL_LDO, 0x0f01}, { |
| 323 | RES4328_BG_FILTBYP, 0x0101}, { |
| 324 | RES4328_TX_FILTBYP, 0x0101}, { |
| 325 | RES4328_RX_FILTBYP, 0x0101}, { |
| 326 | RES4328_XTAL_PU, 0x0101}, { |
| 327 | RES4328_XTAL_EN, 0xa001}, { |
| 328 | RES4328_BB_PLL_FILTBYP, 0x0101}, { |
| 329 | RES4328_RF_PLL_FILTBYP, 0x0101}, { |
| 330 | RES4328_BB_PLL_PU, 0x0701} |
| 331 | }; |
| 332 | |
| 333 | static const pmu_res_depend_t BCMATTACHDATA(bcm4328a0_res_depend)[] = |
| 334 | { |
| 335 | /* Adjust ILP request resource not to force ext/BB switchers into burst mode */ |
| 336 | { |
| 337 | PMURES_BIT(RES4328_ILP_REQUEST), |
| 338 | RES_DEPEND_SET, |
| 339 | PMURES_BIT(RES4328_EXT_SWITCHER_PWM) | |
| 340 | PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL} |
| 341 | }; |
| 342 | |
| 343 | static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown_qt)[] = |
| 344 | { |
| 345 | { |
| 346 | RES4325_HT_AVAIL, 0x0300}, { |
| 347 | RES4325_BBPLL_PWRSW_PU, 0x0101}, { |
| 348 | RES4325_RFPLL_PWRSW_PU, 0x0101}, { |
| 349 | RES4325_ALP_AVAIL, 0x0100}, { |
| 350 | RES4325_XTAL_PU, 0x1000}, { |
| 351 | RES4325_LNLDO1_PU, 0x0800}, { |
| 352 | RES4325_CLDO_CBUCK_PWM, 0x0101}, { |
| 353 | RES4325_CBUCK_PWM, 0x0803} |
| 354 | }; |
| 355 | |
| 356 | static const pmu_res_updown_t BCMATTACHDATA(bcm4325a0_res_updown)[] = |
| 357 | { |
| 358 | { |
| 359 | RES4325_XTAL_PU, 0x1501} |
| 360 | }; |
| 361 | |
| 362 | static const pmu_res_depend_t BCMATTACHDATA(bcm4325a0_res_depend)[] = |
| 363 | { |
| 364 | /* Adjust OTP PU resource dependencies - remove BB BURST */ |
| 365 | { |
| 366 | PMURES_BIT(RES4325_OTP_PU), |
| 367 | RES_DEPEND_REMOVE, |
| 368 | PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL}, |
| 369 | /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */ |
| 370 | { |
| 371 | PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL), |
| 372 | RES_DEPEND_ADD, |
| 373 | PMURES_BIT(RES4325_BUCK_BOOST_BURST) | |
| 374 | PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb}, |
| 375 | /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ |
| 376 | { |
| 377 | PMURES_BIT(RES4325_HT_AVAIL), |
| 378 | RES_DEPEND_ADD, |
| 379 | PMURES_BIT(RES4325_RX_PWRSW_PU) | |
| 380 | PMURES_BIT(RES4325_TX_PWRSW_PU) | |
| 381 | PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | |
| 382 | PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL}, |
| 383 | /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */ |
| 384 | { |
| 385 | PMURES_BIT(RES4325_ILP_REQUEST) | |
| 386 | PMURES_BIT(RES4325_ABUCK_BURST) | |
| 387 | PMURES_BIT(RES4325_ABUCK_PWM) | |
| 388 | PMURES_BIT(RES4325_LNLDO1_PU) | |
| 389 | PMURES_BIT(RES4325C1_LNLDO2_PU) | |
| 390 | PMURES_BIT(RES4325_XTAL_PU) | |
| 391 | PMURES_BIT(RES4325_ALP_AVAIL) | |
| 392 | PMURES_BIT(RES4325_RX_PWRSW_PU) | |
| 393 | PMURES_BIT(RES4325_TX_PWRSW_PU) | |
| 394 | PMURES_BIT(RES4325_RFPLL_PWRSW_PU) | |
| 395 | PMURES_BIT(RES4325_LOGEN_PWRSW_PU) | |
| 396 | PMURES_BIT(RES4325_AFE_PWRSW_PU) | |
| 397 | PMURES_BIT(RES4325_BBPLL_PWRSW_PU) | |
| 398 | PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE, |
| 399 | PMURES_BIT(RES4325B0_CBUCK_LPOM) | |
| 400 | PMURES_BIT(RES4325B0_CBUCK_BURST) | |
| 401 | PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb} |
| 402 | }; |
| 403 | |
| 404 | static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown_qt)[] = |
| 405 | { |
| 406 | { |
| 407 | RES4315_HT_AVAIL, 0x0101}, { |
| 408 | RES4315_XTAL_PU, 0x0100}, { |
| 409 | RES4315_LNLDO1_PU, 0x0100}, { |
| 410 | RES4315_PALDO_PU, 0x0100}, { |
| 411 | RES4315_CLDO_PU, 0x0100}, { |
| 412 | RES4315_CBUCK_PWM, 0x0100}, { |
| 413 | RES4315_CBUCK_BURST, 0x0100}, { |
| 414 | RES4315_CBUCK_LPOM, 0x0100} |
| 415 | }; |
| 416 | |
| 417 | static const pmu_res_updown_t BCMATTACHDATA(bcm4315a0_res_updown)[] = |
| 418 | { |
| 419 | { |
| 420 | RES4315_XTAL_PU, 0x2501} |
| 421 | }; |
| 422 | |
| 423 | static const pmu_res_depend_t BCMATTACHDATA(bcm4315a0_res_depend)[] = |
| 424 | { |
| 425 | /* Adjust OTP PU resource dependencies - not need PALDO unless write */ |
| 426 | { |
| 427 | PMURES_BIT(RES4315_OTP_PU), |
| 428 | RES_DEPEND_REMOVE, |
| 429 | PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo}, |
| 430 | /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */ |
| 431 | { |
| 432 | PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL), |
| 433 | RES_DEPEND_ADD, |
| 434 | PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo}, |
| 435 | /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ |
| 436 | { |
| 437 | PMURES_BIT(RES4315_HT_AVAIL), |
| 438 | RES_DEPEND_ADD, |
| 439 | PMURES_BIT(RES4315_RX_PWRSW_PU) | |
| 440 | PMURES_BIT(RES4315_TX_PWRSW_PU) | |
| 441 | PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | |
| 442 | PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL}, |
| 443 | /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */ |
| 444 | { |
| 445 | PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) | |
| 446 | PMURES_BIT(RES4315_LNLDO1_PU) | |
| 447 | PMURES_BIT(RES4315_OTP_PU) | |
| 448 | PMURES_BIT(RES4315_LNLDO2_PU) | |
| 449 | PMURES_BIT(RES4315_XTAL_PU) | |
| 450 | PMURES_BIT(RES4315_ALP_AVAIL) | |
| 451 | PMURES_BIT(RES4315_RX_PWRSW_PU) | |
| 452 | PMURES_BIT(RES4315_TX_PWRSW_PU) | |
| 453 | PMURES_BIT(RES4315_RFPLL_PWRSW_PU) | |
| 454 | PMURES_BIT(RES4315_LOGEN_PWRSW_PU) | |
| 455 | PMURES_BIT(RES4315_AFE_PWRSW_PU) | |
| 456 | PMURES_BIT(RES4315_BBPLL_PWRSW_PU) | |
| 457 | PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE, |
| 458 | PMURES_BIT(RES4315_CBUCK_LPOM) | |
| 459 | PMURES_BIT(RES4315_CBUCK_BURST) | |
| 460 | PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb} |
| 461 | }; |
| 462 | |
| 463 | /* 4329 specific. needs to come back this issue later */ |
| 464 | static const pmu_res_updown_t BCMINITDATA(bcm4329_res_updown)[] = |
| 465 | { |
| 466 | { |
| 467 | RES4329_XTAL_PU, 0x1501} |
| 468 | }; |
| 469 | |
| 470 | static const pmu_res_depend_t BCMINITDATA(bcm4329_res_depend)[] = |
| 471 | { |
| 472 | /* Adjust HT Avail resource dependencies */ |
| 473 | { |
| 474 | PMURES_BIT(RES4329_HT_AVAIL), |
| 475 | RES_DEPEND_ADD, |
| 476 | PMURES_BIT(RES4329_CBUCK_LPOM) | |
| 477 | PMURES_BIT(RES4329_CBUCK_BURST) | |
| 478 | PMURES_BIT(RES4329_CBUCK_PWM) | |
| 479 | PMURES_BIT(RES4329_CLDO_PU) | |
| 480 | PMURES_BIT(RES4329_PALDO_PU) | |
| 481 | PMURES_BIT(RES4329_LNLDO1_PU) | |
| 482 | PMURES_BIT(RES4329_XTAL_PU) | |
| 483 | PMURES_BIT(RES4329_ALP_AVAIL) | |
| 484 | PMURES_BIT(RES4329_RX_PWRSW_PU) | |
| 485 | PMURES_BIT(RES4329_TX_PWRSW_PU) | |
| 486 | PMURES_BIT(RES4329_RFPLL_PWRSW_PU) | |
| 487 | PMURES_BIT(RES4329_LOGEN_PWRSW_PU) | |
| 488 | PMURES_BIT(RES4329_AFE_PWRSW_PU) | |
| 489 | PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL} |
| 490 | }; |
| 491 | |
| 492 | static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown_qt)[] = |
| 493 | { |
| 494 | { |
| 495 | RES4319_HT_AVAIL, 0x0101}, { |
| 496 | RES4319_XTAL_PU, 0x0100}, { |
| 497 | RES4319_LNLDO1_PU, 0x0100}, { |
| 498 | RES4319_PALDO_PU, 0x0100}, { |
| 499 | RES4319_CLDO_PU, 0x0100}, { |
| 500 | RES4319_CBUCK_PWM, 0x0100}, { |
| 501 | RES4319_CBUCK_BURST, 0x0100}, { |
| 502 | RES4319_CBUCK_LPOM, 0x0100} |
| 503 | }; |
| 504 | |
| 505 | static const pmu_res_updown_t BCMATTACHDATA(bcm4319a0_res_updown)[] = |
| 506 | { |
| 507 | { |
| 508 | RES4319_XTAL_PU, 0x3f01} |
| 509 | }; |
| 510 | |
| 511 | static const pmu_res_depend_t BCMATTACHDATA(bcm4319a0_res_depend)[] = |
| 512 | { |
| 513 | /* Adjust OTP PU resource dependencies - not need PALDO unless write */ |
| 514 | { |
| 515 | PMURES_BIT(RES4319_OTP_PU), |
| 516 | RES_DEPEND_REMOVE, |
| 517 | PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo}, |
| 518 | /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */ |
| 519 | { |
| 520 | PMURES_BIT(RES4319_HT_AVAIL), |
| 521 | RES_DEPEND_ADD, |
| 522 | PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo}, |
| 523 | /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */ |
| 524 | { |
| 525 | PMURES_BIT(RES4319_HT_AVAIL), |
| 526 | RES_DEPEND_ADD, |
| 527 | PMURES_BIT(RES4319_RX_PWRSW_PU) | |
| 528 | PMURES_BIT(RES4319_TX_PWRSW_PU) | |
| 529 | PMURES_BIT(RES4319_RFPLL_PWRSW_PU) | |
| 530 | PMURES_BIT(RES4319_LOGEN_PWRSW_PU) | |
| 531 | PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL} |
| 532 | }; |
| 533 | |
| 534 | static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown_qt)[] = |
| 535 | { |
| 536 | { |
| 537 | RES4336_HT_AVAIL, 0x0101}, { |
| 538 | RES4336_XTAL_PU, 0x0100}, { |
| 539 | RES4336_CLDO_PU, 0x0100}, { |
| 540 | RES4336_CBUCK_PWM, 0x0100}, { |
| 541 | RES4336_CBUCK_BURST, 0x0100}, { |
| 542 | RES4336_CBUCK_LPOM, 0x0100} |
| 543 | }; |
| 544 | |
| 545 | static const pmu_res_updown_t BCMATTACHDATA(bcm4336a0_res_updown)[] = |
| 546 | { |
| 547 | { |
| 548 | RES4336_HT_AVAIL, 0x0D01} |
| 549 | }; |
| 550 | |
| 551 | static const pmu_res_depend_t BCMATTACHDATA(bcm4336a0_res_depend)[] = |
| 552 | { |
| 553 | /* Just a dummy entry for now */ |
| 554 | { |
| 555 | PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL} |
| 556 | }; |
| 557 | |
| 558 | static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown_qt)[] = |
| 559 | { |
| 560 | { |
| 561 | RES4330_HT_AVAIL, 0x0101}, { |
| 562 | RES4330_XTAL_PU, 0x0100}, { |
| 563 | RES4330_CLDO_PU, 0x0100}, { |
| 564 | RES4330_CBUCK_PWM, 0x0100}, { |
| 565 | RES4330_CBUCK_BURST, 0x0100}, { |
| 566 | RES4330_CBUCK_LPOM, 0x0100} |
| 567 | }; |
| 568 | |
| 569 | static const pmu_res_updown_t BCMATTACHDATA(bcm4330a0_res_updown)[] = |
| 570 | { |
| 571 | { |
| 572 | RES4330_HT_AVAIL, 0x0e02} |
| 573 | }; |
| 574 | |
| 575 | static const pmu_res_depend_t BCMATTACHDATA(bcm4330a0_res_depend)[] = |
| 576 | { |
| 577 | /* Just a dummy entry for now */ |
| 578 | { |
| 579 | PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL} |
| 580 | }; |
| 581 | |
| 582 | /* TRUE if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 583 | static bool BCMATTACHFN(si_pmu_res_depfltr_bb) (si_t *sih) |
| 584 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 585 | return (sih->boardflags & BFL_BUCKBOOST) != 0; |
| 586 | } |
| 587 | |
| 588 | /* TRUE if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 589 | static bool BCMATTACHFN(si_pmu_res_depfltr_ncb) (si_t *sih) |
| 590 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 591 | |
Jason Cooper | 90ea229 | 2010-09-14 09:45:32 -0400 | [diff] [blame] | 592 | return (sih->boardflags & BFL_NOCBUCK) != 0; |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | /* TRUE if the power topology uses the PALDO */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 596 | static bool BCMATTACHFN(si_pmu_res_depfltr_paldo) (si_t *sih) |
| 597 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 598 | return (sih->boardflags & BFL_PALDO) != 0; |
| 599 | } |
| 600 | |
| 601 | /* TRUE if the power topology doesn't use the PALDO */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 602 | static bool BCMATTACHFN(si_pmu_res_depfltr_npaldo) (si_t *sih) |
| 603 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 604 | return (sih->boardflags & BFL_PALDO) == 0; |
| 605 | } |
| 606 | |
| 607 | #define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \ |
| 608 | sih->boardtype == BCM94325BGABU_BOARD) |
| 609 | |
| 610 | /* Determine min/max rsrc masks. Value 0 leaves hardware at default. */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 611 | static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 612 | { |
| 613 | uint32 min_mask = 0, max_mask = 0; |
| 614 | uint rsrcs; |
| 615 | char *val; |
| 616 | |
| 617 | /* # resources */ |
| 618 | rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; |
| 619 | |
| 620 | /* determine min/max rsrc masks */ |
| 621 | switch (CHIPID(sih->chip)) { |
| 622 | case BCM43224_CHIP_ID: |
| 623 | case BCM43225_CHIP_ID: |
| 624 | case BCM43421_CHIP_ID: |
| 625 | case BCM43235_CHIP_ID: |
| 626 | case BCM43236_CHIP_ID: |
| 627 | case BCM43238_CHIP_ID: |
| 628 | case BCM4331_CHIP_ID: |
| 629 | case BCM6362_CHIP_ID: |
| 630 | /* ??? */ |
| 631 | break; |
| 632 | |
| 633 | case BCM4329_CHIP_ID: |
| 634 | /* 4329 spedific issue. Needs to come back this issue later */ |
| 635 | /* Down to save the power. */ |
| 636 | min_mask = |
| 637 | PMURES_BIT(RES4329_CBUCK_LPOM) | |
| 638 | PMURES_BIT(RES4329_CLDO_PU); |
| 639 | /* Allow (but don't require) PLL to turn on */ |
| 640 | max_mask = 0x3ff63e; |
| 641 | break; |
| 642 | case BCM4319_CHIP_ID: |
| 643 | /* We only need a few resources to be kept on all the time */ |
| 644 | min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) | |
| 645 | PMURES_BIT(RES4319_CLDO_PU); |
| 646 | |
| 647 | /* Allow everything else to be turned on upon requests */ |
| 648 | max_mask = ~(~0 << rsrcs); |
| 649 | break; |
| 650 | case BCM4336_CHIP_ID: |
| 651 | /* Down to save the power. */ |
| 652 | min_mask = |
| 653 | PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU) |
| 654 | | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU) |
| 655 | | PMURES_BIT(RES4336_DIS_INT_RESET_PD); |
| 656 | /* Allow (but don't require) PLL to turn on */ |
| 657 | max_mask = 0x1ffffff; |
| 658 | break; |
| 659 | |
| 660 | case BCM4330_CHIP_ID: |
| 661 | /* Down to save the power. */ |
| 662 | min_mask = |
| 663 | PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU) |
| 664 | | PMURES_BIT(RES4330_DIS_INT_RESET_PD) | |
| 665 | PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU); |
| 666 | /* Allow (but don't require) PLL to turn on */ |
| 667 | max_mask = 0xfffffff; |
| 668 | break; |
| 669 | |
| 670 | case BCM4313_CHIP_ID: |
| 671 | min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) | |
| 672 | PMURES_BIT(RES4313_XTAL_PU_RSRC) | |
| 673 | PMURES_BIT(RES4313_ALP_AVAIL_RSRC) | |
| 674 | PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC); |
| 675 | max_mask = 0xffff; |
| 676 | break; |
| 677 | default: |
| 678 | break; |
| 679 | } |
| 680 | |
| 681 | /* Apply nvram override to min mask */ |
Jason Cooper | ca8c1e5 | 2010-09-14 09:45:33 -0400 | [diff] [blame^] | 682 | val = getvar(NULL, "rmin"); |
| 683 | if (val != NULL) { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 684 | PMU_MSG(("Applying rmin=%s to min_mask\n", val)); |
| 685 | min_mask = (uint32) bcm_strtoul(val, NULL, 0); |
| 686 | } |
| 687 | /* Apply nvram override to max mask */ |
Jason Cooper | ca8c1e5 | 2010-09-14 09:45:33 -0400 | [diff] [blame^] | 688 | val = getvar(NULL, "rmax"); |
| 689 | if (val != NULL) { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 690 | PMU_MSG(("Applying rmax=%s to max_mask\n", val)); |
| 691 | max_mask = (uint32) bcm_strtoul(val, NULL, 0); |
| 692 | } |
| 693 | |
| 694 | *pmin = min_mask; |
| 695 | *pmax = max_mask; |
| 696 | } |
| 697 | |
| 698 | /* initialize PMU resources */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 699 | void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh) |
| 700 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 701 | chipcregs_t *cc; |
| 702 | uint origidx; |
| 703 | const pmu_res_updown_t *pmu_res_updown_table = NULL; |
| 704 | uint pmu_res_updown_table_sz = 0; |
| 705 | const pmu_res_depend_t *pmu_res_depend_table = NULL; |
| 706 | uint pmu_res_depend_table_sz = 0; |
| 707 | uint32 min_mask = 0, max_mask = 0; |
| 708 | char name[8], *val; |
| 709 | uint i, rsrcs; |
| 710 | |
| 711 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 712 | |
| 713 | /* Remember original core before switch to chipc */ |
| 714 | origidx = si_coreidx(sih); |
| 715 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 716 | ASSERT(cc != NULL); |
| 717 | |
| 718 | switch (CHIPID(sih->chip)) { |
| 719 | case BCM4329_CHIP_ID: |
| 720 | /* Optimize resources up/down timers */ |
| 721 | if (ISSIM_ENAB(sih)) { |
| 722 | pmu_res_updown_table = NULL; |
| 723 | pmu_res_updown_table_sz = 0; |
| 724 | } else { |
| 725 | pmu_res_updown_table = bcm4329_res_updown; |
| 726 | pmu_res_updown_table_sz = ARRAYSIZE(bcm4329_res_updown); |
| 727 | } |
| 728 | /* Optimize resources dependencies */ |
| 729 | pmu_res_depend_table = bcm4329_res_depend; |
| 730 | pmu_res_depend_table_sz = ARRAYSIZE(bcm4329_res_depend); |
| 731 | break; |
| 732 | |
| 733 | case BCM4319_CHIP_ID: |
| 734 | /* Optimize resources up/down timers */ |
| 735 | if (ISSIM_ENAB(sih)) { |
| 736 | pmu_res_updown_table = bcm4319a0_res_updown_qt; |
| 737 | pmu_res_updown_table_sz = |
| 738 | ARRAYSIZE(bcm4319a0_res_updown_qt); |
| 739 | } else { |
| 740 | pmu_res_updown_table = bcm4319a0_res_updown; |
| 741 | pmu_res_updown_table_sz = |
| 742 | ARRAYSIZE(bcm4319a0_res_updown); |
| 743 | } |
| 744 | /* Optimize resources dependancies masks */ |
| 745 | pmu_res_depend_table = bcm4319a0_res_depend; |
| 746 | pmu_res_depend_table_sz = ARRAYSIZE(bcm4319a0_res_depend); |
| 747 | break; |
| 748 | |
| 749 | case BCM4336_CHIP_ID: |
| 750 | /* Optimize resources up/down timers */ |
| 751 | if (ISSIM_ENAB(sih)) { |
| 752 | pmu_res_updown_table = bcm4336a0_res_updown_qt; |
| 753 | pmu_res_updown_table_sz = |
| 754 | ARRAYSIZE(bcm4336a0_res_updown_qt); |
| 755 | } else { |
| 756 | pmu_res_updown_table = bcm4336a0_res_updown; |
| 757 | pmu_res_updown_table_sz = |
| 758 | ARRAYSIZE(bcm4336a0_res_updown); |
| 759 | } |
| 760 | /* Optimize resources dependancies masks */ |
| 761 | pmu_res_depend_table = bcm4336a0_res_depend; |
| 762 | pmu_res_depend_table_sz = ARRAYSIZE(bcm4336a0_res_depend); |
| 763 | break; |
| 764 | |
| 765 | case BCM4330_CHIP_ID: |
| 766 | /* Optimize resources up/down timers */ |
| 767 | if (ISSIM_ENAB(sih)) { |
| 768 | pmu_res_updown_table = bcm4330a0_res_updown_qt; |
| 769 | pmu_res_updown_table_sz = |
| 770 | ARRAYSIZE(bcm4330a0_res_updown_qt); |
| 771 | } else { |
| 772 | pmu_res_updown_table = bcm4330a0_res_updown; |
| 773 | pmu_res_updown_table_sz = |
| 774 | ARRAYSIZE(bcm4330a0_res_updown); |
| 775 | } |
| 776 | /* Optimize resources dependancies masks */ |
| 777 | pmu_res_depend_table = bcm4330a0_res_depend; |
| 778 | pmu_res_depend_table_sz = ARRAYSIZE(bcm4330a0_res_depend); |
| 779 | break; |
| 780 | |
| 781 | default: |
| 782 | break; |
| 783 | } |
| 784 | |
| 785 | /* # resources */ |
| 786 | rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; |
| 787 | |
| 788 | /* Program up/down timers */ |
| 789 | while (pmu_res_updown_table_sz--) { |
| 790 | ASSERT(pmu_res_updown_table != NULL); |
| 791 | PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n", |
| 792 | pmu_res_updown_table[pmu_res_updown_table_sz].resnum, |
| 793 | pmu_res_updown_table[pmu_res_updown_table_sz].updown)); |
| 794 | W_REG(osh, &cc->res_table_sel, |
| 795 | pmu_res_updown_table[pmu_res_updown_table_sz].resnum); |
| 796 | W_REG(osh, &cc->res_updn_timer, |
| 797 | pmu_res_updown_table[pmu_res_updown_table_sz].updown); |
| 798 | } |
| 799 | /* Apply nvram overrides to up/down timers */ |
| 800 | for (i = 0; i < rsrcs; i++) { |
| 801 | snprintf(name, sizeof(name), "r%dt", i); |
Jason Cooper | ca8c1e5 | 2010-09-14 09:45:33 -0400 | [diff] [blame^] | 802 | val = getvar(NULL, name); |
| 803 | if (val == NULL) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 804 | continue; |
| 805 | PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name, |
| 806 | val, i)); |
| 807 | W_REG(osh, &cc->res_table_sel, (uint32) i); |
| 808 | W_REG(osh, &cc->res_updn_timer, |
| 809 | (uint32) bcm_strtoul(val, NULL, 0)); |
| 810 | } |
| 811 | |
| 812 | /* Program resource dependencies table */ |
| 813 | while (pmu_res_depend_table_sz--) { |
| 814 | ASSERT(pmu_res_depend_table != NULL); |
| 815 | if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL |
| 816 | && !(pmu_res_depend_table[pmu_res_depend_table_sz]. |
| 817 | filter) (sih)) |
| 818 | continue; |
| 819 | for (i = 0; i < rsrcs; i++) { |
| 820 | if ((pmu_res_depend_table[pmu_res_depend_table_sz]. |
| 821 | res_mask & PMURES_BIT(i)) == 0) |
| 822 | continue; |
| 823 | W_REG(osh, &cc->res_table_sel, i); |
| 824 | switch (pmu_res_depend_table[pmu_res_depend_table_sz]. |
| 825 | action) { |
| 826 | case RES_DEPEND_SET: |
| 827 | PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask)); |
| 828 | W_REG(osh, &cc->res_dep_mask, |
| 829 | pmu_res_depend_table |
| 830 | [pmu_res_depend_table_sz].depend_mask); |
| 831 | break; |
| 832 | case RES_DEPEND_ADD: |
| 833 | PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i)); |
| 834 | OR_REG(osh, &cc->res_dep_mask, |
| 835 | pmu_res_depend_table |
| 836 | [pmu_res_depend_table_sz].depend_mask); |
| 837 | break; |
| 838 | case RES_DEPEND_REMOVE: |
| 839 | PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i)); |
| 840 | AND_REG(osh, &cc->res_dep_mask, |
| 841 | ~pmu_res_depend_table |
| 842 | [pmu_res_depend_table_sz].depend_mask); |
| 843 | break; |
| 844 | default: |
| 845 | ASSERT(0); |
| 846 | break; |
| 847 | } |
| 848 | } |
| 849 | } |
| 850 | /* Apply nvram overrides to dependancies masks */ |
| 851 | for (i = 0; i < rsrcs; i++) { |
| 852 | snprintf(name, sizeof(name), "r%dd", i); |
Jason Cooper | ca8c1e5 | 2010-09-14 09:45:33 -0400 | [diff] [blame^] | 853 | val = getvar(NULL, name); |
| 854 | if (val == NULL) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 855 | continue; |
| 856 | PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val, |
| 857 | i)); |
| 858 | W_REG(osh, &cc->res_table_sel, (uint32) i); |
| 859 | W_REG(osh, &cc->res_dep_mask, |
| 860 | (uint32) bcm_strtoul(val, NULL, 0)); |
| 861 | } |
| 862 | |
| 863 | /* Determine min/max rsrc masks */ |
| 864 | si_pmu_res_masks(sih, &min_mask, &max_mask); |
| 865 | |
| 866 | /* It is required to program max_mask first and then min_mask */ |
| 867 | |
| 868 | /* Program max resource mask */ |
| 869 | |
| 870 | if (max_mask) { |
| 871 | PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask)); |
| 872 | W_REG(osh, &cc->max_res_mask, max_mask); |
| 873 | } |
| 874 | |
| 875 | /* Program min resource mask */ |
| 876 | |
| 877 | if (min_mask) { |
| 878 | PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask)); |
| 879 | W_REG(osh, &cc->min_res_mask, min_mask); |
| 880 | } |
| 881 | |
| 882 | /* Add some delay; allow resources to come up and settle. */ |
| 883 | OSL_DELAY(2000); |
| 884 | |
| 885 | /* Return to original core */ |
| 886 | si_setcoreidx(sih, origidx); |
| 887 | } |
| 888 | |
| 889 | /* setup pll and query clock speed */ |
| 890 | typedef struct { |
| 891 | uint16 freq; |
| 892 | uint8 xf; |
| 893 | uint8 wbint; |
| 894 | uint32 wbfrac; |
| 895 | } pmu0_xtaltab0_t; |
| 896 | |
| 897 | /* the following table is based on 880Mhz fvco */ |
| 898 | static const pmu0_xtaltab0_t BCMINITDATA(pmu0_xtaltab0)[] = |
| 899 | { |
| 900 | { |
| 901 | 12000, 1, 73, 349525}, { |
| 902 | 13000, 2, 67, 725937}, { |
| 903 | 14400, 3, 61, 116508}, { |
| 904 | 15360, 4, 57, 305834}, { |
| 905 | 16200, 5, 54, 336579}, { |
| 906 | 16800, 6, 52, 399457}, { |
| 907 | 19200, 7, 45, 873813}, { |
| 908 | 19800, 8, 44, 466033}, { |
| 909 | 20000, 9, 44, 0}, { |
| 910 | 25000, 10, 70, 419430}, { |
| 911 | 26000, 11, 67, 725937}, { |
| 912 | 30000, 12, 58, 699050}, { |
| 913 | 38400, 13, 45, 873813}, { |
| 914 | 40000, 14, 45, 0}, { |
| 915 | 0, 0, 0, 0} |
| 916 | }; |
| 917 | |
| 918 | #define PMU0_XTAL0_DEFAULT 8 |
| 919 | |
| 920 | /* setup pll and query clock speed */ |
| 921 | typedef struct { |
| 922 | uint16 fref; |
| 923 | uint8 xf; |
| 924 | uint8 p1div; |
| 925 | uint8 p2div; |
| 926 | uint8 ndiv_int; |
| 927 | uint32 ndiv_frac; |
| 928 | } pmu1_xtaltab0_t; |
| 929 | |
| 930 | static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = |
| 931 | { |
| 932 | { |
| 933 | 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { |
| 934 | 13000, 2, 1, 6, 0xb, 0x483483}, { |
| 935 | 14400, 3, 1, 10, 0xa, 0x1C71C7}, { |
| 936 | 15360, 4, 1, 5, 0xb, 0x755555}, { |
| 937 | 16200, 5, 1, 10, 0x5, 0x6E9E06}, { |
| 938 | 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { |
| 939 | 19200, 7, 1, 4, 0xb, 0x755555}, { |
| 940 | 19800, 8, 1, 11, 0x4, 0xA57EB}, { |
| 941 | 20000, 9, 1, 11, 0x4, 0x0}, { |
| 942 | 24000, 10, 3, 11, 0xa, 0x0}, { |
| 943 | 25000, 11, 5, 16, 0xb, 0x0}, { |
| 944 | 26000, 12, 1, 1, 0x21, 0xD89D89}, { |
| 945 | 30000, 13, 3, 8, 0xb, 0x0}, { |
| 946 | 37400, 14, 3, 1, 0x46, 0x969696}, { |
| 947 | 38400, 15, 1, 1, 0x16, 0xEAAAAA}, { |
| 948 | 40000, 16, 1, 2, 0xb, 0}, { |
| 949 | 0, 0, 0, 0, 0, 0} |
| 950 | }; |
| 951 | |
| 952 | /* the following table is based on 880Mhz fvco */ |
| 953 | static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880)[] = |
| 954 | { |
| 955 | { |
| 956 | 12000, 1, 3, 22, 0x9, 0xFFFFEF}, { |
| 957 | 13000, 2, 1, 6, 0xb, 0x483483}, { |
| 958 | 14400, 3, 1, 10, 0xa, 0x1C71C7}, { |
| 959 | 15360, 4, 1, 5, 0xb, 0x755555}, { |
| 960 | 16200, 5, 1, 10, 0x5, 0x6E9E06}, { |
| 961 | 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, { |
| 962 | 19200, 7, 1, 4, 0xb, 0x755555}, { |
| 963 | 19800, 8, 1, 11, 0x4, 0xA57EB}, { |
| 964 | 20000, 9, 1, 11, 0x4, 0x0}, { |
| 965 | 24000, 10, 3, 11, 0xa, 0x0}, { |
| 966 | 25000, 11, 5, 16, 0xb, 0x0}, { |
| 967 | 26000, 12, 1, 2, 0x10, 0xEC4EC4}, { |
| 968 | 30000, 13, 3, 8, 0xb, 0x0}, { |
| 969 | 33600, 14, 1, 2, 0xd, 0x186186}, { |
| 970 | 38400, 15, 1, 2, 0xb, 0x755555}, { |
| 971 | 40000, 16, 1, 2, 0xb, 0}, { |
| 972 | 0, 0, 0, 0, 0, 0} |
| 973 | }; |
| 974 | |
| 975 | #define PMU1_XTALTAB0_880_12000K 0 |
| 976 | #define PMU1_XTALTAB0_880_13000K 1 |
| 977 | #define PMU1_XTALTAB0_880_14400K 2 |
| 978 | #define PMU1_XTALTAB0_880_15360K 3 |
| 979 | #define PMU1_XTALTAB0_880_16200K 4 |
| 980 | #define PMU1_XTALTAB0_880_16800K 5 |
| 981 | #define PMU1_XTALTAB0_880_19200K 6 |
| 982 | #define PMU1_XTALTAB0_880_19800K 7 |
| 983 | #define PMU1_XTALTAB0_880_20000K 8 |
| 984 | #define PMU1_XTALTAB0_880_24000K 9 |
| 985 | #define PMU1_XTALTAB0_880_25000K 10 |
| 986 | #define PMU1_XTALTAB0_880_26000K 11 |
| 987 | #define PMU1_XTALTAB0_880_30000K 12 |
| 988 | #define PMU1_XTALTAB0_880_37400K 13 |
| 989 | #define PMU1_XTALTAB0_880_38400K 14 |
| 990 | #define PMU1_XTALTAB0_880_40000K 15 |
| 991 | |
| 992 | /* the following table is based on 1760Mhz fvco */ |
| 993 | static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1760)[] = |
| 994 | { |
| 995 | { |
| 996 | 12000, 1, 3, 44, 0x9, 0xFFFFEF}, { |
| 997 | 13000, 2, 1, 12, 0xb, 0x483483}, { |
| 998 | 14400, 3, 1, 20, 0xa, 0x1C71C7}, { |
| 999 | 15360, 4, 1, 10, 0xb, 0x755555}, { |
| 1000 | 16200, 5, 1, 20, 0x5, 0x6E9E06}, { |
| 1001 | 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, { |
| 1002 | 19200, 7, 1, 18, 0x5, 0x17B425}, { |
| 1003 | 19800, 8, 1, 22, 0x4, 0xA57EB}, { |
| 1004 | 20000, 9, 1, 22, 0x4, 0x0}, { |
| 1005 | 24000, 10, 3, 22, 0xa, 0x0}, { |
| 1006 | 25000, 11, 5, 32, 0xb, 0x0}, { |
| 1007 | 26000, 12, 1, 4, 0x10, 0xEC4EC4}, { |
| 1008 | 30000, 13, 3, 16, 0xb, 0x0}, { |
| 1009 | 38400, 14, 1, 10, 0x4, 0x955555}, { |
| 1010 | 40000, 15, 1, 4, 0xb, 0}, { |
| 1011 | 0, 0, 0, 0, 0, 0} |
| 1012 | }; |
| 1013 | |
| 1014 | /* table index */ |
| 1015 | #define PMU1_XTALTAB0_1760_12000K 0 |
| 1016 | #define PMU1_XTALTAB0_1760_13000K 1 |
| 1017 | #define PMU1_XTALTAB0_1760_14400K 2 |
| 1018 | #define PMU1_XTALTAB0_1760_15360K 3 |
| 1019 | #define PMU1_XTALTAB0_1760_16200K 4 |
| 1020 | #define PMU1_XTALTAB0_1760_16800K 5 |
| 1021 | #define PMU1_XTALTAB0_1760_19200K 6 |
| 1022 | #define PMU1_XTALTAB0_1760_19800K 7 |
| 1023 | #define PMU1_XTALTAB0_1760_20000K 8 |
| 1024 | #define PMU1_XTALTAB0_1760_24000K 9 |
| 1025 | #define PMU1_XTALTAB0_1760_25000K 10 |
| 1026 | #define PMU1_XTALTAB0_1760_26000K 11 |
| 1027 | #define PMU1_XTALTAB0_1760_30000K 12 |
| 1028 | #define PMU1_XTALTAB0_1760_38400K 13 |
| 1029 | #define PMU1_XTALTAB0_1760_40000K 14 |
| 1030 | |
| 1031 | /* the following table is based on 1440Mhz fvco */ |
| 1032 | static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1440)[] = |
| 1033 | { |
| 1034 | { |
| 1035 | 12000, 1, 1, 1, 0x78, 0x0}, { |
| 1036 | 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, { |
| 1037 | 14400, 3, 1, 1, 0x64, 0x0}, { |
| 1038 | 15360, 4, 1, 1, 0x5D, 0xC00000}, { |
| 1039 | 16200, 5, 1, 1, 0x58, 0xE38E38}, { |
| 1040 | 16800, 6, 1, 1, 0x55, 0xB6DB6D}, { |
| 1041 | 19200, 7, 1, 1, 0x4B, 0}, { |
| 1042 | 19800, 8, 1, 1, 0x48, 0xBA2E8B}, { |
| 1043 | 20000, 9, 1, 1, 0x48, 0x0}, { |
| 1044 | 25000, 10, 1, 1, 0x39, 0x999999}, { |
| 1045 | 26000, 11, 1, 1, 0x37, 0x627627}, { |
| 1046 | 30000, 12, 1, 1, 0x30, 0x0}, { |
| 1047 | 37400, 13, 2, 1, 0x4D, 0x15E76}, { |
| 1048 | 38400, 13, 2, 1, 0x4B, 0x0}, { |
| 1049 | 40000, 14, 2, 1, 0x48, 0x0}, { |
| 1050 | 48000, 15, 2, 1, 0x3c, 0x0}, { |
| 1051 | 0, 0, 0, 0, 0, 0} |
| 1052 | }; |
| 1053 | |
| 1054 | /* table index */ |
| 1055 | #define PMU1_XTALTAB0_1440_12000K 0 |
| 1056 | #define PMU1_XTALTAB0_1440_13000K 1 |
| 1057 | #define PMU1_XTALTAB0_1440_14400K 2 |
| 1058 | #define PMU1_XTALTAB0_1440_15360K 3 |
| 1059 | #define PMU1_XTALTAB0_1440_16200K 4 |
| 1060 | #define PMU1_XTALTAB0_1440_16800K 5 |
| 1061 | #define PMU1_XTALTAB0_1440_19200K 6 |
| 1062 | #define PMU1_XTALTAB0_1440_19800K 7 |
| 1063 | #define PMU1_XTALTAB0_1440_20000K 8 |
| 1064 | #define PMU1_XTALTAB0_1440_25000K 9 |
| 1065 | #define PMU1_XTALTAB0_1440_26000K 10 |
| 1066 | #define PMU1_XTALTAB0_1440_30000K 11 |
| 1067 | #define PMU1_XTALTAB0_1440_37400K 12 |
| 1068 | #define PMU1_XTALTAB0_1440_38400K 13 |
| 1069 | #define PMU1_XTALTAB0_1440_40000K 14 |
| 1070 | #define PMU1_XTALTAB0_1440_48000K 15 |
| 1071 | |
| 1072 | #define XTAL_FREQ_24000MHZ 24000 |
| 1073 | #define XTAL_FREQ_30000MHZ 30000 |
| 1074 | #define XTAL_FREQ_37400MHZ 37400 |
| 1075 | #define XTAL_FREQ_48000MHZ 48000 |
| 1076 | |
| 1077 | static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_960)[] = |
| 1078 | { |
| 1079 | { |
| 1080 | 12000, 1, 1, 1, 0x50, 0x0}, { |
| 1081 | 13000, 2, 1, 1, 0x49, 0xD89D89}, { |
| 1082 | 14400, 3, 1, 1, 0x42, 0xAAAAAA}, { |
| 1083 | 15360, 4, 1, 1, 0x3E, 0x800000}, { |
| 1084 | 16200, 5, 1, 1, 0x39, 0x425ED0}, { |
| 1085 | 16800, 6, 1, 1, 0x39, 0x249249}, { |
| 1086 | 19200, 7, 1, 1, 0x32, 0x0}, { |
| 1087 | 19800, 8, 1, 1, 0x30, 0x7C1F07}, { |
| 1088 | 20000, 9, 1, 1, 0x30, 0x0}, { |
| 1089 | 25000, 10, 1, 1, 0x26, 0x666666}, { |
| 1090 | 26000, 11, 1, 1, 0x24, 0xEC4EC4}, { |
| 1091 | 30000, 12, 1, 1, 0x20, 0x0}, { |
| 1092 | 37400, 13, 2, 1, 0x33, 0x563EF9}, { |
| 1093 | 38400, 14, 2, 1, 0x32, 0x0}, { |
| 1094 | 40000, 15, 2, 1, 0x30, 0x0}, { |
| 1095 | 48000, 16, 2, 1, 0x28, 0x0}, { |
| 1096 | 0, 0, 0, 0, 0, 0} |
| 1097 | }; |
| 1098 | |
| 1099 | /* table index */ |
| 1100 | #define PMU1_XTALTAB0_960_12000K 0 |
| 1101 | #define PMU1_XTALTAB0_960_13000K 1 |
| 1102 | #define PMU1_XTALTAB0_960_14400K 2 |
| 1103 | #define PMU1_XTALTAB0_960_15360K 3 |
| 1104 | #define PMU1_XTALTAB0_960_16200K 4 |
| 1105 | #define PMU1_XTALTAB0_960_16800K 5 |
| 1106 | #define PMU1_XTALTAB0_960_19200K 6 |
| 1107 | #define PMU1_XTALTAB0_960_19800K 7 |
| 1108 | #define PMU1_XTALTAB0_960_20000K 8 |
| 1109 | #define PMU1_XTALTAB0_960_25000K 9 |
| 1110 | #define PMU1_XTALTAB0_960_26000K 10 |
| 1111 | #define PMU1_XTALTAB0_960_30000K 11 |
| 1112 | #define PMU1_XTALTAB0_960_37400K 12 |
| 1113 | #define PMU1_XTALTAB0_960_38400K 13 |
| 1114 | #define PMU1_XTALTAB0_960_40000K 14 |
| 1115 | #define PMU1_XTALTAB0_960_48000K 15 |
| 1116 | |
| 1117 | /* select xtal table for each chip */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1118 | static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaltab0) (si_t *sih) |
| 1119 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1120 | #ifdef BCMDBG |
| 1121 | char chn[8]; |
| 1122 | #endif |
| 1123 | switch (CHIPID(sih->chip)) { |
| 1124 | case BCM4329_CHIP_ID: |
| 1125 | return pmu1_xtaltab0_880_4329; |
| 1126 | case BCM4319_CHIP_ID: |
| 1127 | return pmu1_xtaltab0_1440; |
| 1128 | case BCM4336_CHIP_ID: |
| 1129 | return pmu1_xtaltab0_960; |
| 1130 | case BCM4330_CHIP_ID: |
| 1131 | if (CST4330_CHIPMODE_SDIOD(sih->chipst)) |
| 1132 | return pmu1_xtaltab0_960; |
| 1133 | else |
| 1134 | return pmu1_xtaltab0_1440; |
| 1135 | default: |
| 1136 | PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", |
| 1137 | bcm_chipname(sih->chip, chn, 8))); |
| 1138 | break; |
| 1139 | } |
| 1140 | ASSERT(0); |
| 1141 | return NULL; |
| 1142 | } |
| 1143 | |
| 1144 | /* select default xtal frequency for each chip */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1145 | static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaldef0) (si_t *sih) |
| 1146 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1147 | #ifdef BCMDBG |
| 1148 | char chn[8]; |
| 1149 | #endif |
| 1150 | |
| 1151 | switch (CHIPID(sih->chip)) { |
| 1152 | case BCM4329_CHIP_ID: |
| 1153 | /* Default to 38400Khz */ |
| 1154 | return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K]; |
| 1155 | case BCM4319_CHIP_ID: |
| 1156 | /* Default to 30000Khz */ |
| 1157 | return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K]; |
| 1158 | case BCM4336_CHIP_ID: |
| 1159 | /* Default to 26000Khz */ |
| 1160 | return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K]; |
| 1161 | case BCM4330_CHIP_ID: |
| 1162 | /* Default to 37400Khz */ |
| 1163 | if (CST4330_CHIPMODE_SDIOD(sih->chipst)) |
| 1164 | return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K]; |
| 1165 | else |
| 1166 | return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K]; |
| 1167 | default: |
| 1168 | PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", |
| 1169 | bcm_chipname(sih->chip, chn, 8))); |
| 1170 | break; |
| 1171 | } |
| 1172 | ASSERT(0); |
| 1173 | return NULL; |
| 1174 | } |
| 1175 | |
| 1176 | /* select default pll fvco for each chip */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1177 | static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih) |
| 1178 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1179 | #ifdef BCMDBG |
| 1180 | char chn[8]; |
| 1181 | #endif |
| 1182 | |
| 1183 | switch (CHIPID(sih->chip)) { |
| 1184 | case BCM4329_CHIP_ID: |
| 1185 | return FVCO_880; |
| 1186 | case BCM4319_CHIP_ID: |
| 1187 | return FVCO_1440; |
| 1188 | case BCM4336_CHIP_ID: |
| 1189 | return FVCO_960; |
| 1190 | case BCM4330_CHIP_ID: |
| 1191 | if (CST4330_CHIPMODE_SDIOD(sih->chipst)) |
| 1192 | return FVCO_960; |
| 1193 | else |
| 1194 | return FVCO_1440; |
| 1195 | default: |
| 1196 | PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", |
| 1197 | bcm_chipname(sih->chip, chn, 8))); |
| 1198 | break; |
| 1199 | } |
| 1200 | ASSERT(0); |
| 1201 | return 0; |
| 1202 | } |
| 1203 | |
| 1204 | /* query alp/xtal clock frequency */ |
| 1205 | static uint32 |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1206 | BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) |
| 1207 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1208 | const pmu1_xtaltab0_t *xt; |
| 1209 | uint32 xf; |
| 1210 | |
| 1211 | /* Find the frequency in the table */ |
| 1212 | xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> |
| 1213 | PCTL_XTALFREQ_SHIFT; |
| 1214 | for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++) |
| 1215 | if (xt->xf == xf) |
| 1216 | break; |
| 1217 | /* Could not find it so assign a default value */ |
| 1218 | if (xt == NULL || xt->fref == 0) |
| 1219 | xt = si_pmu1_xtaldef0(sih); |
| 1220 | ASSERT(xt != NULL && xt->fref != 0); |
| 1221 | |
| 1222 | return xt->fref * 1000; |
| 1223 | } |
| 1224 | |
| 1225 | /* Set up PLL registers in the PMU as per the crystal speed. |
| 1226 | * XtalFreq field in pmucontrol register being 0 indicates the PLL |
| 1227 | * is not programmed and the h/w default is assumed to work, in which |
| 1228 | * case the xtal frequency is unknown to the s/w so we need to call |
| 1229 | * si_pmu1_xtaldef0() wherever it is needed to return a default value. |
| 1230 | */ |
| 1231 | static void |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 1232 | BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1233 | uint32 xtal) { |
| 1234 | const pmu1_xtaltab0_t *xt; |
| 1235 | uint32 tmp; |
| 1236 | uint32 buf_strength = 0; |
| 1237 | uint8 ndiv_mode = 1; |
| 1238 | |
| 1239 | /* Use h/w default PLL config */ |
| 1240 | if (xtal == 0) { |
| 1241 | PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n")); |
| 1242 | return; |
| 1243 | } |
| 1244 | |
| 1245 | /* Find the frequency in the table */ |
| 1246 | for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++) |
| 1247 | if (xt->fref == xtal) |
| 1248 | break; |
| 1249 | |
| 1250 | /* Check current PLL state, bail out if it has been programmed or |
| 1251 | * we don't know how to program it. |
| 1252 | */ |
| 1253 | if (xt == NULL || xt->fref == 0) { |
| 1254 | PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000)); |
| 1255 | return; |
| 1256 | } |
| 1257 | /* for 4319 bootloader already programs the PLL but bootloader does not program the |
| 1258 | PLL4 and PLL5. So Skip this check for 4319 |
| 1259 | */ |
| 1260 | if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> |
| 1261 | PCTL_XTALFREQ_SHIFT) == xt->xf) && |
| 1262 | !((CHIPID(sih->chip) == BCM4319_CHIP_ID) |
| 1263 | || (CHIPID(sih->chip) == BCM4330_CHIP_ID))) { |
| 1264 | PMU_MSG(("PLL already programmed for %d.%d MHz\n", |
| 1265 | xt->fref / 1000, xt->fref % 1000)); |
| 1266 | return; |
| 1267 | } |
| 1268 | |
| 1269 | PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf)); |
| 1270 | PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, |
| 1271 | xt->fref % 1000)); |
| 1272 | |
| 1273 | switch (CHIPID(sih->chip)) { |
| 1274 | case BCM4329_CHIP_ID: |
| 1275 | /* Change the BBPLL drive strength to 8 for all channels */ |
| 1276 | buf_strength = 0x888888; |
| 1277 | AND_REG(osh, &cc->min_res_mask, |
| 1278 | ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | |
| 1279 | PMURES_BIT(RES4329_HT_AVAIL))); |
| 1280 | AND_REG(osh, &cc->max_res_mask, |
| 1281 | ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) | |
| 1282 | PMURES_BIT(RES4329_HT_AVAIL))); |
| 1283 | SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, |
| 1284 | PMU_MAX_TRANSITION_DLY); |
| 1285 | ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); |
| 1286 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 1287 | if (xt->fref == 38400) |
| 1288 | tmp = 0x200024C0; |
| 1289 | else if (xt->fref == 37400) |
| 1290 | tmp = 0x20004500; |
| 1291 | else if (xt->fref == 26000) |
| 1292 | tmp = 0x200024C0; |
| 1293 | else |
| 1294 | tmp = 0x200005C0; /* Chip Dflt Settings */ |
| 1295 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1296 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 1297 | tmp = |
| 1298 | R_REG(osh, |
| 1299 | &cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK; |
| 1300 | if ((xt->fref == 38400) || (xt->fref == 37400) |
| 1301 | || (xt->fref == 26000)) |
| 1302 | tmp |= 0x15; |
| 1303 | else |
| 1304 | tmp |= 0x25; /* Chip Dflt Settings */ |
| 1305 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1306 | break; |
| 1307 | |
| 1308 | case BCM4319_CHIP_ID: |
| 1309 | /* Change the BBPLL drive strength to 2 for all channels */ |
| 1310 | buf_strength = 0x222222; |
| 1311 | |
| 1312 | /* Make sure the PLL is off */ |
| 1313 | /* WAR65104: Disable the HT_AVAIL resource first and then |
| 1314 | * after a delay (more than downtime for HT_AVAIL) remove the |
| 1315 | * BBPLL resource; backplane clock moves to ALP from HT. |
| 1316 | */ |
| 1317 | AND_REG(osh, &cc->min_res_mask, |
| 1318 | ~(PMURES_BIT(RES4319_HT_AVAIL))); |
| 1319 | AND_REG(osh, &cc->max_res_mask, |
| 1320 | ~(PMURES_BIT(RES4319_HT_AVAIL))); |
| 1321 | |
| 1322 | OSL_DELAY(100); |
| 1323 | AND_REG(osh, &cc->min_res_mask, |
| 1324 | ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); |
| 1325 | AND_REG(osh, &cc->max_res_mask, |
| 1326 | ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU))); |
| 1327 | |
| 1328 | OSL_DELAY(100); |
| 1329 | SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, |
| 1330 | PMU_MAX_TRANSITION_DLY); |
| 1331 | ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); |
| 1332 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 1333 | tmp = 0x200005c0; |
| 1334 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1335 | break; |
| 1336 | |
| 1337 | case BCM4336_CHIP_ID: |
| 1338 | AND_REG(osh, &cc->min_res_mask, |
| 1339 | ~(PMURES_BIT(RES4336_HT_AVAIL) | |
| 1340 | PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); |
| 1341 | AND_REG(osh, &cc->max_res_mask, |
| 1342 | ~(PMURES_BIT(RES4336_HT_AVAIL) | |
| 1343 | PMURES_BIT(RES4336_MACPHY_CLKAVAIL))); |
| 1344 | OSL_DELAY(100); |
| 1345 | SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, |
| 1346 | PMU_MAX_TRANSITION_DLY); |
| 1347 | ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); |
| 1348 | break; |
| 1349 | |
| 1350 | case BCM4330_CHIP_ID: |
| 1351 | AND_REG(osh, &cc->min_res_mask, |
| 1352 | ~(PMURES_BIT(RES4330_HT_AVAIL) | |
| 1353 | PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); |
| 1354 | AND_REG(osh, &cc->max_res_mask, |
| 1355 | ~(PMURES_BIT(RES4330_HT_AVAIL) | |
| 1356 | PMURES_BIT(RES4330_MACPHY_CLKAVAIL))); |
| 1357 | OSL_DELAY(100); |
| 1358 | SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, |
| 1359 | PMU_MAX_TRANSITION_DLY); |
| 1360 | ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); |
| 1361 | break; |
| 1362 | |
| 1363 | default: |
| 1364 | ASSERT(0); |
| 1365 | } |
| 1366 | |
| 1367 | PMU_MSG(("Done masking\n")); |
| 1368 | |
| 1369 | /* Write p1div and p2div to pllcontrol[0] */ |
| 1370 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 1371 | tmp = R_REG(osh, &cc->pllcontrol_data) & |
| 1372 | ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK); |
| 1373 | tmp |= |
| 1374 | ((xt-> |
| 1375 | p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) | |
| 1376 | ((xt-> |
| 1377 | p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK); |
| 1378 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1379 | |
| 1380 | if ((CHIPID(sih->chip) == BCM4330_CHIP_ID)) |
| 1381 | si_pmu_set_4330_plldivs(sih); |
| 1382 | |
| 1383 | if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) |
| 1384 | && (CHIPREV(sih->chiprev) == 0)) { |
| 1385 | |
| 1386 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 1387 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1388 | tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK); |
| 1389 | tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL; |
| 1390 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1391 | } |
| 1392 | if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) || |
| 1393 | (CHIPID(sih->chip) == BCM4336_CHIP_ID) || |
| 1394 | (CHIPID(sih->chip) == BCM4330_CHIP_ID)) |
| 1395 | ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB; |
| 1396 | else |
| 1397 | ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH; |
| 1398 | |
| 1399 | /* Write ndiv_int and ndiv_mode to pllcontrol[2] */ |
| 1400 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 1401 | tmp = R_REG(osh, &cc->pllcontrol_data) & |
| 1402 | ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK); |
| 1403 | tmp |= |
| 1404 | ((xt-> |
| 1405 | ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) & |
| 1406 | PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode << |
| 1407 | PMU1_PLL0_PC2_NDIV_MODE_SHIFT) & |
| 1408 | PMU1_PLL0_PC2_NDIV_MODE_MASK); |
| 1409 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1410 | |
| 1411 | /* Write ndiv_frac to pllcontrol[3] */ |
| 1412 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 1413 | tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK; |
| 1414 | tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) & |
| 1415 | PMU1_PLL0_PC3_NDIV_FRAC_MASK); |
| 1416 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1417 | |
| 1418 | /* Write clock driving strength to pllcontrol[5] */ |
| 1419 | if (buf_strength) { |
| 1420 | PMU_MSG(("Adjusting PLL buffer drive strength: %x\n", |
| 1421 | buf_strength)); |
| 1422 | |
| 1423 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 1424 | tmp = |
| 1425 | R_REG(osh, |
| 1426 | &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK; |
| 1427 | tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT); |
| 1428 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 1429 | } |
| 1430 | |
| 1431 | PMU_MSG(("Done pll\n")); |
| 1432 | |
| 1433 | /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs |
| 1434 | * to be updated. |
| 1435 | */ |
| 1436 | if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) |
| 1437 | && (xt->fref != XTAL_FREQ_30000MHZ)) { |
| 1438 | W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2); |
| 1439 | tmp = |
| 1440 | R_REG(osh, |
| 1441 | &cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK; |
| 1442 | if (xt->fref == XTAL_FREQ_24000MHZ) { |
| 1443 | tmp |= |
| 1444 | (CCTL_4319USB_24MHZ_PLL_SEL << |
| 1445 | CCTL_4319USB_XTAL_SEL_SHIFT); |
| 1446 | } else if (xt->fref == XTAL_FREQ_48000MHZ) { |
| 1447 | tmp |= |
| 1448 | (CCTL_4319USB_48MHZ_PLL_SEL << |
| 1449 | CCTL_4319USB_XTAL_SEL_SHIFT); |
| 1450 | } |
| 1451 | W_REG(osh, &cc->chipcontrol_data, tmp); |
| 1452 | } |
| 1453 | |
| 1454 | /* Flush deferred pll control registers writes */ |
| 1455 | if (sih->pmurev >= 2) |
| 1456 | OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD); |
| 1457 | |
| 1458 | /* Write XtalFreq. Set the divisor also. */ |
| 1459 | tmp = R_REG(osh, &cc->pmucontrol) & |
| 1460 | ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK); |
| 1461 | tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & |
| 1462 | PCTL_ILP_DIV_MASK) | |
| 1463 | ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK); |
| 1464 | |
| 1465 | if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) |
| 1466 | && CHIPREV(sih->chiprev) == 0) { |
| 1467 | /* clear the htstretch before clearing HTReqEn */ |
| 1468 | AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT); |
| 1469 | tmp &= ~PCTL_HT_REQ_EN; |
| 1470 | } |
| 1471 | |
| 1472 | W_REG(osh, &cc->pmucontrol, tmp); |
| 1473 | } |
| 1474 | |
| 1475 | /* query the CPU clock frequency */ |
| 1476 | static uint32 |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1477 | BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) |
| 1478 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1479 | uint32 tmp, m1div; |
| 1480 | #ifdef BCMDBG |
| 1481 | uint32 ndiv_int, ndiv_frac, p2div, p1div, fvco; |
| 1482 | uint32 fref; |
| 1483 | #endif |
| 1484 | uint32 FVCO = si_pmu1_pllfvco0(sih); |
| 1485 | |
| 1486 | /* Read m1div from pllcontrol[1] */ |
| 1487 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 1488 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1489 | m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT; |
| 1490 | |
| 1491 | #ifdef BCMDBG |
| 1492 | /* Read p2div/p1div from pllcontrol[0] */ |
| 1493 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 1494 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1495 | p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT; |
| 1496 | p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT; |
| 1497 | |
| 1498 | /* Calculate fvco based on xtal freq and ndiv and pdiv */ |
| 1499 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 1500 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1501 | ndiv_int = |
| 1502 | (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT; |
| 1503 | |
| 1504 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 1505 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1506 | ndiv_frac = |
| 1507 | (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >> |
| 1508 | PMU1_PLL0_PC3_NDIV_FRAC_SHIFT; |
| 1509 | |
| 1510 | fref = si_pmu1_alpclk0(sih, osh, cc) / 1000; |
| 1511 | |
| 1512 | fvco = (fref * ndiv_int) << 8; |
| 1513 | fvco += (fref * (ndiv_frac >> 12)) >> 4; |
| 1514 | fvco += (fref * (ndiv_frac & 0xfff)) >> 12; |
| 1515 | fvco >>= 8; |
| 1516 | fvco *= p2div; |
| 1517 | fvco /= p1div; |
| 1518 | fvco /= 1000; |
| 1519 | fvco *= 1000; |
| 1520 | |
| 1521 | PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco)); |
| 1522 | |
| 1523 | FVCO = fvco; |
| 1524 | #endif /* BCMDBG */ |
| 1525 | |
| 1526 | /* Return ARM/SB clock */ |
| 1527 | return FVCO / m1div * 1000; |
| 1528 | } |
| 1529 | |
| 1530 | /* initialize PLL */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1531 | void BCMATTACHFN(si_pmu_pll_init) (si_t *sih, osl_t *osh, uint xtalfreq) |
| 1532 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1533 | chipcregs_t *cc; |
| 1534 | uint origidx; |
| 1535 | #ifdef BCMDBG |
| 1536 | char chn[8]; |
| 1537 | #endif |
| 1538 | |
| 1539 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 1540 | |
| 1541 | /* Remember original core before switch to chipc */ |
| 1542 | origidx = si_coreidx(sih); |
| 1543 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1544 | ASSERT(cc != NULL); |
| 1545 | |
| 1546 | switch (CHIPID(sih->chip)) { |
| 1547 | case BCM4329_CHIP_ID: |
| 1548 | if (xtalfreq == 0) |
| 1549 | xtalfreq = 38400; |
| 1550 | si_pmu1_pllinit0(sih, osh, cc, xtalfreq); |
| 1551 | break; |
| 1552 | case BCM4313_CHIP_ID: |
| 1553 | case BCM43224_CHIP_ID: |
| 1554 | case BCM43225_CHIP_ID: |
| 1555 | case BCM43421_CHIP_ID: |
| 1556 | case BCM43235_CHIP_ID: |
| 1557 | case BCM43236_CHIP_ID: |
| 1558 | case BCM43238_CHIP_ID: |
| 1559 | case BCM4331_CHIP_ID: |
| 1560 | case BCM6362_CHIP_ID: |
| 1561 | /* ??? */ |
| 1562 | break; |
| 1563 | case BCM4319_CHIP_ID: |
| 1564 | case BCM4336_CHIP_ID: |
| 1565 | case BCM4330_CHIP_ID: |
| 1566 | si_pmu1_pllinit0(sih, osh, cc, xtalfreq); |
| 1567 | break; |
| 1568 | default: |
| 1569 | PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n", |
| 1570 | bcm_chipname(sih->chip, chn, 8), sih->chiprev, |
| 1571 | sih->pmurev)); |
| 1572 | break; |
| 1573 | } |
| 1574 | |
| 1575 | #ifdef BCMDBG_FORCEHT |
| 1576 | OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT); |
| 1577 | #endif |
| 1578 | |
| 1579 | /* Return to original core */ |
| 1580 | si_setcoreidx(sih, origidx); |
| 1581 | } |
| 1582 | |
| 1583 | /* query alp/xtal clock frequency */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1584 | uint32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh) |
| 1585 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1586 | chipcregs_t *cc; |
| 1587 | uint origidx; |
| 1588 | uint32 clock = ALP_CLOCK; |
| 1589 | #ifdef BCMDBG |
| 1590 | char chn[8]; |
| 1591 | #endif |
| 1592 | |
| 1593 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 1594 | |
| 1595 | /* Remember original core before switch to chipc */ |
| 1596 | origidx = si_coreidx(sih); |
| 1597 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1598 | ASSERT(cc != NULL); |
| 1599 | |
| 1600 | switch (CHIPID(sih->chip)) { |
| 1601 | case BCM43224_CHIP_ID: |
| 1602 | case BCM43225_CHIP_ID: |
| 1603 | case BCM43421_CHIP_ID: |
| 1604 | case BCM43235_CHIP_ID: |
| 1605 | case BCM43236_CHIP_ID: |
| 1606 | case BCM43238_CHIP_ID: |
| 1607 | case BCM4331_CHIP_ID: |
| 1608 | case BCM6362_CHIP_ID: |
| 1609 | case BCM4716_CHIP_ID: |
| 1610 | case BCM4748_CHIP_ID: |
| 1611 | case BCM47162_CHIP_ID: |
| 1612 | case BCM4313_CHIP_ID: |
| 1613 | case BCM5357_CHIP_ID: |
| 1614 | /* always 20Mhz */ |
| 1615 | clock = 20000 * 1000; |
| 1616 | break; |
| 1617 | case BCM4329_CHIP_ID: |
| 1618 | case BCM4319_CHIP_ID: |
| 1619 | case BCM4336_CHIP_ID: |
| 1620 | case BCM4330_CHIP_ID: |
| 1621 | |
| 1622 | clock = si_pmu1_alpclk0(sih, osh, cc); |
| 1623 | break; |
| 1624 | case BCM5356_CHIP_ID: |
| 1625 | /* always 25Mhz */ |
| 1626 | clock = 25000 * 1000; |
| 1627 | break; |
| 1628 | default: |
| 1629 | PMU_MSG(("No ALP clock specified " |
| 1630 | "for chip %s rev %d pmurev %d, using default %d Hz\n", |
| 1631 | bcm_chipname(sih->chip, chn, 8), sih->chiprev, |
| 1632 | sih->pmurev, clock)); |
| 1633 | break; |
| 1634 | } |
| 1635 | |
| 1636 | /* Return to original core */ |
| 1637 | si_setcoreidx(sih, origidx); |
| 1638 | return clock; |
| 1639 | } |
| 1640 | |
| 1641 | /* Find the output of the "m" pll divider given pll controls that start with |
| 1642 | * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. |
| 1643 | */ |
| 1644 | static uint32 |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 1645 | BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1646 | uint m) { |
| 1647 | uint32 tmp, div, ndiv, p1, p2, fc; |
| 1648 | |
| 1649 | if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) { |
| 1650 | PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0)); |
| 1651 | return 0; |
| 1652 | } |
| 1653 | |
| 1654 | /* Strictly there is an m5 divider, but I'm not sure we use it */ |
| 1655 | if ((m == 0) || (m > 4)) { |
| 1656 | PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m)); |
| 1657 | return 0; |
| 1658 | } |
| 1659 | |
| 1660 | if (CHIPID(sih->chip) == BCM5357_CHIP_ID) { |
| 1661 | /* Detect failure in clock setting */ |
| 1662 | if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) { |
Jason Cooper | 90ea229 | 2010-09-14 09:45:32 -0400 | [diff] [blame] | 1663 | return 133 * 1000000; |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1664 | } |
| 1665 | } |
| 1666 | |
| 1667 | W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF); |
| 1668 | (void)R_REG(osh, &cc->pllcontrol_addr); |
| 1669 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1670 | p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT; |
| 1671 | p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT; |
| 1672 | |
| 1673 | W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF); |
| 1674 | (void)R_REG(osh, &cc->pllcontrol_addr); |
| 1675 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1676 | div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK; |
| 1677 | |
| 1678 | W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF); |
| 1679 | (void)R_REG(osh, &cc->pllcontrol_addr); |
| 1680 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 1681 | ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT; |
| 1682 | |
| 1683 | /* Do calculation in Mhz */ |
| 1684 | fc = si_pmu_alp_clock(sih, osh) / 1000000; |
| 1685 | fc = (p1 * ndiv * fc) / p2; |
| 1686 | |
| 1687 | PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n", |
| 1688 | __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div)); |
| 1689 | |
| 1690 | /* Return clock in Hertz */ |
Jason Cooper | 90ea229 | 2010-09-14 09:45:32 -0400 | [diff] [blame] | 1691 | return (fc / div) * 1000000; |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1692 | } |
| 1693 | |
| 1694 | /* query backplane clock frequency */ |
| 1695 | /* For designs that feed the same clock to both backplane |
| 1696 | * and CPU just return the CPU clock speed. |
| 1697 | */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1698 | uint32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh) |
| 1699 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1700 | chipcregs_t *cc; |
| 1701 | uint origidx; |
| 1702 | uint32 clock = HT_CLOCK; |
| 1703 | #ifdef BCMDBG |
| 1704 | char chn[8]; |
| 1705 | #endif |
| 1706 | |
| 1707 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 1708 | |
| 1709 | /* Remember original core before switch to chipc */ |
| 1710 | origidx = si_coreidx(sih); |
| 1711 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1712 | ASSERT(cc != NULL); |
| 1713 | |
| 1714 | switch (CHIPID(sih->chip)) { |
| 1715 | case BCM43224_CHIP_ID: |
| 1716 | case BCM43225_CHIP_ID: |
| 1717 | case BCM43421_CHIP_ID: |
| 1718 | case BCM4331_CHIP_ID: |
| 1719 | case BCM6362_CHIP_ID: |
| 1720 | /* 96MHz backplane clock */ |
| 1721 | clock = 96000 * 1000; |
| 1722 | break; |
| 1723 | case BCM4716_CHIP_ID: |
| 1724 | case BCM4748_CHIP_ID: |
| 1725 | case BCM47162_CHIP_ID: |
| 1726 | clock = |
| 1727 | si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0, |
| 1728 | PMU5_MAINPLL_SI); |
| 1729 | break; |
| 1730 | case BCM4329_CHIP_ID: |
| 1731 | if (CHIPREV(sih->chiprev) == 0) |
| 1732 | clock = 38400 * 1000; |
| 1733 | else |
| 1734 | clock = si_pmu1_cpuclk0(sih, osh, cc); |
| 1735 | break; |
| 1736 | case BCM4319_CHIP_ID: |
| 1737 | case BCM4336_CHIP_ID: |
| 1738 | case BCM4330_CHIP_ID: |
| 1739 | clock = si_pmu1_cpuclk0(sih, osh, cc); |
| 1740 | break; |
| 1741 | case BCM4313_CHIP_ID: |
| 1742 | /* 80MHz backplane clock */ |
| 1743 | clock = 80000 * 1000; |
| 1744 | break; |
| 1745 | case BCM43235_CHIP_ID: |
| 1746 | case BCM43236_CHIP_ID: |
| 1747 | case BCM43238_CHIP_ID: |
| 1748 | clock = |
| 1749 | (cc->chipstatus & CST43236_BP_CLK) ? (120000 * |
| 1750 | 1000) : (96000 * |
| 1751 | 1000); |
| 1752 | break; |
| 1753 | case BCM5356_CHIP_ID: |
| 1754 | clock = |
| 1755 | si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0, |
| 1756 | PMU5_MAINPLL_SI); |
| 1757 | break; |
| 1758 | case BCM5357_CHIP_ID: |
| 1759 | clock = |
| 1760 | si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0, |
| 1761 | PMU5_MAINPLL_SI); |
| 1762 | break; |
| 1763 | default: |
| 1764 | PMU_MSG(("No backplane clock specified " |
| 1765 | "for chip %s rev %d pmurev %d, using default %d Hz\n", |
| 1766 | bcm_chipname(sih->chip, chn, 8), sih->chiprev, |
| 1767 | sih->pmurev, clock)); |
| 1768 | break; |
| 1769 | } |
| 1770 | |
| 1771 | /* Return to original core */ |
| 1772 | si_setcoreidx(sih, origidx); |
| 1773 | return clock; |
| 1774 | } |
| 1775 | |
| 1776 | /* query CPU clock frequency */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1777 | uint32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh) |
| 1778 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1779 | chipcregs_t *cc; |
| 1780 | uint origidx; |
| 1781 | uint32 clock; |
| 1782 | |
| 1783 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 1784 | |
| 1785 | if ((sih->pmurev >= 5) && |
| 1786 | !((CHIPID(sih->chip) == BCM4329_CHIP_ID) || |
| 1787 | (CHIPID(sih->chip) == BCM4319_CHIP_ID) || |
| 1788 | (CHIPID(sih->chip) == BCM43236_CHIP_ID) || |
| 1789 | (CHIPID(sih->chip) == BCM4336_CHIP_ID) || |
| 1790 | (CHIPID(sih->chip) == BCM4330_CHIP_ID))) { |
| 1791 | uint pll; |
| 1792 | |
| 1793 | switch (CHIPID(sih->chip)) { |
| 1794 | case BCM5356_CHIP_ID: |
| 1795 | pll = PMU5356_MAINPLL_PLL0; |
| 1796 | break; |
| 1797 | case BCM5357_CHIP_ID: |
| 1798 | pll = PMU5357_MAINPLL_PLL0; |
| 1799 | break; |
| 1800 | default: |
| 1801 | pll = PMU4716_MAINPLL_PLL0; |
| 1802 | break; |
| 1803 | } |
| 1804 | |
| 1805 | /* Remember original core before switch to chipc */ |
| 1806 | origidx = si_coreidx(sih); |
| 1807 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1808 | ASSERT(cc != NULL); |
| 1809 | |
| 1810 | clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU); |
| 1811 | |
| 1812 | /* Return to original core */ |
| 1813 | si_setcoreidx(sih, origidx); |
| 1814 | } else |
| 1815 | clock = si_pmu_si_clock(sih, osh); |
| 1816 | |
| 1817 | return clock; |
| 1818 | } |
| 1819 | |
| 1820 | /* query memory clock frequency */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1821 | uint32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh) |
| 1822 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1823 | chipcregs_t *cc; |
| 1824 | uint origidx; |
| 1825 | uint32 clock; |
| 1826 | |
| 1827 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 1828 | |
| 1829 | if ((sih->pmurev >= 5) && |
| 1830 | !((CHIPID(sih->chip) == BCM4329_CHIP_ID) || |
| 1831 | (CHIPID(sih->chip) == BCM4319_CHIP_ID) || |
| 1832 | (CHIPID(sih->chip) == BCM4330_CHIP_ID) || |
| 1833 | (CHIPID(sih->chip) == BCM4336_CHIP_ID) || |
| 1834 | (CHIPID(sih->chip) == BCM43236_CHIP_ID))) { |
| 1835 | uint pll; |
| 1836 | |
| 1837 | switch (CHIPID(sih->chip)) { |
| 1838 | case BCM5356_CHIP_ID: |
| 1839 | pll = PMU5356_MAINPLL_PLL0; |
| 1840 | break; |
| 1841 | case BCM5357_CHIP_ID: |
| 1842 | pll = PMU5357_MAINPLL_PLL0; |
| 1843 | break; |
| 1844 | default: |
| 1845 | pll = PMU4716_MAINPLL_PLL0; |
| 1846 | break; |
| 1847 | } |
| 1848 | |
| 1849 | /* Remember original core before switch to chipc */ |
| 1850 | origidx = si_coreidx(sih); |
| 1851 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1852 | ASSERT(cc != NULL); |
| 1853 | |
| 1854 | clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM); |
| 1855 | |
| 1856 | /* Return to original core */ |
| 1857 | si_setcoreidx(sih, origidx); |
| 1858 | } else { |
| 1859 | clock = si_pmu_si_clock(sih, osh); |
| 1860 | } |
| 1861 | |
| 1862 | return clock; |
| 1863 | } |
| 1864 | |
| 1865 | /* Measure ILP clock frequency */ |
| 1866 | #define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */ |
| 1867 | |
| 1868 | static uint32 ilpcycles_per_sec = 0; |
| 1869 | |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1870 | uint32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh) |
| 1871 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1872 | if (ISSIM_ENAB(sih)) |
| 1873 | return ILP_CLOCK; |
| 1874 | |
| 1875 | if (ilpcycles_per_sec == 0) { |
| 1876 | uint32 start, end, delta; |
| 1877 | uint32 origidx = si_coreidx(sih); |
| 1878 | chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX); |
| 1879 | ASSERT(cc != NULL); |
| 1880 | start = R_REG(osh, &cc->pmutimer); |
| 1881 | OSL_DELAY(ILP_CALC_DUR * 1000); |
| 1882 | end = R_REG(osh, &cc->pmutimer); |
| 1883 | delta = end - start; |
| 1884 | ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR); |
| 1885 | si_setcoreidx(sih, origidx); |
| 1886 | } |
| 1887 | |
| 1888 | return ilpcycles_per_sec; |
| 1889 | } |
| 1890 | |
| 1891 | /* SDIO Pad drive strength to select value mappings */ |
| 1892 | typedef struct { |
| 1893 | uint8 strength; /* Pad Drive Strength in mA */ |
| 1894 | uint8 sel; /* Chip-specific select value */ |
| 1895 | } sdiod_drive_str_t; |
| 1896 | |
| 1897 | /* SDIO Drive Strength to sel value table for PMU Rev 1 */ |
| 1898 | static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab1)[] = |
| 1899 | { |
| 1900 | { |
| 1901 | 4, 0x2}, { |
| 1902 | 2, 0x3}, { |
| 1903 | 1, 0x0}, { |
| 1904 | 0, 0x0}}; |
| 1905 | |
| 1906 | /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */ |
| 1907 | static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab2)[] = |
| 1908 | { |
| 1909 | { |
| 1910 | 12, 0x7}, { |
| 1911 | 10, 0x6}, { |
| 1912 | 8, 0x5}, { |
| 1913 | 6, 0x4}, { |
| 1914 | 4, 0x2}, { |
| 1915 | 2, 0x1}, { |
| 1916 | 0, 0x0}}; |
| 1917 | |
| 1918 | /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */ |
| 1919 | static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab3)[] = |
| 1920 | { |
| 1921 | { |
| 1922 | 32, 0x7}, { |
| 1923 | 26, 0x6}, { |
| 1924 | 22, 0x5}, { |
| 1925 | 16, 0x4}, { |
| 1926 | 12, 0x3}, { |
| 1927 | 8, 0x2}, { |
| 1928 | 4, 0x1}, { |
| 1929 | 0, 0x0}}; |
| 1930 | |
| 1931 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
| 1932 | |
| 1933 | void |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 1934 | BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1935 | uint32 drivestrength) { |
| 1936 | chipcregs_t *cc; |
| 1937 | uint origidx, intr_val = 0; |
| 1938 | sdiod_drive_str_t *str_tab = NULL; |
| 1939 | uint32 str_mask = 0; |
| 1940 | uint32 str_shift = 0; |
| 1941 | #ifdef BCMDBG |
| 1942 | char chn[8]; |
| 1943 | #endif |
| 1944 | |
| 1945 | if (!(sih->cccaps & CC_CAP_PMU)) { |
| 1946 | return; |
| 1947 | } |
| 1948 | |
| 1949 | /* Remember original core before switch to chipc */ |
| 1950 | cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, |
| 1951 | &intr_val); |
| 1952 | |
| 1953 | switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) { |
| 1954 | case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8): |
| 1955 | str_tab = (sdiod_drive_str_t *) & sdiod_drive_strength_tab3; |
| 1956 | str_mask = 0x00003800; |
| 1957 | str_shift = 11; |
| 1958 | break; |
| 1959 | |
| 1960 | default: |
| 1961 | PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev)); |
| 1962 | |
| 1963 | break; |
| 1964 | } |
| 1965 | |
| 1966 | if (str_tab != NULL) { |
| 1967 | uint32 drivestrength_sel = 0; |
| 1968 | uint32 cc_data_temp; |
| 1969 | int i; |
| 1970 | |
| 1971 | for (i = 0; str_tab[i].strength != 0; i++) { |
| 1972 | if (drivestrength >= str_tab[i].strength) { |
| 1973 | drivestrength_sel = str_tab[i].sel; |
| 1974 | break; |
| 1975 | } |
| 1976 | } |
| 1977 | |
| 1978 | W_REG(osh, &cc->chipcontrol_addr, 1); |
| 1979 | cc_data_temp = R_REG(osh, &cc->chipcontrol_data); |
| 1980 | cc_data_temp &= ~str_mask; |
| 1981 | drivestrength_sel <<= str_shift; |
| 1982 | cc_data_temp |= drivestrength_sel; |
| 1983 | W_REG(osh, &cc->chipcontrol_data, cc_data_temp); |
| 1984 | |
| 1985 | PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n", |
| 1986 | drivestrength, cc_data_temp)); |
| 1987 | } |
| 1988 | |
| 1989 | /* Return to original core */ |
| 1990 | si_restore_core(sih, origidx, intr_val); |
| 1991 | } |
| 1992 | |
| 1993 | /* initialize PMU */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 1994 | void BCMATTACHFN(si_pmu_init) (si_t *sih, osl_t *osh) |
| 1995 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 1996 | chipcregs_t *cc; |
| 1997 | uint origidx; |
| 1998 | |
| 1999 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2000 | |
| 2001 | /* Remember original core before switch to chipc */ |
| 2002 | origidx = si_coreidx(sih); |
| 2003 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2004 | ASSERT(cc != NULL); |
| 2005 | |
| 2006 | if (sih->pmurev == 1) |
| 2007 | AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); |
| 2008 | else if (sih->pmurev >= 2) |
| 2009 | OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT); |
| 2010 | |
| 2011 | if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 2)) { |
| 2012 | /* Fix for 4329b0 bad LPOM state. */ |
| 2013 | W_REG(osh, &cc->regcontrol_addr, 2); |
| 2014 | OR_REG(osh, &cc->regcontrol_data, 0x100); |
| 2015 | |
| 2016 | W_REG(osh, &cc->regcontrol_addr, 3); |
| 2017 | OR_REG(osh, &cc->regcontrol_data, 0x4); |
| 2018 | } |
| 2019 | |
| 2020 | /* Return to original core */ |
| 2021 | si_setcoreidx(sih, origidx); |
| 2022 | } |
| 2023 | |
| 2024 | /* Return up time in ILP cycles for the given resource. */ |
| 2025 | static uint |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2026 | BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2027 | uint8 rsrc) { |
| 2028 | uint32 deps; |
| 2029 | uint up, i, dup, dmax; |
| 2030 | uint32 min_mask = 0, max_mask = 0; |
| 2031 | |
| 2032 | /* uptime of resource 'rsrc' */ |
| 2033 | W_REG(osh, &cc->res_table_sel, rsrc); |
| 2034 | up = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff; |
| 2035 | |
| 2036 | /* direct dependancies of resource 'rsrc' */ |
| 2037 | deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), FALSE); |
| 2038 | for (i = 0; i <= PMURES_MAX_RESNUM; i++) { |
| 2039 | if (!(deps & PMURES_BIT(i))) |
| 2040 | continue; |
| 2041 | deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), TRUE); |
| 2042 | } |
| 2043 | si_pmu_res_masks(sih, &min_mask, &max_mask); |
| 2044 | deps &= ~min_mask; |
| 2045 | |
| 2046 | /* max uptime of direct dependancies */ |
| 2047 | dmax = 0; |
| 2048 | for (i = 0; i <= PMURES_MAX_RESNUM; i++) { |
| 2049 | if (!(deps & PMURES_BIT(i))) |
| 2050 | continue; |
| 2051 | dup = si_pmu_res_uptime(sih, osh, cc, (uint8) i); |
| 2052 | if (dmax < dup) |
| 2053 | dmax = dup; |
| 2054 | } |
| 2055 | |
| 2056 | PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax)); |
| 2057 | |
| 2058 | return up + dmax + PMURES_UP_TRANSITION; |
| 2059 | } |
| 2060 | |
| 2061 | /* Return dependancies (direct or all/indirect) for the given resources */ |
| 2062 | static uint32 |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2063 | si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2064 | bool all) |
| 2065 | { |
| 2066 | uint32 deps = 0; |
| 2067 | uint32 i; |
| 2068 | |
| 2069 | for (i = 0; i <= PMURES_MAX_RESNUM; i++) { |
| 2070 | if (!(rsrcs & PMURES_BIT(i))) |
| 2071 | continue; |
| 2072 | W_REG(osh, &cc->res_table_sel, i); |
| 2073 | deps |= R_REG(osh, &cc->res_dep_mask); |
| 2074 | } |
| 2075 | |
| 2076 | return !all ? deps : (deps |
| 2077 | ? (deps | |
| 2078 | si_pmu_res_deps(sih, osh, cc, deps, |
| 2079 | TRUE)) : 0); |
| 2080 | } |
| 2081 | |
| 2082 | /* power up/down OTP through PMU resources */ |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2083 | void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2084 | { |
| 2085 | chipcregs_t *cc; |
| 2086 | uint origidx; |
| 2087 | uint32 rsrcs = 0; /* rsrcs to turn on/off OTP power */ |
| 2088 | |
| 2089 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2090 | |
| 2091 | /* Don't do anything if OTP is disabled */ |
| 2092 | if (si_is_otp_disabled(sih)) { |
| 2093 | PMU_MSG(("si_pmu_otp_power: OTP is disabled\n")); |
| 2094 | return; |
| 2095 | } |
| 2096 | |
| 2097 | /* Remember original core before switch to chipc */ |
| 2098 | origidx = si_coreidx(sih); |
| 2099 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2100 | ASSERT(cc != NULL); |
| 2101 | |
| 2102 | switch (CHIPID(sih->chip)) { |
| 2103 | case BCM4329_CHIP_ID: |
| 2104 | rsrcs = PMURES_BIT(RES4329_OTP_PU); |
| 2105 | break; |
| 2106 | case BCM4319_CHIP_ID: |
| 2107 | rsrcs = PMURES_BIT(RES4319_OTP_PU); |
| 2108 | break; |
| 2109 | case BCM4336_CHIP_ID: |
| 2110 | rsrcs = PMURES_BIT(RES4336_OTP_PU); |
| 2111 | break; |
| 2112 | case BCM4330_CHIP_ID: |
| 2113 | rsrcs = PMURES_BIT(RES4330_OTP_PU); |
| 2114 | break; |
| 2115 | default: |
| 2116 | break; |
| 2117 | } |
| 2118 | |
| 2119 | if (rsrcs != 0) { |
| 2120 | uint32 otps; |
| 2121 | |
| 2122 | /* Figure out the dependancies (exclude min_res_mask) */ |
| 2123 | uint32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE); |
| 2124 | uint32 min_mask = 0, max_mask = 0; |
| 2125 | si_pmu_res_masks(sih, &min_mask, &max_mask); |
| 2126 | deps &= ~min_mask; |
| 2127 | /* Turn on/off the power */ |
| 2128 | if (on) { |
| 2129 | PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", |
| 2130 | rsrcs | deps)); |
| 2131 | OR_REG(osh, &cc->min_res_mask, (rsrcs | deps)); |
| 2132 | SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs), |
| 2133 | PMU_MAX_TRANSITION_DLY); |
| 2134 | ASSERT(R_REG(osh, &cc->res_state) & rsrcs); |
| 2135 | } else { |
| 2136 | PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", |
| 2137 | rsrcs | deps)); |
| 2138 | AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps)); |
| 2139 | } |
| 2140 | |
| 2141 | SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) != |
| 2142 | (on ? OTPS_READY : 0)), 100); |
| 2143 | ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0)); |
| 2144 | if ((otps & OTPS_READY) != (on ? OTPS_READY : 0)) |
| 2145 | PMU_MSG(("OTP ready bit not %s after wait\n", |
| 2146 | (on ? "ON" : "OFF"))); |
| 2147 | } |
| 2148 | |
| 2149 | /* Return to original core */ |
| 2150 | si_setcoreidx(sih, origidx); |
| 2151 | } |
| 2152 | |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2153 | void si_pmu_rcal(si_t *sih, osl_t *osh) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2154 | { |
| 2155 | chipcregs_t *cc; |
| 2156 | uint origidx; |
| 2157 | |
| 2158 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2159 | |
| 2160 | /* Remember original core before switch to chipc */ |
| 2161 | origidx = si_coreidx(sih); |
| 2162 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2163 | ASSERT(cc != NULL); |
| 2164 | |
| 2165 | switch (CHIPID(sih->chip)) { |
| 2166 | case BCM4329_CHIP_ID:{ |
| 2167 | uint8 rcal_code; |
| 2168 | uint32 val; |
| 2169 | |
| 2170 | /* Kick RCal */ |
| 2171 | W_REG(osh, &cc->chipcontrol_addr, 1); |
| 2172 | |
| 2173 | /* Power Down RCAL Block */ |
| 2174 | AND_REG(osh, &cc->chipcontrol_data, ~0x04); |
| 2175 | |
| 2176 | /* Power Up RCAL block */ |
| 2177 | OR_REG(osh, &cc->chipcontrol_data, 0x04); |
| 2178 | |
| 2179 | /* Wait for completion */ |
| 2180 | SPINWAIT(0 == (R_REG(osh, &cc->chipstatus) & 0x08), |
| 2181 | 10 * 1000 * 1000); |
| 2182 | ASSERT(R_REG(osh, &cc->chipstatus) & 0x08); |
| 2183 | |
| 2184 | /* Drop the LSB to convert from 5 bit code to 4 bit code */ |
| 2185 | rcal_code = |
| 2186 | (uint8) (R_REG(osh, &cc->chipstatus) >> 5) & 0x0f; |
| 2187 | |
| 2188 | PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n", |
| 2189 | R_REG(osh, &cc->chipstatus), rcal_code)); |
| 2190 | |
| 2191 | /* Write RCal code into pmu_vreg_ctrl[32:29] */ |
| 2192 | W_REG(osh, &cc->regcontrol_addr, 0); |
| 2193 | val = |
| 2194 | R_REG(osh, |
| 2195 | &cc-> |
| 2196 | regcontrol_data) & ~((uint32) 0x07 << 29); |
| 2197 | val |= (uint32) (rcal_code & 0x07) << 29; |
| 2198 | W_REG(osh, &cc->regcontrol_data, val); |
| 2199 | W_REG(osh, &cc->regcontrol_addr, 1); |
| 2200 | val = R_REG(osh, &cc->regcontrol_data) & ~(uint32) 0x01; |
| 2201 | val |= (uint32) ((rcal_code >> 3) & 0x01); |
| 2202 | W_REG(osh, &cc->regcontrol_data, val); |
| 2203 | |
| 2204 | /* Write RCal code into pmu_chip_ctrl[33:30] */ |
| 2205 | W_REG(osh, &cc->chipcontrol_addr, 0); |
| 2206 | val = |
| 2207 | R_REG(osh, |
| 2208 | &cc-> |
| 2209 | chipcontrol_data) & ~((uint32) 0x03 << 30); |
| 2210 | val |= (uint32) (rcal_code & 0x03) << 30; |
| 2211 | W_REG(osh, &cc->chipcontrol_data, val); |
| 2212 | W_REG(osh, &cc->chipcontrol_addr, 1); |
| 2213 | val = |
| 2214 | R_REG(osh, &cc->chipcontrol_data) & ~(uint32) 0x03; |
| 2215 | val |= (uint32) ((rcal_code >> 2) & 0x03); |
| 2216 | W_REG(osh, &cc->chipcontrol_data, val); |
| 2217 | |
| 2218 | /* Set override in pmu_chip_ctrl[29] */ |
| 2219 | W_REG(osh, &cc->chipcontrol_addr, 0); |
| 2220 | OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29)); |
| 2221 | |
| 2222 | /* Power off RCal block */ |
| 2223 | W_REG(osh, &cc->chipcontrol_addr, 1); |
| 2224 | AND_REG(osh, &cc->chipcontrol_data, ~0x04); |
| 2225 | |
| 2226 | break; |
| 2227 | } |
| 2228 | default: |
| 2229 | break; |
| 2230 | } |
| 2231 | |
| 2232 | /* Return to original core */ |
| 2233 | si_setcoreidx(sih, origidx); |
| 2234 | } |
| 2235 | |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2236 | void si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2237 | { |
| 2238 | chipcregs_t *cc; |
| 2239 | uint origidx, intr_val; |
| 2240 | uint32 tmp = 0; |
| 2241 | |
| 2242 | /* Remember original core before switch to chipc */ |
| 2243 | cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, |
| 2244 | &intr_val); |
| 2245 | ASSERT(cc != NULL); |
| 2246 | |
| 2247 | /* force the HT off */ |
| 2248 | if (CHIPID(sih->chip) == BCM4336_CHIP_ID) { |
| 2249 | tmp = R_REG(osh, &cc->max_res_mask); |
| 2250 | tmp &= ~RES4336_HT_AVAIL; |
| 2251 | W_REG(osh, &cc->max_res_mask, tmp); |
| 2252 | /* wait for the ht to really go away */ |
| 2253 | SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0), |
| 2254 | 10000); |
| 2255 | ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0); |
| 2256 | } |
| 2257 | |
| 2258 | /* update the pll changes */ |
| 2259 | si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid); |
| 2260 | |
| 2261 | /* enable HT back on */ |
| 2262 | if (CHIPID(sih->chip) == BCM4336_CHIP_ID) { |
| 2263 | tmp = R_REG(osh, &cc->max_res_mask); |
| 2264 | tmp |= RES4336_HT_AVAIL; |
| 2265 | W_REG(osh, &cc->max_res_mask, tmp); |
| 2266 | } |
| 2267 | |
| 2268 | /* Return to original core */ |
| 2269 | si_restore_core(sih, origidx, intr_val); |
| 2270 | } |
| 2271 | |
| 2272 | static void |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2273 | si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2274 | uint8 spuravoid) |
| 2275 | { |
| 2276 | uint32 tmp = 0; |
| 2277 | uint8 phypll_offset = 0; |
| 2278 | uint8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 }; |
| 2279 | uint8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc }; |
| 2280 | |
| 2281 | switch (CHIPID(sih->chip)) { |
| 2282 | case BCM5357_CHIP_ID: |
| 2283 | case BCM43235_CHIP_ID: |
| 2284 | case BCM43236_CHIP_ID: |
| 2285 | case BCM43238_CHIP_ID: |
| 2286 | |
| 2287 | /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */ |
| 2288 | phypll_offset = (CHIPID(sih->chip) == BCM5357_CHIP_ID) ? 6 : 0; |
| 2289 | |
| 2290 | /* RMW only the P1 divider */ |
| 2291 | W_REG(osh, &cc->pllcontrol_addr, |
| 2292 | PMU1_PLL0_PLLCTL0 + phypll_offset); |
| 2293 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 2294 | tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK)); |
| 2295 | tmp |= |
| 2296 | (bcm5357_bcm43236_p1div[spuravoid] << |
| 2297 | PMU1_PLL0_PC0_P1DIV_SHIFT); |
| 2298 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 2299 | |
| 2300 | /* RMW only the int feedback divider */ |
| 2301 | W_REG(osh, &cc->pllcontrol_addr, |
| 2302 | PMU1_PLL0_PLLCTL2 + phypll_offset); |
| 2303 | tmp = R_REG(osh, &cc->pllcontrol_data); |
| 2304 | tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK); |
| 2305 | tmp |= |
| 2306 | (bcm5357_bcm43236_ndiv[spuravoid]) << |
| 2307 | PMU1_PLL0_PC2_NDIV_INT_SHIFT; |
| 2308 | W_REG(osh, &cc->pllcontrol_data, tmp); |
| 2309 | |
| 2310 | tmp = 1 << 10; |
| 2311 | break; |
| 2312 | |
| 2313 | case BCM4331_CHIP_ID: |
| 2314 | if (spuravoid == 2) { |
| 2315 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2316 | W_REG(osh, &cc->pllcontrol_data, 0x11500014); |
| 2317 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2318 | W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08); |
| 2319 | } else if (spuravoid == 1) { |
| 2320 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2321 | W_REG(osh, &cc->pllcontrol_data, 0x11500014); |
| 2322 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2323 | W_REG(osh, &cc->pllcontrol_data, 0x0F600a08); |
| 2324 | } else { |
| 2325 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2326 | W_REG(osh, &cc->pllcontrol_data, 0x11100014); |
| 2327 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2328 | W_REG(osh, &cc->pllcontrol_data, 0x03000a08); |
| 2329 | } |
| 2330 | tmp = 1 << 10; |
| 2331 | break; |
| 2332 | |
| 2333 | case BCM43224_CHIP_ID: |
| 2334 | case BCM43225_CHIP_ID: |
| 2335 | case BCM43421_CHIP_ID: |
| 2336 | case BCM6362_CHIP_ID: |
| 2337 | if (spuravoid == 1) { |
| 2338 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2339 | W_REG(osh, &cc->pllcontrol_data, 0x11500010); |
| 2340 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2341 | W_REG(osh, &cc->pllcontrol_data, 0x000C0C06); |
| 2342 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2343 | W_REG(osh, &cc->pllcontrol_data, 0x0F600a08); |
| 2344 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2345 | W_REG(osh, &cc->pllcontrol_data, 0x00000000); |
| 2346 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2347 | W_REG(osh, &cc->pllcontrol_data, 0x2001E920); |
| 2348 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2349 | W_REG(osh, &cc->pllcontrol_data, 0x88888815); |
| 2350 | } else { |
| 2351 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2352 | W_REG(osh, &cc->pllcontrol_data, 0x11100010); |
| 2353 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2354 | W_REG(osh, &cc->pllcontrol_data, 0x000c0c06); |
| 2355 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2356 | W_REG(osh, &cc->pllcontrol_data, 0x03000a08); |
| 2357 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2358 | W_REG(osh, &cc->pllcontrol_data, 0x00000000); |
| 2359 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2360 | W_REG(osh, &cc->pllcontrol_data, 0x200005c0); |
| 2361 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2362 | W_REG(osh, &cc->pllcontrol_data, 0x88888815); |
| 2363 | } |
| 2364 | tmp = 1 << 10; |
| 2365 | break; |
| 2366 | |
| 2367 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2368 | W_REG(osh, &cc->pllcontrol_data, 0x11100008); |
| 2369 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2370 | W_REG(osh, &cc->pllcontrol_data, 0x0c000c06); |
| 2371 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2372 | W_REG(osh, &cc->pllcontrol_data, 0x03000a08); |
| 2373 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2374 | W_REG(osh, &cc->pllcontrol_data, 0x00000000); |
| 2375 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2376 | W_REG(osh, &cc->pllcontrol_data, 0x200005c0); |
| 2377 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2378 | W_REG(osh, &cc->pllcontrol_data, 0x88888855); |
| 2379 | |
| 2380 | tmp = 1 << 10; |
| 2381 | break; |
| 2382 | |
| 2383 | case BCM4716_CHIP_ID: |
| 2384 | case BCM4748_CHIP_ID: |
| 2385 | case BCM47162_CHIP_ID: |
| 2386 | if (spuravoid == 1) { |
| 2387 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2388 | W_REG(osh, &cc->pllcontrol_data, 0x11500060); |
| 2389 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2390 | W_REG(osh, &cc->pllcontrol_data, 0x080C0C06); |
| 2391 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2392 | W_REG(osh, &cc->pllcontrol_data, 0x0F600000); |
| 2393 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2394 | W_REG(osh, &cc->pllcontrol_data, 0x00000000); |
| 2395 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2396 | W_REG(osh, &cc->pllcontrol_data, 0x2001E924); |
| 2397 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2398 | W_REG(osh, &cc->pllcontrol_data, 0x88888815); |
| 2399 | } else { |
| 2400 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2401 | W_REG(osh, &cc->pllcontrol_data, 0x11100060); |
| 2402 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2403 | W_REG(osh, &cc->pllcontrol_data, 0x080c0c06); |
| 2404 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2405 | W_REG(osh, &cc->pllcontrol_data, 0x03000000); |
| 2406 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2407 | W_REG(osh, &cc->pllcontrol_data, 0x00000000); |
| 2408 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2409 | W_REG(osh, &cc->pllcontrol_data, 0x200005c0); |
| 2410 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2411 | W_REG(osh, &cc->pllcontrol_data, 0x88888815); |
| 2412 | } |
| 2413 | |
| 2414 | tmp = 3 << 9; |
| 2415 | break; |
| 2416 | |
| 2417 | case BCM4319_CHIP_ID: |
| 2418 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2419 | W_REG(osh, &cc->pllcontrol_data, 0x11100070); |
| 2420 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2421 | W_REG(osh, &cc->pllcontrol_data, 0x1014140a); |
| 2422 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2423 | W_REG(osh, &cc->pllcontrol_data, 0x88888854); |
| 2424 | |
| 2425 | if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */ |
| 2426 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2427 | W_REG(osh, &cc->pllcontrol_data, 0x05201828); |
| 2428 | } else { /* enable 40/80/160Mhz clock mode */ |
| 2429 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2430 | W_REG(osh, &cc->pllcontrol_data, 0x05001828); |
| 2431 | } |
| 2432 | break; |
| 2433 | case BCM4336_CHIP_ID: |
| 2434 | /* Looks like these are only for default xtal freq 26MHz */ |
| 2435 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); |
| 2436 | W_REG(osh, &cc->pllcontrol_data, 0x02100020); |
| 2437 | |
| 2438 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); |
| 2439 | W_REG(osh, &cc->pllcontrol_data, 0x0C0C0C0C); |
| 2440 | |
| 2441 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); |
| 2442 | W_REG(osh, &cc->pllcontrol_data, 0x01240C0C); |
| 2443 | |
| 2444 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); |
| 2445 | W_REG(osh, &cc->pllcontrol_data, 0x202C2820); |
| 2446 | |
| 2447 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); |
| 2448 | W_REG(osh, &cc->pllcontrol_data, 0x88888825); |
| 2449 | |
| 2450 | W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); |
| 2451 | if (spuravoid == 1) { |
| 2452 | W_REG(osh, &cc->pllcontrol_data, 0x00EC4EC4); |
| 2453 | } else { |
| 2454 | W_REG(osh, &cc->pllcontrol_data, 0x00762762); |
| 2455 | } |
| 2456 | |
| 2457 | tmp = PCTL_PLL_PLLCTL_UPD; |
| 2458 | break; |
| 2459 | |
| 2460 | default: |
| 2461 | PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8))); |
| 2462 | break; |
| 2463 | } |
| 2464 | |
| 2465 | tmp |= R_REG(osh, &cc->pmucontrol); |
| 2466 | W_REG(osh, &cc->pmucontrol, tmp); |
| 2467 | } |
| 2468 | |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2469 | bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2470 | { |
| 2471 | uint idx; |
| 2472 | chipcregs_t *cc; |
| 2473 | bool st; |
| 2474 | |
| 2475 | /* Remember original core before switch to chipc */ |
| 2476 | idx = si_coreidx(sih); |
| 2477 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2478 | ASSERT(cc != NULL); |
| 2479 | |
| 2480 | switch (CHIPID(sih->chip)) { |
| 2481 | case BCM4329_CHIP_ID: |
| 2482 | st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU)) |
| 2483 | != 0; |
| 2484 | break; |
| 2485 | case BCM4319_CHIP_ID: |
| 2486 | st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU)) |
| 2487 | != 0; |
| 2488 | break; |
| 2489 | case BCM4336_CHIP_ID: |
| 2490 | st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU)) |
| 2491 | != 0; |
| 2492 | break; |
| 2493 | case BCM4330_CHIP_ID: |
| 2494 | st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU)) |
| 2495 | != 0; |
| 2496 | break; |
| 2497 | |
| 2498 | /* These chip doesn't use PMU bit to power up/down OTP. OTP always on. |
| 2499 | * Use OTP_INIT command to reset/refresh state. |
| 2500 | */ |
| 2501 | case BCM43224_CHIP_ID: |
| 2502 | case BCM43225_CHIP_ID: |
| 2503 | case BCM43421_CHIP_ID: |
| 2504 | case BCM43236_CHIP_ID: |
| 2505 | case BCM43235_CHIP_ID: |
| 2506 | case BCM43238_CHIP_ID: |
| 2507 | st = TRUE; |
| 2508 | break; |
| 2509 | default: |
| 2510 | st = TRUE; |
| 2511 | break; |
| 2512 | } |
| 2513 | |
| 2514 | /* Return to original core */ |
| 2515 | si_setcoreidx(sih, idx); |
| 2516 | return st; |
| 2517 | } |
| 2518 | |
| 2519 | void |
| 2520 | #if defined(BCMDBG) |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2521 | si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2522 | #else |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2523 | BCMATTACHFN(si_pmu_sprom_enable) (si_t *sih, osl_t *osh, bool enable) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2524 | #endif |
| 2525 | { |
| 2526 | chipcregs_t *cc; |
| 2527 | uint origidx; |
| 2528 | |
| 2529 | /* Remember original core before switch to chipc */ |
| 2530 | origidx = si_coreidx(sih); |
| 2531 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2532 | ASSERT(cc != NULL); |
| 2533 | |
| 2534 | /* Return to original core */ |
| 2535 | si_setcoreidx(sih, origidx); |
| 2536 | } |
| 2537 | |
| 2538 | /* initialize PMU chip controls and other chip level stuff */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 2539 | void BCMATTACHFN(si_pmu_chip_init) (si_t *sih, osl_t *osh) |
| 2540 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2541 | uint origidx; |
| 2542 | |
| 2543 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2544 | |
| 2545 | #ifdef CHIPC_UART_ALWAYS_ON |
| 2546 | si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), |
| 2547 | CCS_FORCEALP, CCS_FORCEALP); |
| 2548 | #endif /* CHIPC_UART_ALWAYS_ON */ |
| 2549 | |
| 2550 | /* Gate off SPROM clock and chip select signals */ |
| 2551 | si_pmu_sprom_enable(sih, osh, FALSE); |
| 2552 | |
| 2553 | /* Remember original core */ |
| 2554 | origidx = si_coreidx(sih); |
| 2555 | |
| 2556 | /* Return to original core */ |
| 2557 | si_setcoreidx(sih, origidx); |
| 2558 | } |
| 2559 | |
| 2560 | /* initialize PMU switch/regulators */ |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 2561 | void BCMATTACHFN(si_pmu_swreg_init) (si_t *sih, osl_t *osh) |
| 2562 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2563 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2564 | |
| 2565 | switch (CHIPID(sih->chip)) { |
| 2566 | case BCM4336_CHIP_ID: |
| 2567 | /* Reduce CLDO PWM output voltage to 1.2V */ |
| 2568 | si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe); |
| 2569 | /* Reduce CLDO BURST output voltage to 1.2V */ |
| 2570 | si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, |
| 2571 | 0xe); |
| 2572 | /* Reduce LNLDO1 output voltage to 1.2V */ |
| 2573 | si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe); |
| 2574 | if (CHIPREV(sih->chiprev) == 0) |
| 2575 | si_pmu_regcontrol(sih, 2, 0x400000, 0x400000); |
| 2576 | break; |
| 2577 | |
| 2578 | case BCM4330_CHIP_ID: |
| 2579 | /* CBUCK Voltage is 1.8 by default and set that to 1.5 */ |
| 2580 | si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0); |
| 2581 | break; |
| 2582 | default: |
| 2583 | break; |
| 2584 | } |
| 2585 | } |
| 2586 | |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2587 | void si_pmu_radio_enable(si_t *sih, bool enable) |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2588 | { |
| 2589 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2590 | |
| 2591 | switch (CHIPID(sih->chip)) { |
| 2592 | case BCM4319_CHIP_ID: |
| 2593 | if (enable) |
| 2594 | si_write_wrapperreg(sih, AI_OOBSELOUTB74, |
| 2595 | (uint32) 0x868584); |
| 2596 | else |
| 2597 | si_write_wrapperreg(sih, AI_OOBSELOUTB74, |
| 2598 | (uint32) 0x060584); |
| 2599 | break; |
| 2600 | } |
| 2601 | } |
| 2602 | |
| 2603 | /* Wait for a particular clock level to be on the backplane */ |
| 2604 | uint32 |
Jason Cooper | 7cc4a4c | 2010-09-14 09:45:30 -0400 | [diff] [blame] | 2605 | si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk, |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2606 | uint32 delay) |
| 2607 | { |
| 2608 | chipcregs_t *cc; |
| 2609 | uint origidx; |
| 2610 | |
| 2611 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2612 | |
| 2613 | /* Remember original core before switch to chipc */ |
| 2614 | origidx = si_coreidx(sih); |
| 2615 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2616 | ASSERT(cc != NULL); |
| 2617 | |
| 2618 | if (delay) |
| 2619 | SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay); |
| 2620 | |
| 2621 | /* Return to original core */ |
| 2622 | si_setcoreidx(sih, origidx); |
| 2623 | |
Jason Cooper | 90ea229 | 2010-09-14 09:45:32 -0400 | [diff] [blame] | 2624 | return R_REG(osh, &cc->pmustatus) & clk; |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2625 | } |
| 2626 | |
| 2627 | /* |
| 2628 | * Measures the ALP clock frequency in KHz. Returns 0 if not possible. |
| 2629 | * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal. |
| 2630 | */ |
| 2631 | |
| 2632 | #define EXT_ILP_HZ 32768 |
| 2633 | |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 2634 | uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh) |
| 2635 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2636 | chipcregs_t *cc; |
| 2637 | uint origidx; |
| 2638 | uint32 alp_khz; |
| 2639 | |
| 2640 | if (sih->pmurev < 10) |
| 2641 | return 0; |
| 2642 | |
| 2643 | ASSERT(sih->cccaps & CC_CAP_PMU); |
| 2644 | |
| 2645 | /* Remember original core before switch to chipc */ |
| 2646 | origidx = si_coreidx(sih); |
| 2647 | cc = si_setcoreidx(sih, SI_CC_IDX); |
| 2648 | ASSERT(cc != NULL); |
| 2649 | |
| 2650 | if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) { |
| 2651 | uint32 ilp_ctr, alp_hz; |
| 2652 | |
| 2653 | /* Enable the reg to measure the freq, in case disabled before */ |
| 2654 | W_REG(osh, &cc->pmu_xtalfreq, |
| 2655 | 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT); |
| 2656 | |
| 2657 | /* Delay for well over 4 ILP clocks */ |
| 2658 | OSL_DELAY(1000); |
| 2659 | |
| 2660 | /* Read the latched number of ALP ticks per 4 ILP ticks */ |
| 2661 | ilp_ctr = |
| 2662 | R_REG(osh, |
| 2663 | &cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK; |
| 2664 | |
| 2665 | /* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */ |
| 2666 | W_REG(osh, &cc->pmu_xtalfreq, 0); |
| 2667 | |
| 2668 | /* Calculate ALP frequency */ |
| 2669 | alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4; |
| 2670 | |
| 2671 | /* Round to nearest 100KHz, and at the same time convert to KHz */ |
| 2672 | alp_khz = (alp_hz + 50000) / 100000 * 100; |
| 2673 | } else |
| 2674 | alp_khz = 0; |
| 2675 | |
| 2676 | /* Return to original core */ |
| 2677 | si_setcoreidx(sih, origidx); |
| 2678 | |
| 2679 | return alp_khz; |
| 2680 | } |
| 2681 | |
Jason Cooper | a2627bc | 2010-09-14 09:45:31 -0400 | [diff] [blame] | 2682 | static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih) |
| 2683 | { |
Henry Ptasinski | a9533e7 | 2010-09-08 21:04:42 -0700 | [diff] [blame] | 2684 | uint32 FVCO = si_pmu1_pllfvco0(sih) / 1000; |
| 2685 | uint32 m1div, m2div, m3div, m4div, m5div, m6div; |
| 2686 | uint32 pllc1, pllc2; |
| 2687 | |
| 2688 | m2div = m3div = m4div = m6div = FVCO / 80; |
| 2689 | m5div = FVCO / 160; |
| 2690 | |
| 2691 | if (CST4330_CHIPMODE_SDIOD(sih->chipst)) |
| 2692 | m1div = FVCO / 80; |
| 2693 | else |
| 2694 | m1div = FVCO / 90; |
| 2695 | pllc1 = |
| 2696 | (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div << |
| 2697 | PMU1_PLL0_PC1_M2DIV_SHIFT) | |
| 2698 | (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div << |
| 2699 | PMU1_PLL0_PC1_M4DIV_SHIFT); |
| 2700 | si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1); |
| 2701 | |
| 2702 | pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0); |
| 2703 | pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK); |
| 2704 | pllc2 |= |
| 2705 | ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) | |
| 2706 | (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT)); |
| 2707 | si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2); |
| 2708 | } |