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Sangbeom Kimf8bfff82011-03-12 08:02:07 +09001/* linux/arch/arm/plat-s5p/s5p-time.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Common hr-timer support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
Sangbeom Kimf8bfff82011-03-12 08:02:07 +090013#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/platform_device.h>
19
20#include <asm/smp_twd.h>
21#include <asm/mach/time.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/map.h>
24#include <asm/sched_clock.h>
25
26#include <mach/map.h>
27#include <plat/devs.h>
28#include <plat/regs-timer.h>
29#include <plat/s5p-time.h>
30
31static struct clk *tin_event;
32static struct clk *tin_source;
33static struct clk *tdiv_event;
34static struct clk *tdiv_source;
35static struct clk *timerclk;
36static struct s5p_timer_source timer_source;
37static unsigned long clock_count_per_tick;
38static void s5p_timer_resume(void);
39
40static void s5p_time_stop(enum s5p_timer_mode mode)
41{
42 unsigned long tcon;
43
44 tcon = __raw_readl(S3C2410_TCON);
45
46 switch (mode) {
47 case S5P_PWM0:
48 tcon &= ~S3C2410_TCON_T0START;
49 break;
50
51 case S5P_PWM1:
52 tcon &= ~S3C2410_TCON_T1START;
53 break;
54
55 case S5P_PWM2:
56 tcon &= ~S3C2410_TCON_T2START;
57 break;
58
59 case S5P_PWM3:
60 tcon &= ~S3C2410_TCON_T3START;
61 break;
62
63 case S5P_PWM4:
64 tcon &= ~S3C2410_TCON_T4START;
65 break;
66
67 default:
68 printk(KERN_ERR "Invalid Timer %d\n", mode);
69 break;
70 }
71 __raw_writel(tcon, S3C2410_TCON);
72}
73
74static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
75{
76 unsigned long tcon;
77
78 tcon = __raw_readl(S3C2410_TCON);
79
80 tcnt--;
81
82 switch (mode) {
83 case S5P_PWM0:
84 tcon &= ~(0x0f << 0);
85 tcon |= S3C2410_TCON_T0MANUALUPD;
86 break;
87
88 case S5P_PWM1:
89 tcon &= ~(0x0f << 8);
90 tcon |= S3C2410_TCON_T1MANUALUPD;
91 break;
92
93 case S5P_PWM2:
94 tcon &= ~(0x0f << 12);
95 tcon |= S3C2410_TCON_T2MANUALUPD;
96 break;
97
98 case S5P_PWM3:
99 tcon &= ~(0x0f << 16);
100 tcon |= S3C2410_TCON_T3MANUALUPD;
101 break;
102
103 case S5P_PWM4:
104 tcon &= ~(0x07 << 20);
105 tcon |= S3C2410_TCON_T4MANUALUPD;
106 break;
107
108 default:
109 printk(KERN_ERR "Invalid Timer %d\n", mode);
110 break;
111 }
112
113 __raw_writel(tcnt, S3C2410_TCNTB(mode));
114 __raw_writel(tcnt, S3C2410_TCMPB(mode));
115 __raw_writel(tcon, S3C2410_TCON);
116}
117
118static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
119{
120 unsigned long tcon;
121
122 tcon = __raw_readl(S3C2410_TCON);
123
124 switch (mode) {
125 case S5P_PWM0:
126 tcon |= S3C2410_TCON_T0START;
127 tcon &= ~S3C2410_TCON_T0MANUALUPD;
128
129 if (periodic)
130 tcon |= S3C2410_TCON_T0RELOAD;
131 else
132 tcon &= ~S3C2410_TCON_T0RELOAD;
133 break;
134
135 case S5P_PWM1:
136 tcon |= S3C2410_TCON_T1START;
137 tcon &= ~S3C2410_TCON_T1MANUALUPD;
138
139 if (periodic)
140 tcon |= S3C2410_TCON_T1RELOAD;
141 else
142 tcon &= ~S3C2410_TCON_T1RELOAD;
143 break;
144
145 case S5P_PWM2:
146 tcon |= S3C2410_TCON_T2START;
147 tcon &= ~S3C2410_TCON_T2MANUALUPD;
148
149 if (periodic)
150 tcon |= S3C2410_TCON_T2RELOAD;
151 else
152 tcon &= ~S3C2410_TCON_T2RELOAD;
153 break;
154
155 case S5P_PWM3:
156 tcon |= S3C2410_TCON_T3START;
157 tcon &= ~S3C2410_TCON_T3MANUALUPD;
158
159 if (periodic)
160 tcon |= S3C2410_TCON_T3RELOAD;
161 else
162 tcon &= ~S3C2410_TCON_T3RELOAD;
163 break;
164
165 case S5P_PWM4:
166 tcon |= S3C2410_TCON_T4START;
167 tcon &= ~S3C2410_TCON_T4MANUALUPD;
168
169 if (periodic)
170 tcon |= S3C2410_TCON_T4RELOAD;
171 else
172 tcon &= ~S3C2410_TCON_T4RELOAD;
173 break;
174
175 default:
176 printk(KERN_ERR "Invalid Timer %d\n", mode);
177 break;
178 }
179 __raw_writel(tcon, S3C2410_TCON);
180}
181
182static int s5p_set_next_event(unsigned long cycles,
183 struct clock_event_device *evt)
184{
185 s5p_time_setup(timer_source.event_id, cycles);
186 s5p_time_start(timer_source.event_id, NON_PERIODIC);
187
188 return 0;
189}
190
191static void s5p_set_mode(enum clock_event_mode mode,
192 struct clock_event_device *evt)
193{
194 s5p_time_stop(timer_source.event_id);
195
196 switch (mode) {
197 case CLOCK_EVT_MODE_PERIODIC:
198 s5p_time_setup(timer_source.event_id, clock_count_per_tick);
199 s5p_time_start(timer_source.event_id, PERIODIC);
200 break;
201
202 case CLOCK_EVT_MODE_ONESHOT:
203 break;
204
205 case CLOCK_EVT_MODE_UNUSED:
206 case CLOCK_EVT_MODE_SHUTDOWN:
207 break;
208
209 case CLOCK_EVT_MODE_RESUME:
210 s5p_timer_resume();
211 break;
212 }
213}
214
215static void s5p_timer_resume(void)
216{
217 /* event timer restart */
218 s5p_time_setup(timer_source.event_id, clock_count_per_tick);
219 s5p_time_start(timer_source.event_id, PERIODIC);
220
221 /* source timer restart */
222 s5p_time_setup(timer_source.source_id, TCNT_MAX);
223 s5p_time_start(timer_source.source_id, PERIODIC);
224}
225
226void __init s5p_set_timer_source(enum s5p_timer_mode event,
227 enum s5p_timer_mode source)
228{
229 s3c_device_timer[event].dev.bus = &platform_bus_type;
230 s3c_device_timer[source].dev.bus = &platform_bus_type;
231
232 timer_source.event_id = event;
233 timer_source.source_id = source;
234}
235
236static struct clock_event_device time_event_device = {
237 .name = "s5p_event_timer",
238 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
239 .rating = 200,
240 .set_next_event = s5p_set_next_event,
241 .set_mode = s5p_set_mode,
242};
243
244static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
245{
246 struct clock_event_device *evt = dev_id;
247
248 evt->event_handler(evt);
249
250 return IRQ_HANDLED;
251}
252
253static struct irqaction s5p_clock_event_irq = {
254 .name = "s5p_time_irq",
255 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
256 .handler = s5p_clock_event_isr,
257 .dev_id = &time_event_device,
258};
259
260static void __init s5p_clockevent_init(void)
261{
262 unsigned long pclk;
263 unsigned long clock_rate;
264 unsigned int irq_number;
265 struct clk *tscaler;
266
267 pclk = clk_get_rate(timerclk);
268
269 tscaler = clk_get_parent(tdiv_event);
270
271 clk_set_rate(tscaler, pclk / 2);
272 clk_set_rate(tdiv_event, pclk / 2);
273 clk_set_parent(tin_event, tdiv_event);
274
275 clock_rate = clk_get_rate(tin_event);
276 clock_count_per_tick = clock_rate / HZ;
277
278 clockevents_calc_mult_shift(&time_event_device,
279 clock_rate, S5PTIMER_MIN_RANGE);
280 time_event_device.max_delta_ns =
281 clockevent_delta2ns(-1, &time_event_device);
282 time_event_device.min_delta_ns =
283 clockevent_delta2ns(1, &time_event_device);
284
285 time_event_device.cpumask = cpumask_of(0);
286 clockevents_register_device(&time_event_device);
287
288 irq_number = timer_source.event_id + IRQ_TIMER0;
289 setup_irq(irq_number, &s5p_clock_event_irq);
290}
291
Russell Kingdf4c1442011-05-08 15:43:07 +0100292static void __iomem *s5p_timer_reg(void)
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900293{
294 unsigned long offset = 0;
295
296 switch (timer_source.source_id) {
297 case S5P_PWM0:
298 case S5P_PWM1:
299 case S5P_PWM2:
300 case S5P_PWM3:
301 offset = (timer_source.source_id * 0x0c) + 0x14;
302 break;
303
304 case S5P_PWM4:
305 offset = 0x40;
306 break;
307
308 default:
309 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
Russell Kingdf4c1442011-05-08 15:43:07 +0100310 return NULL;
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900311 }
312
Russell Kingdf4c1442011-05-08 15:43:07 +0100313 return S3C_TIMERREG(offset);
314}
315
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900316/*
317 * Override the global weak sched_clock symbol with this
318 * local implementation which uses the clocksource to get some
319 * better resolution when scheduling the kernel. We accept that
320 * this wraps around for now, since it is just a relative time
321 * stamp. (Inspired by U300 implementation.)
322 */
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100323static u32 notrace s5p_read_sched_clock(void)
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900324{
Russell Kingdf4c1442011-05-08 15:43:07 +0100325 void __iomem *reg = s5p_timer_reg();
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900326
Russell Kingdf4c1442011-05-08 15:43:07 +0100327 if (!reg)
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900328 return 0;
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900329
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100330 return ~__raw_readl(reg);
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900331}
332
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900333static void __init s5p_clocksource_init(void)
334{
335 unsigned long pclk;
336 unsigned long clock_rate;
337
338 pclk = clk_get_rate(timerclk);
339
340 clk_set_rate(tdiv_source, pclk / 2);
341 clk_set_parent(tin_source, tdiv_source);
342
343 clock_rate = clk_get_rate(tin_source);
344
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900345 s5p_time_setup(timer_source.source_id, TCNT_MAX);
346 s5p_time_start(timer_source.source_id, PERIODIC);
347
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100348 setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
Sangbeom Kim27ea7fd2011-06-23 21:43:58 +0900349
Chanwoo Choi0665ccc2011-07-18 15:07:14 +0900350 if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
351 clock_rate, 250, 32, clocksource_mmio_readl_down))
352 panic("s5p_clocksource_timer: can't register clocksource\n");
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900353}
354
355static void __init s5p_timer_resources(void)
356{
357
358 unsigned long event_id = timer_source.event_id;
359 unsigned long source_id = timer_source.source_id;
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900360 char devname[15];
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900361
362 timerclk = clk_get(NULL, "timers");
363 if (IS_ERR(timerclk))
364 panic("failed to get timers clock for timer");
365
366 clk_enable(timerclk);
367
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900368 sprintf(devname, "s3c24xx-pwm.%lu", event_id);
369 s3c_device_timer[event_id].id = event_id;
370 s3c_device_timer[event_id].dev.init_name = devname;
371
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900372 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
373 if (IS_ERR(tin_event))
374 panic("failed to get pwm-tin clock for event timer");
375
376 tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
377 if (IS_ERR(tdiv_event))
378 panic("failed to get pwm-tdiv clock for event timer");
379
380 clk_enable(tin_event);
381
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900382 sprintf(devname, "s3c24xx-pwm.%lu", source_id);
383 s3c_device_timer[source_id].id = source_id;
384 s3c_device_timer[source_id].dev.init_name = devname;
385
Sangbeom Kimf8bfff82011-03-12 08:02:07 +0900386 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
387 if (IS_ERR(tin_source))
388 panic("failed to get pwm-tin clock for source timer");
389
390 tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
391 if (IS_ERR(tdiv_source))
392 panic("failed to get pwm-tdiv clock for source timer");
393
394 clk_enable(tin_source);
395}
396
397static void __init s5p_timer_init(void)
398{
399 s5p_timer_resources();
400 s5p_clockevent_init();
401 s5p_clocksource_init();
402}
403
404struct sys_timer s5p_timer = {
405 .init = s5p_timer_init,
406};