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gerrit-public.fairphone.software / kernel / msm-4.9 / caa9eac5bcc835cfd98085fcd3944f44890d8a8f / . / arch / arm / boot / dts / tegra30-apalis.dtsi
blob: a5446cba9804d3c6c24f7c2207642820869ccaa8 [file] [log] [blame]
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200[diff] [blame]1#include "tegra30.dtsi"
2
3/*
4 * Toradex Apalis T30 Device Tree
5 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C
6 */
7/ {
8 model = "Toradex Apalis T30";
9 compatible = "toradex,apalis_t30", "nvidia,tegra30";
10
11 pcie-controller@00003000 {
Marcel Ziswilerb607b192014-06-25 22:10:01 +0200[diff] [blame]12 avdd-pexa-supply = <&vdd2_reg>;
13 vdd-pexa-supply = <&vdd2_reg>;
14 avdd-pexb-supply = <&vdd2_reg>;
15 vdd-pexb-supply = <&vdd2_reg>;
16 avdd-pex-pll-supply = <&vdd2_reg>;
17 avdd-plle-supply = <&ldo6_reg>;
18 vddio-pex-ctl-supply = <&sys_3v3_reg>;
19 hvdd-pex-supply = <&sys_3v3_reg>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200[diff] [blame]20
21 pci@1,0 {
22 nvidia,num-lanes = <4>;
23 };
24
25 pci@2,0 {
26 nvidia,num-lanes = <1>;
27 };
28
29 pci@3,0 {
30 nvidia,num-lanes = <1>;
31 };
32 };
33
34 host1x@50000000 {
35 hdmi@54280000 {
36 vdd-supply = <&sys_3v3_reg>;
37 pll-supply = <&vio_reg>;
38
39 nvidia,hpd-gpio =
40 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
41 nvidia,ddc-i2c-bus = <&hdmiddc>;
42 };
43 };
44
45 pinmux@70000868 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&state_default>;
48
49 state_default: pinmux {
50 /* Apalis BKL1_ON */
51 pv2 {
52 nvidia,pins = "pv2";
53 nvidia,function = "rsvd4";
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57
58 /* Apalis BKL1_PWM */
59 uart3_rts_n_pc0 {
60 nvidia,pins = "uart3_rts_n_pc0";
61 nvidia,function = "pwm0";
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 };
65 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
66 uart3_cts_n_pa1 {
67 nvidia,pins = "uart3_cts_n_pa1";
68 nvidia,function = "rsvd1";
69 nvidia,pull = <TEGRA_PIN_PULL_UP>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 };
72
73 /* Apalis CAN1 on SPI6 */
74 spi2_cs0_n_px3 {
75 nvidia,pins = "spi2_cs0_n_px3",
76 "spi2_miso_px1",
77 "spi2_mosi_px0",
78 "spi2_sck_px2";
79 nvidia,function = "spi6";
80 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
81 nvidia,tristate = <TEGRA_PIN_DISABLE>;
82 };
83 /* CAN_INT1 */
84 spi2_cs1_n_pw2 {
85 nvidia,pins = "spi2_cs1_n_pw2";
86 nvidia,function = "spi3";
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
90 };
91
92 /* Apalis CAN2 on SPI4 */
93 gmi_a16_pj7 {
94 nvidia,pins = "gmi_a16_pj7",
95 "gmi_a17_pb0",
96 "gmi_a18_pb1",
97 "gmi_a19_pk7";
98 nvidia,function = "spi4";
99 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
100 nvidia,tristate = <TEGRA_PIN_DISABLE>;
101 };
102 /* CAN_INT2 */
103 spi2_cs2_n_pw3 {
104 nvidia,pins = "spi2_cs2_n_pw3";
105 nvidia,function = "spi3";
106 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
108 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
109 };
110
111 /* Apalis I2C3 */
112 cam_i2c_scl_pbb1 {
113 nvidia,pins = "cam_i2c_scl_pbb1",
114 "cam_i2c_sda_pbb2";
115 nvidia,function = "i2c3";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
119 nvidia,lock = <TEGRA_PIN_DISABLE>;
120 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
121 };
122
123 /* Apalis MMC1 */
124 sdmmc3_clk_pa6 {
125 nvidia,pins = "sdmmc3_clk_pa6",
126 "sdmmc3_cmd_pa7";
127 nvidia,function = "sdmmc3";
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 };
131 sdmmc3_dat0_pb7 {
132 nvidia,pins = "sdmmc3_dat0_pb7",
133 "sdmmc3_dat1_pb6",
134 "sdmmc3_dat2_pb5",
135 "sdmmc3_dat3_pb4",
136 "sdmmc3_dat4_pd1",
137 "sdmmc3_dat5_pd0",
138 "sdmmc3_dat6_pd3",
139 "sdmmc3_dat7_pd4";
140 nvidia,function = "sdmmc3";
141 nvidia,pull = <TEGRA_PIN_PULL_UP>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 };
144 /* Apalis MMC1_CD# */
145 pv3 {
146 nvidia,pins = "pv3";
147 nvidia,function = "rsvd2";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
151 };
152
153 /* Apalis PWM1 */
154 gpio_pu6 {
155 nvidia,pins = "gpio_pu6";
156 nvidia,function = "pwm3";
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 };
160
161 /* Apalis PWM2 */
162 gpio_pu5 {
163 nvidia,pins = "gpio_pu5";
164 nvidia,function = "pwm2";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168
169 /* Apalis PWM3 */
170 gpio_pu4 {
171 nvidia,pins = "gpio_pu4";
172 nvidia,function = "pwm1";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 };
176
177 /* Apalis PWM4 */
178 gpio_pu3 {
179 nvidia,pins = "gpio_pu3";
180 nvidia,function = "pwm0";
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 };
184
185 /* Apalis RESET_MOCI# */
186 gmi_rst_n_pi4 {
187 nvidia,pins = "gmi_rst_n_pi4";
188 nvidia,function = "gmi";
189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 };
192
193 /* Apalis SD1 */
194 sdmmc1_clk_pz0 {
195 nvidia,pins = "sdmmc1_clk_pz0";
196 nvidia,function = "sdmmc1";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 };
200 sdmmc1_cmd_pz1 {
201 nvidia,pins = "sdmmc1_cmd_pz1",
202 "sdmmc1_dat0_py7",
203 "sdmmc1_dat1_py6",
204 "sdmmc1_dat2_py5",
205 "sdmmc1_dat3_py4";
206 nvidia,function = "sdmmc1";
207 nvidia,pull = <TEGRA_PIN_PULL_UP>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 };
210 /* Apalis SD1_CD# */
211 clk2_req_pcc5 {
212 nvidia,pins = "clk2_req_pcc5";
213 nvidia,function = "rsvd2";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 };
218
219 /* Apalis SPI1 */
220 spi1_sck_px5 {
221 nvidia,pins = "spi1_sck_px5",
222 "spi1_mosi_px4",
223 "spi1_miso_px7",
224 "spi1_cs0_n_px6";
225 nvidia,function = "spi1";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229
230 /* Apalis SPI2 */
231 lcd_sck_pz4 {
232 nvidia,pins = "lcd_sck_pz4",
233 "lcd_sdout_pn5",
234 "lcd_sdin_pz2",
235 "lcd_cs0_n_pn4";
236 nvidia,function = "spi5";
237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
239 };
240
241 /* Apalis UART1 */
242 ulpi_data0 {
243 nvidia,pins = "ulpi_data0_po1",
244 "ulpi_data1_po2",
245 "ulpi_data2_po3",
246 "ulpi_data3_po4",
247 "ulpi_data4_po5",
248 "ulpi_data5_po6",
249 "ulpi_data6_po7",
250 "ulpi_data7_po0";
251 nvidia,function = "uarta";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 };
255
256 /* Apalis UART2 */
257 ulpi_clk_py0 {
258 nvidia,pins = "ulpi_clk_py0",
259 "ulpi_dir_py1",
260 "ulpi_nxt_py2",
261 "ulpi_stp_py3";
262 nvidia,function = "uartd";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 };
266
267 /* Apalis UART3 */
268 uart2_rxd_pc3 {
269 nvidia,pins = "uart2_rxd_pc3",
270 "uart2_txd_pc2";
271 nvidia,function = "uartb";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 };
275
276 /* Apalis UART4 */
277 uart3_rxd_pw7 {
278 nvidia,pins = "uart3_rxd_pw7",
279 "uart3_txd_pw6";
280 nvidia,function = "uartc";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
283 };
284
285 /* Apalis USBO1_EN */
286 gen2_i2c_scl_pt5 {
287 nvidia,pins = "gen2_i2c_scl_pt5";
288 nvidia,function = "rsvd4";
289 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
290 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
291 nvidia,tristate = <TEGRA_PIN_DISABLE>;
292 };
293
294 /* Apalis USBO1_OC# */
295 gen2_i2c_sda_pt6 {
296 nvidia,pins = "gen2_i2c_sda_pt6";
297 nvidia,function = "rsvd4";
298 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 };
303
304 /* Apalis WAKE1_MICO */
305 pv1 {
306 nvidia,pins = "pv1";
307 nvidia,function = "rsvd1";
308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
311 };
312
313 /* eMMC (On-module) */
314 sdmmc4_clk_pcc4 {
315 nvidia,pins = "sdmmc4_clk_pcc4",
316 "sdmmc4_rst_n_pcc3";
317 nvidia,function = "sdmmc4";
318 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
319 nvidia,tristate = <TEGRA_PIN_DISABLE>;
320 };
321 sdmmc4_dat0_paa0 {
322 nvidia,pins = "sdmmc4_dat0_paa0",
323 "sdmmc4_dat1_paa1",
324 "sdmmc4_dat2_paa2",
325 "sdmmc4_dat3_paa3",
326 "sdmmc4_dat4_paa4",
327 "sdmmc4_dat5_paa5",
328 "sdmmc4_dat6_paa6",
329 "sdmmc4_dat7_paa7";
330 nvidia,function = "sdmmc4";
331 nvidia,pull = <TEGRA_PIN_PULL_UP>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 };
334
335 /* LVDS Transceiver Configuration */
336 pbb0 {
337 nvidia,pins = "pbb0",
338 "pbb7",
339 "pcc1",
340 "pcc2";
341 nvidia,function = "rsvd2";
342 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
343 nvidia,tristate = <TEGRA_PIN_DISABLE>;
344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
345 nvidia,lock = <TEGRA_PIN_DISABLE>;
346 };
347 pbb3 {
348 nvidia,pins = "pbb3",
349 "pbb4",
350 "pbb5",
351 "pbb6";
352 nvidia,function = "displayb";
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 nvidia,lock = <TEGRA_PIN_DISABLE>;
357 };
358
359 /* Power I2C (On-module) */
360 pwr_i2c_scl_pz6 {
361 nvidia,pins = "pwr_i2c_scl_pz6",
362 "pwr_i2c_sda_pz7";
363 nvidia,function = "i2cpwr";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
367 nvidia,lock = <TEGRA_PIN_DISABLE>;
368 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
369 };
370
371 /*
372 * THERMD_ALERT#, unlatched I2C address pin of LM95245
373 * temperature sensor therefore requires disabling for
374 * now
375 */
376 lcd_dc1_pd2 {
377 nvidia,pins = "lcd_dc1_pd2";
378 nvidia,function = "rsvd3";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382 };
383
384 /* TOUCH_PEN_INT# */
385 pv0 {
386 nvidia,pins = "pv0";
387 nvidia,function = "rsvd1";
388 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
389 nvidia,tristate = <TEGRA_PIN_DISABLE>;
390 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
391 };
392 };
393 };
394
395 hdmiddc: i2c@7000c700 {
396 clock-frequency = <100000>;
397 };
398
399 /*
400 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
401 * touch screen controller
402 */
403 i2c@7000d000 {
404 status = "okay";
405 clock-frequency = <100000>;
406
407 pmic: tps65911@2d {
408 compatible = "ti,tps65911";
409 reg = <0x2d>;
410
411 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
412 #interrupt-cells = <2>;
413 interrupt-controller;
414
415 ti,system-power-controller;
416
417 #gpio-cells = <2>;
418 gpio-controller;
419
420 vcc1-supply = <&sys_3v3_reg>;
421 vcc2-supply = <&sys_3v3_reg>;
422 vcc3-supply = <&vio_reg>;
423 vcc4-supply = <&sys_3v3_reg>;
424 vcc5-supply = <&sys_3v3_reg>;
425 vcc6-supply = <&vio_reg>;
Marcel Ziswilercaa9eac2014-08-22 13:25:10 -0600[diff] [blame^]426 vcc7-supply = <&charge_pump_5v0_reg>;
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200[diff] [blame]427 vccio-supply = <&sys_3v3_reg>;
428
429 regulators {
430 /* SW1: +V1.35_VDDIO_DDR */
431 vdd1_reg: vdd1 {
432 regulator-name = "vddio_ddr_1v35";
433 regulator-min-microvolt = <1350000>;
434 regulator-max-microvolt = <1350000>;
435 regulator-always-on;
436 };
437
438 /* SW2: +V1.05 */
439 vdd2_reg: vdd2 {
440 regulator-name =
441 "vdd_pexa,vdd_pexb,vdd_sata";
442 regulator-min-microvolt = <1050000>;
443 regulator-max-microvolt = <1050000>;
444 };
445
446 /* SW CTRL: +V1.0_VDD_CPU */
447 vddctrl_reg: vddctrl {
448 regulator-name = "vdd_cpu,vdd_sys";
449 regulator-min-microvolt = <1150000>;
450 regulator-max-microvolt = <1150000>;
451 regulator-always-on;
452 };
453
454 /* SWIO: +V1.8 */
455 vio_reg: vio {
456 regulator-name = "vdd_1v8_gen";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 regulator-always-on;
460 };
461
462 /* LDO1: unused */
463
464 /*
465 * EN_+V3.3 switching via FET:
466 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
467 * see also v3_3 fixed supply
468 */
469 ldo2_reg: ldo2 {
470 regulator-name = "en_3v3";
471 regulator-min-microvolt = <3300000>;
472 regulator-max-microvolt = <3300000>;
473 regulator-always-on;
474 };
475
476 /* +V1.2_CSI */
477 ldo3_reg: ldo3 {
478 regulator-name =
479 "avdd_dsi_csi,pwrdet_mipi";
480 regulator-min-microvolt = <1200000>;
481 regulator-max-microvolt = <1200000>;
482 };
483
484 /* +V1.2_VDD_RTC */
485 ldo4_reg: ldo4 {
486 regulator-name = "vdd_rtc";
487 regulator-min-microvolt = <1200000>;
488 regulator-max-microvolt = <1200000>;
489 regulator-always-on;
490 };
491
492 /*
493 * +V2.8_AVDD_VDAC:
494 * only required for analog RGB
495 */
496 ldo5_reg: ldo5 {
497 regulator-name = "avdd_vdac";
498 regulator-min-microvolt = <2800000>;
499 regulator-max-microvolt = <2800000>;
500 regulator-always-on;
501 };
502
503 /*
504 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
505 * but LDO6 can't set voltage in 50mV
506 * granularity
507 */
508 ldo6_reg: ldo6 {
509 regulator-name = "avdd_plle";
510 regulator-min-microvolt = <1100000>;
511 regulator-max-microvolt = <1100000>;
512 };
513
514 /* +V1.2_AVDD_PLL */
515 ldo7_reg: ldo7 {
516 regulator-name = "avdd_pll";
517 regulator-min-microvolt = <1200000>;
518 regulator-max-microvolt = <1200000>;
519 regulator-always-on;
520 };
521
522 /* +V1.0_VDD_DDR_HS */
523 ldo8_reg: ldo8 {
524 regulator-name = "vdd_ddr_hs";
525 regulator-min-microvolt = <1000000>;
526 regulator-max-microvolt = <1000000>;
527 regulator-always-on;
528 };
529 };
530 };
531
532 /* STMPE811 touch screen controller */
533 stmpe811@41 {
534 compatible = "st,stmpe811";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0x41>;
538 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
539 interrupt-parent = <&gpio>;
540 interrupt-controller;
541 id = <0>;
542 blocks = <0x5>;
543 irq-trigger = <0x1>;
544
545 stmpe_touchscreen {
546 compatible = "st,stmpe-ts";
547 reg = <0>;
548 /* 3.25 MHz ADC clock speed */
549 st,adc-freq = <1>;
550 /* 8 sample average control */
551 st,ave-ctrl = <3>;
552 /* 7 length fractional part in z */
553 st,fraction-z = <7>;
554 /*
555 * 50 mA typical 80 mA max touchscreen drivers
556 * current limit value
557 */
558 st,i-drive = <1>;
559 /* 12-bit ADC */
560 st,mod-12b = <1>;
561 /* internal ADC reference */
562 st,ref-sel = <0>;
563 /* ADC converstion time: 80 clocks */
564 st,sample-time = <4>;
565 /* 1 ms panel driver settling time */
566 st,settling = <3>;
567 /* 5 ms touch detect interrupt delay */
568 st,touch-det-delay = <5>;
569 };
570 };
571
572 /*
573 * LM95245 temperature sensor
574 * Note: OVERT_N directly connected to PMIC PWRDN
575 */
576 temp-sensor@4c {
577 compatible = "national,lm95245";
578 reg = <0x4c>;
579 };
580
581 /* SW: +V1.2_VDD_CORE */
582 tps62362@60 {
583 compatible = "ti,tps62362";
584 reg = <0x60>;
585
586 regulator-name = "tps62362-vout";
587 regulator-min-microvolt = <900000>;
588 regulator-max-microvolt = <1400000>;
589 regulator-boot-on;
590 regulator-always-on;
591 ti,vsel0-state-low;
592 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
593 ti,vsel1-state-low;
594 };
595 };
596
597 /* SPI4: CAN2 */
598 spi@7000da00 {
599 status = "okay";
600 spi-max-frequency = <10000000>;
601
602 can@1 {
603 compatible = "microchip,mcp2515";
604 reg = <1>;
605 clocks = <&clk16m>;
606 interrupt-parent = <&gpio>;
607 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
608 spi-max-frequency = <10000000>;
609 };
610 };
611
612 /* SPI6: CAN1 */
613 spi@7000de00 {
614 status = "okay";
615 spi-max-frequency = <10000000>;
616
617 can@0 {
618 compatible = "microchip,mcp2515";
619 reg = <0>;
620 clocks = <&clk16m>;
621 interrupt-parent = <&gpio>;
622 interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
623 spi-max-frequency = <10000000>;
624 };
625 };
626
627 pmc@7000e400 {
628 nvidia,invert-interrupt;
629 nvidia,suspend-mode = <1>;
630 nvidia,cpu-pwr-good-time = <5000>;
631 nvidia,cpu-pwr-off-time = <5000>;
632 nvidia,core-pwr-good-time = <3845 3845>;
633 nvidia,core-pwr-off-time = <0>;
634 nvidia,core-power-req-active-high;
635 nvidia,sys-clock-req-active-high;
636 };
637
638 sdhci@78000600 {
639 status = "okay";
640 bus-width = <8>;
641 non-removable;
642 };
643
644 clocks {
645 compatible = "simple-bus";
646 #address-cells = <1>;
647 #size-cells = <0>;
648
649 clk32k_in: clk@0 {
650 compatible = "fixed-clock";
651 reg=<0>;
652 #clock-cells = <0>;
653 clock-frequency = <32768>;
654 };
655 clk16m: clk@1 {
656 compatible = "fixed-clock";
657 reg=<1>;
658 #clock-cells = <0>;
659 clock-frequency = <16000000>;
660 clock-output-names = "clk16m";
661 };
662 };
663
664 regulators {
665 compatible = "simple-bus";
666 #address-cells = <1>;
667 #size-cells = <0>;
668
669 sys_3v3_reg: regulator@100 {
670 compatible = "regulator-fixed";
671 reg = <100>;
672 regulator-name = "3v3";
673 regulator-min-microvolt = <3300000>;
674 regulator-max-microvolt = <3300000>;
675 regulator-always-on;
676 };
Marcel Ziswilercaa9eac2014-08-22 13:25:10 -0600[diff] [blame^]677
678 charge_pump_5v0_reg: regulator@101 {
679 compatible = "regulator-fixed";
680 reg = <101>;
681 regulator-name = "5v0";
682 regulator-min-microvolt = <5000000>;
683 regulator-max-microvolt = <5000000>;
684 regulator-always-on;
685 };
Marcel Ziswiler6d0a0672014-06-10 00:52:46 +0200[diff] [blame]686 };
687};