Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | |
| 30 | #include "atom.h" |
| 31 | #include <asm/div64.h> |
| 32 | |
| 33 | #include "drm_crtc_helper.h" |
| 34 | #include "drm_edid.h" |
| 35 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 36 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
| 37 | { |
| 38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 39 | struct drm_device *dev = crtc->dev; |
| 40 | struct radeon_device *rdev = dev->dev_private; |
| 41 | int i; |
| 42 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 43 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
| 45 | |
| 46 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
| 47 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
| 48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
| 49 | |
| 50 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
| 51 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
| 52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
| 53 | |
| 54 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
| 55 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
| 56 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
| 57 | |
| 58 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
| 59 | for (i = 0; i < 256; i++) { |
| 60 | WREG32(AVIVO_DC_LUT_30_COLOR, |
| 61 | (radeon_crtc->lut_r[i] << 20) | |
| 62 | (radeon_crtc->lut_g[i] << 10) | |
| 63 | (radeon_crtc->lut_b[i] << 0)); |
| 64 | } |
| 65 | |
| 66 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
| 67 | } |
| 68 | |
Alex Deucher | fee298f | 2011-01-06 21:19:30 -0500 | [diff] [blame] | 69 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 70 | { |
| 71 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 72 | struct drm_device *dev = crtc->dev; |
| 73 | struct radeon_device *rdev = dev->dev_private; |
| 74 | int i; |
| 75 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 76 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 77 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
| 78 | |
| 79 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
| 80 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
| 81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
| 82 | |
| 83 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
| 84 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
| 85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
| 86 | |
Alex Deucher | 677d076 | 2010-04-22 22:58:50 -0400 | [diff] [blame] | 87 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
| 88 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 89 | |
Alex Deucher | 677d076 | 2010-04-22 22:58:50 -0400 | [diff] [blame] | 90 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 91 | for (i = 0; i < 256; i++) { |
Alex Deucher | 677d076 | 2010-04-22 22:58:50 -0400 | [diff] [blame] | 92 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 93 | (radeon_crtc->lut_r[i] << 20) | |
| 94 | (radeon_crtc->lut_g[i] << 10) | |
| 95 | (radeon_crtc->lut_b[i] << 0)); |
| 96 | } |
| 97 | } |
| 98 | |
Alex Deucher | fee298f | 2011-01-06 21:19:30 -0500 | [diff] [blame] | 99 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
| 100 | { |
| 101 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 102 | struct drm_device *dev = crtc->dev; |
| 103 | struct radeon_device *rdev = dev->dev_private; |
| 104 | int i; |
| 105 | |
| 106 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
| 107 | |
| 108 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
| 109 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
| 110 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
| 111 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
| 112 | NI_GRPH_PRESCALE_BYPASS); |
| 113 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
| 114 | NI_OVL_PRESCALE_BYPASS); |
| 115 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
| 116 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
| 117 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
| 118 | |
| 119 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
| 120 | |
| 121 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
| 122 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
| 123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
| 124 | |
| 125 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
| 126 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
| 127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
| 128 | |
| 129 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
| 130 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
| 131 | |
| 132 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
| 133 | for (i = 0; i < 256; i++) { |
| 134 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
| 135 | (radeon_crtc->lut_r[i] << 20) | |
| 136 | (radeon_crtc->lut_g[i] << 10) | |
| 137 | (radeon_crtc->lut_b[i] << 0)); |
| 138 | } |
| 139 | |
| 140 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
| 141 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
| 142 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
| 143 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
| 144 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
| 145 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
| 146 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
| 147 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
| 148 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
| 149 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
| 150 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
| 151 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
| 152 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
| 153 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
| 154 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
| 155 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
| 156 | |
| 157 | } |
| 158 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
| 160 | { |
| 161 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 162 | struct drm_device *dev = crtc->dev; |
| 163 | struct radeon_device *rdev = dev->dev_private; |
| 164 | int i; |
| 165 | uint32_t dac2_cntl; |
| 166 | |
| 167 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
| 168 | if (radeon_crtc->crtc_id == 0) |
| 169 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
| 170 | else |
| 171 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
| 172 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 173 | |
| 174 | WREG8(RADEON_PALETTE_INDEX, 0); |
| 175 | for (i = 0; i < 256; i++) { |
| 176 | WREG32(RADEON_PALETTE_30_DATA, |
| 177 | (radeon_crtc->lut_r[i] << 20) | |
| 178 | (radeon_crtc->lut_g[i] << 10) | |
| 179 | (radeon_crtc->lut_b[i] << 0)); |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
| 184 | { |
| 185 | struct drm_device *dev = crtc->dev; |
| 186 | struct radeon_device *rdev = dev->dev_private; |
| 187 | |
| 188 | if (!crtc->enabled) |
| 189 | return; |
| 190 | |
Alex Deucher | fee298f | 2011-01-06 21:19:30 -0500 | [diff] [blame] | 191 | if (ASIC_IS_DCE5(rdev)) |
| 192 | dce5_crtc_load_lut(crtc); |
| 193 | else if (ASIC_IS_DCE4(rdev)) |
| 194 | dce4_crtc_load_lut(crtc); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 195 | else if (ASIC_IS_AVIVO(rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | avivo_crtc_load_lut(crtc); |
| 197 | else |
| 198 | legacy_crtc_load_lut(crtc); |
| 199 | } |
| 200 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 201 | /** Sets the color ramps on behalf of fbcon */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 203 | u16 blue, int regno) |
| 204 | { |
| 205 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 206 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 207 | radeon_crtc->lut_r[regno] = red >> 6; |
| 208 | radeon_crtc->lut_g[regno] = green >> 6; |
| 209 | radeon_crtc->lut_b[regno] = blue >> 6; |
| 210 | } |
| 211 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 212 | /** Gets the color ramps on behalf of fbcon */ |
| 213 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 214 | u16 *blue, int regno) |
| 215 | { |
| 216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 217 | |
| 218 | *red = radeon_crtc->lut_r[regno] << 6; |
| 219 | *green = radeon_crtc->lut_g[regno] << 6; |
| 220 | *blue = radeon_crtc->lut_b[regno] << 6; |
| 221 | } |
| 222 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 224 | u16 *blue, uint32_t start, uint32_t size) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | { |
| 226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 227 | int end = (start + size > 256) ? 256 : start + size, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 229 | /* userspace palettes are always correct as is */ |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 230 | for (i = start; i < end; i++) { |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 231 | radeon_crtc->lut_r[i] = red[i] >> 6; |
| 232 | radeon_crtc->lut_g[i] = green[i] >> 6; |
| 233 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 234 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | radeon_crtc_load_lut(crtc); |
| 236 | } |
| 237 | |
| 238 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
| 239 | { |
| 240 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 241 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | drm_crtc_cleanup(crtc); |
| 243 | kfree(radeon_crtc); |
| 244 | } |
| 245 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 246 | /* |
| 247 | * Handle unpin events outside the interrupt handler proper. |
| 248 | */ |
| 249 | static void radeon_unpin_work_func(struct work_struct *__work) |
| 250 | { |
| 251 | struct radeon_unpin_work *work = |
| 252 | container_of(__work, struct radeon_unpin_work, work); |
| 253 | int r; |
| 254 | |
| 255 | /* unpin of the old buffer */ |
| 256 | r = radeon_bo_reserve(work->old_rbo, false); |
| 257 | if (likely(r == 0)) { |
| 258 | r = radeon_bo_unpin(work->old_rbo); |
| 259 | if (unlikely(r != 0)) { |
| 260 | DRM_ERROR("failed to unpin buffer after flip\n"); |
| 261 | } |
| 262 | radeon_bo_unreserve(work->old_rbo); |
| 263 | } else |
| 264 | DRM_ERROR("failed to reserve buffer after flip\n"); |
Dave Airlie | 498c555 | 2011-05-29 17:48:32 +1000 | [diff] [blame] | 265 | |
| 266 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 267 | kfree(work); |
| 268 | } |
| 269 | |
| 270 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) |
| 271 | { |
| 272 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 273 | struct radeon_unpin_work *work; |
| 274 | struct drm_pending_vblank_event *e; |
| 275 | struct timeval now; |
| 276 | unsigned long flags; |
| 277 | u32 update_pending; |
| 278 | int vpos, hpos; |
| 279 | |
| 280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); |
| 281 | work = radeon_crtc->unpin_work; |
| 282 | if (work == NULL || |
Michel Dänzer | fcc485d | 2011-07-13 15:18:09 +0000 | [diff] [blame] | 283 | (work->fence && !radeon_fence_signaled(work->fence))) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 284 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
| 285 | return; |
| 286 | } |
| 287 | /* New pageflip, or just completion of a previous one? */ |
| 288 | if (!radeon_crtc->deferred_flip_completion) { |
| 289 | /* do the flip (mmio) */ |
| 290 | update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); |
| 291 | } else { |
| 292 | /* This is just a completion of a flip queued in crtc |
| 293 | * at last invocation. Make sure we go directly to |
| 294 | * completion routine. |
| 295 | */ |
| 296 | update_pending = 0; |
| 297 | radeon_crtc->deferred_flip_completion = 0; |
| 298 | } |
| 299 | |
| 300 | /* Has the pageflip already completed in crtc, or is it certain |
| 301 | * to complete in this vblank? |
| 302 | */ |
| 303 | if (update_pending && |
| 304 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, |
| 305 | &vpos, &hpos)) && |
Felix Kuehling | 81ffbbe | 2012-02-23 19:16:12 -0500 | [diff] [blame] | 306 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
| 307 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { |
| 308 | /* crtc didn't flip in this target vblank interval, |
| 309 | * but flip is pending in crtc. Based on the current |
| 310 | * scanout position we know that the current frame is |
| 311 | * (nearly) complete and the flip will (likely) |
| 312 | * complete before the start of the next frame. |
| 313 | */ |
| 314 | update_pending = 0; |
| 315 | } |
| 316 | if (update_pending) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 317 | /* crtc didn't flip in this target vblank interval, |
| 318 | * but flip is pending in crtc. It will complete it |
| 319 | * in next vblank interval, so complete the flip at |
| 320 | * next vblank irq. |
| 321 | */ |
| 322 | radeon_crtc->deferred_flip_completion = 1; |
| 323 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
| 324 | return; |
| 325 | } |
| 326 | |
| 327 | /* Pageflip (will be) certainly completed in this vblank. Clean up. */ |
| 328 | radeon_crtc->unpin_work = NULL; |
| 329 | |
| 330 | /* wakeup userspace */ |
| 331 | if (work->event) { |
| 332 | e = work->event; |
Mario Kleiner | b672440 | 2010-11-21 10:59:03 -0500 | [diff] [blame] | 333 | e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 334 | e->event.tv_sec = now.tv_sec; |
| 335 | e->event.tv_usec = now.tv_usec; |
| 336 | list_add_tail(&e->base.link, &e->base.file_priv->event_list); |
| 337 | wake_up_interruptible(&e->base.file_priv->event_wait); |
| 338 | } |
| 339 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
| 340 | |
| 341 | drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); |
| 342 | radeon_fence_unref(&work->fence); |
| 343 | radeon_post_page_flip(work->rdev, work->crtc_id); |
| 344 | schedule_work(&work->work); |
| 345 | } |
| 346 | |
| 347 | static int radeon_crtc_page_flip(struct drm_crtc *crtc, |
| 348 | struct drm_framebuffer *fb, |
| 349 | struct drm_pending_vblank_event *event) |
| 350 | { |
| 351 | struct drm_device *dev = crtc->dev; |
| 352 | struct radeon_device *rdev = dev->dev_private; |
| 353 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 354 | struct radeon_framebuffer *old_radeon_fb; |
| 355 | struct radeon_framebuffer *new_radeon_fb; |
| 356 | struct drm_gem_object *obj; |
| 357 | struct radeon_bo *rbo; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 358 | struct radeon_unpin_work *work; |
| 359 | unsigned long flags; |
| 360 | u32 tiling_flags, pitch_pixels; |
| 361 | u64 base; |
| 362 | int r; |
| 363 | |
| 364 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 365 | if (work == NULL) |
| 366 | return -ENOMEM; |
| 367 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 368 | work->event = event; |
| 369 | work->rdev = rdev; |
| 370 | work->crtc_id = radeon_crtc->crtc_id; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 371 | old_radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 372 | new_radeon_fb = to_radeon_framebuffer(fb); |
| 373 | /* schedule unpin of the old buffer */ |
| 374 | obj = old_radeon_fb->obj; |
Dave Airlie | 498c555 | 2011-05-29 17:48:32 +1000 | [diff] [blame] | 375 | /* take a reference to the old object */ |
| 376 | drm_gem_object_reference(obj); |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 377 | rbo = gem_to_radeon_bo(obj); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 378 | work->old_rbo = rbo; |
Michel Dänzer | fcc485d | 2011-07-13 15:18:09 +0000 | [diff] [blame] | 379 | obj = new_radeon_fb->obj; |
| 380 | rbo = gem_to_radeon_bo(obj); |
| 381 | if (rbo->tbo.sync_obj) |
| 382 | work->fence = radeon_fence_ref(rbo->tbo.sync_obj); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 383 | INIT_WORK(&work->work, radeon_unpin_work_func); |
| 384 | |
| 385 | /* We borrow the event spin lock for protecting unpin_work */ |
| 386 | spin_lock_irqsave(&dev->event_lock, flags); |
| 387 | if (radeon_crtc->unpin_work) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 388 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Dave Airlie | 498c555 | 2011-05-29 17:48:32 +1000 | [diff] [blame] | 389 | r = -EBUSY; |
| 390 | goto unlock_free; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 391 | } |
| 392 | radeon_crtc->unpin_work = work; |
| 393 | radeon_crtc->deferred_flip_completion = 0; |
| 394 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 395 | |
| 396 | /* pin the new buffer */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 397 | DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", |
| 398 | work->old_rbo, rbo); |
| 399 | |
| 400 | r = radeon_bo_reserve(rbo, false); |
| 401 | if (unlikely(r != 0)) { |
| 402 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); |
| 403 | goto pflip_cleanup; |
| 404 | } |
Michel Dänzer | 0349af7 | 2012-03-14 17:12:42 +0100 | [diff] [blame] | 405 | /* Only 27 bit offset for legacy CRTC */ |
| 406 | r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, |
| 407 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 408 | if (unlikely(r != 0)) { |
| 409 | radeon_bo_unreserve(rbo); |
| 410 | r = -EINVAL; |
| 411 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); |
| 412 | goto pflip_cleanup; |
| 413 | } |
| 414 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 415 | radeon_bo_unreserve(rbo); |
| 416 | |
| 417 | if (!ASIC_IS_AVIVO(rdev)) { |
| 418 | /* crtc offset is from display base addr not FB location */ |
| 419 | base -= radeon_crtc->legacy_display_base_addr; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 420 | pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 421 | |
| 422 | if (tiling_flags & RADEON_TILING_MACRO) { |
| 423 | if (ASIC_IS_R300(rdev)) { |
| 424 | base &= ~0x7ff; |
| 425 | } else { |
| 426 | int byteshift = fb->bits_per_pixel >> 4; |
| 427 | int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; |
| 428 | base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); |
| 429 | } |
| 430 | } else { |
| 431 | int offset = crtc->y * pitch_pixels + crtc->x; |
| 432 | switch (fb->bits_per_pixel) { |
| 433 | case 8: |
| 434 | default: |
| 435 | offset *= 1; |
| 436 | break; |
| 437 | case 15: |
| 438 | case 16: |
| 439 | offset *= 2; |
| 440 | break; |
| 441 | case 24: |
| 442 | offset *= 3; |
| 443 | break; |
| 444 | case 32: |
| 445 | offset *= 4; |
| 446 | break; |
| 447 | } |
| 448 | base += offset; |
| 449 | } |
| 450 | base &= ~7; |
| 451 | } |
| 452 | |
| 453 | spin_lock_irqsave(&dev->event_lock, flags); |
| 454 | work->new_crtc_base = base; |
| 455 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 456 | |
| 457 | /* update crtc fb */ |
| 458 | crtc->fb = fb; |
| 459 | |
| 460 | r = drm_vblank_get(dev, radeon_crtc->crtc_id); |
| 461 | if (r) { |
| 462 | DRM_ERROR("failed to get vblank before flip\n"); |
| 463 | goto pflip_cleanup1; |
| 464 | } |
| 465 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 466 | /* set the proper interrupt */ |
| 467 | radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 468 | |
| 469 | return 0; |
| 470 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 471 | pflip_cleanup1: |
Michel Dänzer | d0254d5 | 2011-07-13 15:18:10 +0000 | [diff] [blame] | 472 | if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 473 | DRM_ERROR("failed to reserve new rbo in error path\n"); |
| 474 | goto pflip_cleanup; |
| 475 | } |
Michel Dänzer | d0254d5 | 2011-07-13 15:18:10 +0000 | [diff] [blame] | 476 | if (unlikely(radeon_bo_unpin(rbo) != 0)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 477 | DRM_ERROR("failed to unpin new rbo in error path\n"); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 478 | } |
| 479 | radeon_bo_unreserve(rbo); |
| 480 | |
| 481 | pflip_cleanup: |
| 482 | spin_lock_irqsave(&dev->event_lock, flags); |
| 483 | radeon_crtc->unpin_work = NULL; |
Dave Airlie | 498c555 | 2011-05-29 17:48:32 +1000 | [diff] [blame] | 484 | unlock_free: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 485 | spin_unlock_irqrestore(&dev->event_lock, flags); |
Michel Dänzer | db318d7 | 2011-09-13 11:29:12 +0200 | [diff] [blame] | 486 | drm_gem_object_unreference_unlocked(old_radeon_fb->obj); |
Michel Dänzer | fcc485d | 2011-07-13 15:18:09 +0000 | [diff] [blame] | 487 | radeon_fence_unref(&work->fence); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 488 | kfree(work); |
| 489 | |
| 490 | return r; |
| 491 | } |
| 492 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 493 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
| 494 | .cursor_set = radeon_crtc_cursor_set, |
| 495 | .cursor_move = radeon_crtc_cursor_move, |
| 496 | .gamma_set = radeon_crtc_gamma_set, |
| 497 | .set_config = drm_crtc_helper_set_config, |
| 498 | .destroy = radeon_crtc_destroy, |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 499 | .page_flip = radeon_crtc_page_flip, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 500 | }; |
| 501 | |
| 502 | static void radeon_crtc_init(struct drm_device *dev, int index) |
| 503 | { |
| 504 | struct radeon_device *rdev = dev->dev_private; |
| 505 | struct radeon_crtc *radeon_crtc; |
| 506 | int i; |
| 507 | |
| 508 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 509 | if (radeon_crtc == NULL) |
| 510 | return; |
| 511 | |
| 512 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
| 513 | |
| 514 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
| 515 | radeon_crtc->crtc_id = index; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 516 | rdev->mode_info.crtcs[index] = radeon_crtc; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 517 | |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 518 | #if 0 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 519 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
| 520 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
| 521 | radeon_crtc->mode_set.num_connectors = 0; |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 522 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 523 | |
| 524 | for (i = 0; i < 256; i++) { |
| 525 | radeon_crtc->lut_r[i] = i << 2; |
| 526 | radeon_crtc->lut_g[i] = i << 2; |
| 527 | radeon_crtc->lut_b[i] = i << 2; |
| 528 | } |
| 529 | |
| 530 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
| 531 | radeon_atombios_init_crtc(dev, radeon_crtc); |
| 532 | else |
| 533 | radeon_legacy_init_crtc(dev, radeon_crtc); |
| 534 | } |
| 535 | |
Ilija Hadzic | df391c0 | 2012-04-19 12:22:20 -0400 | [diff] [blame] | 536 | static const char *encoder_names[37] = { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | "NONE", |
| 538 | "INTERNAL_LVDS", |
| 539 | "INTERNAL_TMDS1", |
| 540 | "INTERNAL_TMDS2", |
| 541 | "INTERNAL_DAC1", |
| 542 | "INTERNAL_DAC2", |
| 543 | "INTERNAL_SDVOA", |
| 544 | "INTERNAL_SDVOB", |
| 545 | "SI170B", |
| 546 | "CH7303", |
| 547 | "CH7301", |
| 548 | "INTERNAL_DVO1", |
| 549 | "EXTERNAL_SDVOA", |
| 550 | "EXTERNAL_SDVOB", |
| 551 | "TITFP513", |
| 552 | "INTERNAL_LVTM1", |
| 553 | "VT1623", |
| 554 | "HDMI_SI1930", |
| 555 | "HDMI_INTERNAL", |
| 556 | "INTERNAL_KLDSCP_TMDS1", |
| 557 | "INTERNAL_KLDSCP_DVO1", |
| 558 | "INTERNAL_KLDSCP_DAC1", |
| 559 | "INTERNAL_KLDSCP_DAC2", |
| 560 | "SI178", |
| 561 | "MVPU_FPGA", |
| 562 | "INTERNAL_DDI", |
| 563 | "VT1625", |
| 564 | "HDMI_SI1932", |
| 565 | "DP_AN9801", |
| 566 | "DP_DP501", |
| 567 | "INTERNAL_UNIPHY", |
| 568 | "INTERNAL_KLDSCP_LVTMA", |
| 569 | "INTERNAL_UNIPHY1", |
| 570 | "INTERNAL_UNIPHY2", |
Alex Deucher | bf982eb | 2010-11-22 17:56:24 -0500 | [diff] [blame] | 571 | "NUTMEG", |
| 572 | "TRAVIS", |
Ilija Hadzic | df391c0 | 2012-04-19 12:22:20 -0400 | [diff] [blame] | 573 | "INTERNAL_VCE" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 574 | }; |
| 575 | |
Alex Deucher | 196c58d | 2010-01-07 14:22:32 -0500 | [diff] [blame] | 576 | static const char *connector_names[15] = { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 577 | "Unknown", |
| 578 | "VGA", |
| 579 | "DVI-I", |
| 580 | "DVI-D", |
| 581 | "DVI-A", |
| 582 | "Composite", |
| 583 | "S-video", |
| 584 | "LVDS", |
| 585 | "Component", |
| 586 | "DIN", |
| 587 | "DisplayPort", |
| 588 | "HDMI-A", |
| 589 | "HDMI-B", |
Alex Deucher | 196c58d | 2010-01-07 14:22:32 -0500 | [diff] [blame] | 590 | "TV", |
| 591 | "eDP", |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 592 | }; |
| 593 | |
Alex Deucher | cbd4623 | 2010-06-07 02:24:54 -0400 | [diff] [blame] | 594 | static const char *hpd_names[6] = { |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 595 | "HPD1", |
| 596 | "HPD2", |
| 597 | "HPD3", |
| 598 | "HPD4", |
| 599 | "HPD5", |
| 600 | "HPD6", |
| 601 | }; |
| 602 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 603 | static void radeon_print_display_setup(struct drm_device *dev) |
| 604 | { |
| 605 | struct drm_connector *connector; |
| 606 | struct radeon_connector *radeon_connector; |
| 607 | struct drm_encoder *encoder; |
| 608 | struct radeon_encoder *radeon_encoder; |
| 609 | uint32_t devices; |
| 610 | int i = 0; |
| 611 | |
| 612 | DRM_INFO("Radeon Display Connectors\n"); |
| 613 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 614 | radeon_connector = to_radeon_connector(connector); |
| 615 | DRM_INFO("Connector %d:\n", i); |
| 616 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 617 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
| 618 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
Dave Airlie | 4b9d2a2 | 2010-02-08 13:16:55 +1000 | [diff] [blame] | 619 | if (radeon_connector->ddc_bus) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 620 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
| 621 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
| 622 | radeon_connector->ddc_bus->rec.mask_data_reg, |
| 623 | radeon_connector->ddc_bus->rec.a_clk_reg, |
| 624 | radeon_connector->ddc_bus->rec.a_data_reg, |
Alex Deucher | 9b9fe72 | 2009-11-10 15:59:44 -0500 | [diff] [blame] | 625 | radeon_connector->ddc_bus->rec.en_clk_reg, |
| 626 | radeon_connector->ddc_bus->rec.en_data_reg, |
| 627 | radeon_connector->ddc_bus->rec.y_clk_reg, |
| 628 | radeon_connector->ddc_bus->rec.y_data_reg); |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 629 | if (radeon_connector->router.ddc_valid) |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 630 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 631 | radeon_connector->router.ddc_mux_control_pin, |
| 632 | radeon_connector->router.ddc_mux_state); |
| 633 | if (radeon_connector->router.cd_valid) |
| 634 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
| 635 | radeon_connector->router.cd_mux_control_pin, |
| 636 | radeon_connector->router.cd_mux_state); |
Dave Airlie | 4b9d2a2 | 2010-02-08 13:16:55 +1000 | [diff] [blame] | 637 | } else { |
| 638 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
| 639 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
| 640 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
| 641 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
| 642 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
| 643 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
| 644 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
| 645 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 646 | DRM_INFO(" Encoders:\n"); |
| 647 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 648 | radeon_encoder = to_radeon_encoder(encoder); |
| 649 | devices = radeon_encoder->devices & radeon_connector->devices; |
| 650 | if (devices) { |
| 651 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
| 652 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 653 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
| 654 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 655 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
| 656 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 657 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
| 658 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 659 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
| 660 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 661 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
| 662 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 663 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
| 664 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 665 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
| 666 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
Alex Deucher | 73758a5 | 2010-09-24 14:59:32 -0400 | [diff] [blame] | 667 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
| 668 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 669 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
| 670 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 671 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
| 672 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
| 673 | } |
| 674 | } |
| 675 | i++; |
| 676 | } |
| 677 | } |
| 678 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 679 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 680 | { |
| 681 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 682 | bool ret = false; |
| 683 | |
| 684 | if (rdev->bios) { |
| 685 | if (rdev->is_atom_bios) { |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 686 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
| 687 | if (ret == false) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 688 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
Alex Deucher | b9597a1 | 2010-01-04 19:12:02 -0500 | [diff] [blame] | 689 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 690 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
Alex Deucher | b9597a1 | 2010-01-04 19:12:02 -0500 | [diff] [blame] | 691 | if (ret == false) |
| 692 | ret = radeon_get_legacy_connector_info_from_table(dev); |
| 693 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 694 | } else { |
| 695 | if (!ASIC_IS_AVIVO(rdev)) |
| 696 | ret = radeon_get_legacy_connector_info_from_table(dev); |
| 697 | } |
| 698 | if (ret) { |
Dave Airlie | 1f3b6a4 | 2009-10-13 14:10:37 +1000 | [diff] [blame] | 699 | radeon_setup_encoder_clones(dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 700 | radeon_print_display_setup(dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 701 | } |
| 702 | |
| 703 | return ret; |
| 704 | } |
| 705 | |
| 706 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
| 707 | { |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 708 | struct drm_device *dev = radeon_connector->base.dev; |
| 709 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 710 | int ret = 0; |
| 711 | |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 712 | /* on hw with routers, select right port */ |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 713 | if (radeon_connector->router.ddc_valid) |
| 714 | radeon_router_select_ddc_port(radeon_connector); |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 715 | |
Alex Deucher | 196c58d | 2010-01-07 14:22:32 -0500 | [diff] [blame] | 716 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
Alex Deucher | b06947b | 2011-09-02 14:23:09 +0000 | [diff] [blame] | 717 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) || |
Alex Deucher | 1d33e1f | 2011-10-31 08:58:47 -0400 | [diff] [blame] | 718 | (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != |
| 719 | ENCODER_OBJECT_ID_NONE)) { |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 720 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
Alex Deucher | b06947b | 2011-09-02 14:23:09 +0000 | [diff] [blame] | 721 | |
Dave Airlie | 7a15cbd4 | 2010-01-14 11:42:17 +1000 | [diff] [blame] | 722 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
| 723 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
Alex Deucher | b06947b | 2011-09-02 14:23:09 +0000 | [diff] [blame] | 724 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
| 725 | &dig->dp_i2c_bus->adapter); |
| 726 | else if (radeon_connector->ddc_bus && !radeon_connector->edid) |
| 727 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
| 728 | &radeon_connector->ddc_bus->adapter); |
| 729 | } else { |
| 730 | if (radeon_connector->ddc_bus && !radeon_connector->edid) |
| 731 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
| 732 | &radeon_connector->ddc_bus->adapter); |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 733 | } |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 734 | |
| 735 | if (!radeon_connector->edid) { |
| 736 | if (rdev->is_atom_bios) { |
| 737 | /* some laptops provide a hardcoded edid in rom for LCDs */ |
| 738 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || |
| 739 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) |
| 740 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
| 741 | } else |
| 742 | /* some servers provide a hardcoded edid in rom for KVMs */ |
| 743 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
| 744 | } |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 745 | if (radeon_connector->edid) { |
| 746 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
| 747 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 748 | return ret; |
| 749 | } |
| 750 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
Dave Airlie | 42dea5d | 2009-09-15 20:21:11 +1000 | [diff] [blame] | 751 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 752 | } |
| 753 | |
Alex Deucher | f523f74 | 2011-01-31 16:48:52 -0500 | [diff] [blame] | 754 | /* avivo */ |
| 755 | static void avivo_get_fb_div(struct radeon_pll *pll, |
| 756 | u32 target_clock, |
| 757 | u32 post_div, |
| 758 | u32 ref_div, |
| 759 | u32 *fb_div, |
| 760 | u32 *frac_fb_div) |
| 761 | { |
| 762 | u32 tmp = post_div * ref_div; |
| 763 | |
| 764 | tmp *= target_clock; |
| 765 | *fb_div = tmp / pll->reference_freq; |
| 766 | *frac_fb_div = tmp % pll->reference_freq; |
Alex Deucher | a4b40d5 | 2011-02-14 11:43:10 -0500 | [diff] [blame] | 767 | |
| 768 | if (*fb_div > pll->max_feedback_div) |
| 769 | *fb_div = pll->max_feedback_div; |
| 770 | else if (*fb_div < pll->min_feedback_div) |
| 771 | *fb_div = pll->min_feedback_div; |
Alex Deucher | f523f74 | 2011-01-31 16:48:52 -0500 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
| 775 | u32 target_clock) |
| 776 | { |
| 777 | u32 vco, post_div, tmp; |
| 778 | |
| 779 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
| 780 | return pll->post_div; |
| 781 | |
| 782 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
| 783 | if (pll->flags & RADEON_PLL_IS_LCD) |
| 784 | vco = pll->lcd_pll_out_min; |
| 785 | else |
| 786 | vco = pll->pll_out_min; |
| 787 | } else { |
| 788 | if (pll->flags & RADEON_PLL_IS_LCD) |
| 789 | vco = pll->lcd_pll_out_max; |
| 790 | else |
| 791 | vco = pll->pll_out_max; |
| 792 | } |
| 793 | |
| 794 | post_div = vco / target_clock; |
| 795 | tmp = vco % target_clock; |
| 796 | |
| 797 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
| 798 | if (tmp) |
| 799 | post_div++; |
| 800 | } else { |
| 801 | if (!tmp) |
| 802 | post_div--; |
| 803 | } |
| 804 | |
Alex Deucher | a4b40d5 | 2011-02-14 11:43:10 -0500 | [diff] [blame] | 805 | if (post_div > pll->max_post_div) |
| 806 | post_div = pll->max_post_div; |
| 807 | else if (post_div < pll->min_post_div) |
| 808 | post_div = pll->min_post_div; |
| 809 | |
Alex Deucher | f523f74 | 2011-01-31 16:48:52 -0500 | [diff] [blame] | 810 | return post_div; |
| 811 | } |
| 812 | |
| 813 | #define MAX_TOLERANCE 10 |
| 814 | |
| 815 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
| 816 | u32 freq, |
| 817 | u32 *dot_clock_p, |
| 818 | u32 *fb_div_p, |
| 819 | u32 *frac_fb_div_p, |
| 820 | u32 *ref_div_p, |
| 821 | u32 *post_div_p) |
| 822 | { |
| 823 | u32 target_clock = freq / 10; |
| 824 | u32 post_div = avivo_get_post_div(pll, target_clock); |
| 825 | u32 ref_div = pll->min_ref_div; |
| 826 | u32 fb_div = 0, frac_fb_div = 0, tmp; |
| 827 | |
| 828 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
| 829 | ref_div = pll->reference_div; |
| 830 | |
| 831 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
| 832 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); |
| 833 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; |
| 834 | if (frac_fb_div >= 5) { |
| 835 | frac_fb_div -= 5; |
| 836 | frac_fb_div = frac_fb_div / 10; |
| 837 | frac_fb_div++; |
| 838 | } |
| 839 | if (frac_fb_div >= 10) { |
| 840 | fb_div++; |
| 841 | frac_fb_div = 0; |
| 842 | } |
| 843 | } else { |
| 844 | while (ref_div <= pll->max_ref_div) { |
| 845 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, |
| 846 | &fb_div, &frac_fb_div); |
| 847 | if (frac_fb_div >= (pll->reference_freq / 2)) |
| 848 | fb_div++; |
| 849 | frac_fb_div = 0; |
| 850 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); |
| 851 | tmp = (tmp * 10000) / target_clock; |
| 852 | |
| 853 | if (tmp > (10000 + MAX_TOLERANCE)) |
| 854 | ref_div++; |
| 855 | else if (tmp >= (10000 - MAX_TOLERANCE)) |
| 856 | break; |
| 857 | else |
| 858 | ref_div++; |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / |
| 863 | (ref_div * post_div * 10); |
| 864 | *fb_div_p = fb_div; |
| 865 | *frac_fb_div_p = frac_fb_div; |
| 866 | *ref_div_p = ref_div; |
| 867 | *post_div_p = post_div; |
| 868 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
| 869 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); |
| 870 | } |
| 871 | |
| 872 | /* pre-avivo */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 873 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
| 874 | { |
| 875 | uint64_t mod; |
| 876 | |
| 877 | n += d / 2; |
| 878 | |
| 879 | mod = do_div(n, d); |
| 880 | return n; |
| 881 | } |
| 882 | |
Alex Deucher | f523f74 | 2011-01-31 16:48:52 -0500 | [diff] [blame] | 883 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
| 884 | uint64_t freq, |
| 885 | uint32_t *dot_clock_p, |
| 886 | uint32_t *fb_div_p, |
| 887 | uint32_t *frac_fb_div_p, |
| 888 | uint32_t *ref_div_p, |
| 889 | uint32_t *post_div_p) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 890 | { |
| 891 | uint32_t min_ref_div = pll->min_ref_div; |
| 892 | uint32_t max_ref_div = pll->max_ref_div; |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 893 | uint32_t min_post_div = pll->min_post_div; |
| 894 | uint32_t max_post_div = pll->max_post_div; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 895 | uint32_t min_fractional_feed_div = 0; |
| 896 | uint32_t max_fractional_feed_div = 0; |
| 897 | uint32_t best_vco = pll->best_vco; |
| 898 | uint32_t best_post_div = 1; |
| 899 | uint32_t best_ref_div = 1; |
| 900 | uint32_t best_feedback_div = 1; |
| 901 | uint32_t best_frac_feedback_div = 0; |
| 902 | uint32_t best_freq = -1; |
| 903 | uint32_t best_error = 0xffffffff; |
| 904 | uint32_t best_vco_diff = 1; |
| 905 | uint32_t post_div; |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 906 | u32 pll_out_min, pll_out_max; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 907 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 908 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 909 | freq = freq * 1000; |
| 910 | |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 911 | if (pll->flags & RADEON_PLL_IS_LCD) { |
| 912 | pll_out_min = pll->lcd_pll_out_min; |
| 913 | pll_out_max = pll->lcd_pll_out_max; |
| 914 | } else { |
| 915 | pll_out_min = pll->pll_out_min; |
| 916 | pll_out_max = pll->pll_out_max; |
| 917 | } |
| 918 | |
Alex Deucher | 619efb1 | 2011-01-31 16:48:53 -0500 | [diff] [blame] | 919 | if (pll_out_min > 64800) |
| 920 | pll_out_min = 64800; |
| 921 | |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 922 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 923 | min_ref_div = max_ref_div = pll->reference_div; |
| 924 | else { |
| 925 | while (min_ref_div < max_ref_div-1) { |
| 926 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
| 927 | uint32_t pll_in = pll->reference_freq / mid; |
| 928 | if (pll_in < pll->pll_in_min) |
| 929 | max_ref_div = mid; |
| 930 | else if (pll_in > pll->pll_in_max) |
| 931 | min_ref_div = mid; |
| 932 | else |
| 933 | break; |
| 934 | } |
| 935 | } |
| 936 | |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 937 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
| 938 | min_post_div = max_post_div = pll->post_div; |
| 939 | |
| 940 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 941 | min_fractional_feed_div = pll->min_frac_feedback_div; |
| 942 | max_fractional_feed_div = pll->max_frac_feedback_div; |
| 943 | } |
| 944 | |
Alex Deucher | bd6a60a | 2011-02-21 01:11:59 -0500 | [diff] [blame] | 945 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 946 | uint32_t ref_div; |
| 947 | |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 948 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 949 | continue; |
| 950 | |
| 951 | /* legacy radeons only have a few post_divs */ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 952 | if (pll->flags & RADEON_PLL_LEGACY) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 953 | if ((post_div == 5) || |
| 954 | (post_div == 7) || |
| 955 | (post_div == 9) || |
| 956 | (post_div == 10) || |
| 957 | (post_div == 11) || |
| 958 | (post_div == 13) || |
| 959 | (post_div == 14) || |
| 960 | (post_div == 15)) |
| 961 | continue; |
| 962 | } |
| 963 | |
| 964 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
| 965 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
| 966 | uint32_t pll_in = pll->reference_freq / ref_div; |
| 967 | uint32_t min_feed_div = pll->min_feedback_div; |
| 968 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
| 969 | |
| 970 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
| 971 | continue; |
| 972 | |
| 973 | while (min_feed_div < max_feed_div) { |
| 974 | uint32_t vco; |
| 975 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
| 976 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
| 977 | uint32_t frac_feedback_div; |
| 978 | uint64_t tmp; |
| 979 | |
| 980 | feedback_div = (min_feed_div + max_feed_div) / 2; |
| 981 | |
| 982 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
| 983 | vco = radeon_div(tmp, ref_div); |
| 984 | |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 985 | if (vco < pll_out_min) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 986 | min_feed_div = feedback_div + 1; |
| 987 | continue; |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 988 | } else if (vco > pll_out_max) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 989 | max_feed_div = feedback_div; |
| 990 | continue; |
| 991 | } |
| 992 | |
| 993 | while (min_frac_feed_div < max_frac_feed_div) { |
| 994 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
| 995 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
| 996 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
| 997 | current_freq = radeon_div(tmp, ref_div * post_div); |
| 998 | |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 999 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
Dan Carpenter | 167ffc4 | 2010-07-17 12:28:02 +0200 | [diff] [blame] | 1000 | if (freq < current_freq) |
| 1001 | error = 0xffffffff; |
| 1002 | else |
| 1003 | error = freq - current_freq; |
Alex Deucher | d0e275a | 2009-07-13 11:08:18 -0400 | [diff] [blame] | 1004 | } else |
| 1005 | error = abs(current_freq - freq); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1006 | vco_diff = abs(vco - best_vco); |
| 1007 | |
| 1008 | if ((best_vco == 0 && error < best_error) || |
| 1009 | (best_vco != 0 && |
Dan Carpenter | 167ffc4 | 2010-07-17 12:28:02 +0200 | [diff] [blame] | 1010 | ((best_error > 100 && error < best_error - 100) || |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 1011 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1012 | best_post_div = post_div; |
| 1013 | best_ref_div = ref_div; |
| 1014 | best_feedback_div = feedback_div; |
| 1015 | best_frac_feedback_div = frac_feedback_div; |
| 1016 | best_freq = current_freq; |
| 1017 | best_error = error; |
| 1018 | best_vco_diff = vco_diff; |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 1019 | } else if (current_freq == freq) { |
| 1020 | if (best_freq == -1) { |
| 1021 | best_post_div = post_div; |
| 1022 | best_ref_div = ref_div; |
| 1023 | best_feedback_div = feedback_div; |
| 1024 | best_frac_feedback_div = frac_feedback_div; |
| 1025 | best_freq = current_freq; |
| 1026 | best_error = error; |
| 1027 | best_vco_diff = vco_diff; |
| 1028 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
| 1029 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
| 1030 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
| 1031 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
| 1032 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
| 1033 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
| 1034 | best_post_div = post_div; |
| 1035 | best_ref_div = ref_div; |
| 1036 | best_feedback_div = feedback_div; |
| 1037 | best_frac_feedback_div = frac_feedback_div; |
| 1038 | best_freq = current_freq; |
| 1039 | best_error = error; |
| 1040 | best_vco_diff = vco_diff; |
| 1041 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1042 | } |
| 1043 | if (current_freq < freq) |
| 1044 | min_frac_feed_div = frac_feedback_div + 1; |
| 1045 | else |
| 1046 | max_frac_feed_div = frac_feedback_div; |
| 1047 | } |
| 1048 | if (current_freq < freq) |
| 1049 | min_feed_div = feedback_div + 1; |
| 1050 | else |
| 1051 | max_feed_div = feedback_div; |
| 1052 | } |
| 1053 | } |
| 1054 | } |
| 1055 | |
| 1056 | *dot_clock_p = best_freq / 10000; |
| 1057 | *fb_div_p = best_feedback_div; |
| 1058 | *frac_fb_div_p = best_frac_feedback_div; |
| 1059 | *ref_div_p = best_ref_div; |
| 1060 | *post_div_p = best_post_div; |
Joe Perches | bbb0aef | 2011-04-17 20:35:52 -0700 | [diff] [blame] | 1061 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
| 1062 | (long long)freq, |
| 1063 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
Alex Deucher | 51d4bf8 | 2011-01-31 16:48:51 -0500 | [diff] [blame] | 1064 | best_ref_div, best_post_div); |
| 1065 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 1069 | { |
| 1070 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1071 | |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 1072 | if (radeon_fb->obj) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1073 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 1074 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1075 | drm_framebuffer_cleanup(fb); |
| 1076 | kfree(radeon_fb); |
| 1077 | } |
| 1078 | |
| 1079 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 1080 | struct drm_file *file_priv, |
| 1081 | unsigned int *handle) |
| 1082 | { |
| 1083 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
| 1084 | |
| 1085 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
| 1086 | } |
| 1087 | |
| 1088 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
| 1089 | .destroy = radeon_user_framebuffer_destroy, |
| 1090 | .create_handle = radeon_user_framebuffer_create_handle, |
| 1091 | }; |
| 1092 | |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1093 | int |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1094 | radeon_framebuffer_init(struct drm_device *dev, |
| 1095 | struct radeon_framebuffer *rfb, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 1096 | struct drm_mode_fb_cmd2 *mode_cmd, |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1097 | struct drm_gem_object *obj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1098 | { |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1099 | int ret; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1100 | rfb->obj = obj; |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1101 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
| 1102 | if (ret) { |
| 1103 | rfb->obj = NULL; |
| 1104 | return ret; |
| 1105 | } |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1106 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1107 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1108 | } |
| 1109 | |
| 1110 | static struct drm_framebuffer * |
| 1111 | radeon_user_framebuffer_create(struct drm_device *dev, |
| 1112 | struct drm_file *file_priv, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 1113 | struct drm_mode_fb_cmd2 *mode_cmd) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1114 | { |
| 1115 | struct drm_gem_object *obj; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1116 | struct radeon_framebuffer *radeon_fb; |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1117 | int ret; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1118 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 1119 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); |
Jerome Glisse | 7e71c9e | 2010-01-17 21:21:41 +0100 | [diff] [blame] | 1120 | if (obj == NULL) { |
| 1121 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 1122 | "can't create framebuffer\n", mode_cmd->handles[0]); |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 1123 | return ERR_PTR(-ENOENT); |
Jerome Glisse | 7e71c9e | 2010-01-17 21:21:41 +0100 | [diff] [blame] | 1124 | } |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1125 | |
| 1126 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 1127 | if (radeon_fb == NULL) |
| 1128 | return ERR_PTR(-ENOMEM); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1129 | |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 1130 | ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); |
| 1131 | if (ret) { |
| 1132 | kfree(radeon_fb); |
| 1133 | drm_gem_object_unreference_unlocked(obj); |
| 1134 | return NULL; |
| 1135 | } |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1136 | |
| 1137 | return &radeon_fb->base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | } |
| 1139 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1140 | static void radeon_output_poll_changed(struct drm_device *dev) |
| 1141 | { |
| 1142 | struct radeon_device *rdev = dev->dev_private; |
| 1143 | radeon_fb_output_poll_changed(rdev); |
| 1144 | } |
| 1145 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1146 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
| 1147 | .fb_create = radeon_user_framebuffer_create, |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1148 | .output_poll_changed = radeon_output_poll_changed |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1149 | }; |
| 1150 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1151 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
| 1152 | { { 0, "driver" }, |
| 1153 | { 1, "bios" }, |
| 1154 | }; |
| 1155 | |
| 1156 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
| 1157 | { { TV_STD_NTSC, "ntsc" }, |
| 1158 | { TV_STD_PAL, "pal" }, |
| 1159 | { TV_STD_PAL_M, "pal-m" }, |
| 1160 | { TV_STD_PAL_60, "pal-60" }, |
| 1161 | { TV_STD_NTSC_J, "ntsc-j" }, |
| 1162 | { TV_STD_SCART_PAL, "scart-pal" }, |
| 1163 | { TV_STD_PAL_CN, "pal-cn" }, |
| 1164 | { TV_STD_SECAM, "secam" }, |
| 1165 | }; |
| 1166 | |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1167 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
| 1168 | { { UNDERSCAN_OFF, "off" }, |
| 1169 | { UNDERSCAN_ON, "on" }, |
| 1170 | { UNDERSCAN_AUTO, "auto" }, |
| 1171 | }; |
| 1172 | |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1173 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1174 | { |
Sascha Hauer | 4a67d39 | 2012-02-06 10:58:17 +0100 | [diff] [blame] | 1175 | int sz; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1176 | |
| 1177 | if (rdev->is_atom_bios) { |
| 1178 | rdev->mode_info.coherent_mode_property = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 1179 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1180 | if (!rdev->mode_info.coherent_mode_property) |
| 1181 | return -ENOMEM; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1182 | } |
| 1183 | |
| 1184 | if (!ASIC_IS_AVIVO(rdev)) { |
| 1185 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
| 1186 | rdev->mode_info.tmds_pll_property = |
Sascha Hauer | 4a67d39 | 2012-02-06 10:58:17 +0100 | [diff] [blame] | 1187 | drm_property_create_enum(rdev->ddev, 0, |
| 1188 | "tmds_pll", |
| 1189 | radeon_tmds_pll_enum_list, sz); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1190 | } |
| 1191 | |
| 1192 | rdev->mode_info.load_detect_property = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 1193 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1194 | if (!rdev->mode_info.load_detect_property) |
| 1195 | return -ENOMEM; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1196 | |
| 1197 | drm_mode_create_scaling_mode_property(rdev->ddev); |
| 1198 | |
| 1199 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
| 1200 | rdev->mode_info.tv_std_property = |
Sascha Hauer | 4a67d39 | 2012-02-06 10:58:17 +0100 | [diff] [blame] | 1201 | drm_property_create_enum(rdev->ddev, 0, |
| 1202 | "tv standard", |
| 1203 | radeon_tv_std_enum_list, sz); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1204 | |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1205 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
| 1206 | rdev->mode_info.underscan_property = |
Sascha Hauer | 4a67d39 | 2012-02-06 10:58:17 +0100 | [diff] [blame] | 1207 | drm_property_create_enum(rdev->ddev, 0, |
| 1208 | "underscan", |
| 1209 | radeon_underscan_enum_list, sz); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1210 | |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1211 | rdev->mode_info.underscan_hborder_property = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 1212 | drm_property_create_range(rdev->ddev, 0, |
| 1213 | "underscan hborder", 0, 128); |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1214 | if (!rdev->mode_info.underscan_hborder_property) |
| 1215 | return -ENOMEM; |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1216 | |
| 1217 | rdev->mode_info.underscan_vborder_property = |
Sascha Hauer | d9bc3c0 | 2012-02-06 10:58:18 +0100 | [diff] [blame] | 1218 | drm_property_create_range(rdev->ddev, 0, |
| 1219 | "underscan vborder", 0, 128); |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1220 | if (!rdev->mode_info.underscan_vborder_property) |
| 1221 | return -ENOMEM; |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1222 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1223 | return 0; |
| 1224 | } |
| 1225 | |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1226 | void radeon_update_display_priority(struct radeon_device *rdev) |
| 1227 | { |
| 1228 | /* adjustment options for the display watermarks */ |
| 1229 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
| 1230 | /* set display priority to high for r3xx, rv515 chips |
| 1231 | * this avoids flickering due to underflow to the |
| 1232 | * display controllers during heavy acceleration. |
Alex Deucher | 4573744 | 2010-05-20 11:26:11 -0400 | [diff] [blame] | 1233 | * Don't force high on rs4xx igp chips as it seems to |
| 1234 | * affect the sound card. See kernel bug 15982. |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1235 | */ |
Alex Deucher | 4573744 | 2010-05-20 11:26:11 -0400 | [diff] [blame] | 1236 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
| 1237 | !(rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1238 | rdev->disp_priority = 2; |
| 1239 | else |
| 1240 | rdev->disp_priority = 0; |
| 1241 | } else |
| 1242 | rdev->disp_priority = radeon_disp_priority; |
| 1243 | |
| 1244 | } |
| 1245 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1246 | int radeon_modeset_init(struct radeon_device *rdev) |
| 1247 | { |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1248 | int i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1249 | int ret; |
| 1250 | |
| 1251 | drm_mode_config_init(rdev->ddev); |
| 1252 | rdev->mode_info.mode_config_initialized = true; |
| 1253 | |
| 1254 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
| 1255 | |
Alex Deucher | 881dd74 | 2011-01-06 21:19:14 -0500 | [diff] [blame] | 1256 | if (ASIC_IS_DCE5(rdev)) { |
| 1257 | rdev->ddev->mode_config.max_width = 16384; |
| 1258 | rdev->ddev->mode_config.max_height = 16384; |
| 1259 | } else if (ASIC_IS_AVIVO(rdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1260 | rdev->ddev->mode_config.max_width = 8192; |
| 1261 | rdev->ddev->mode_config.max_height = 8192; |
| 1262 | } else { |
| 1263 | rdev->ddev->mode_config.max_width = 4096; |
| 1264 | rdev->ddev->mode_config.max_height = 4096; |
| 1265 | } |
| 1266 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 1267 | rdev->ddev->mode_config.preferred_depth = 24; |
| 1268 | rdev->ddev->mode_config.prefer_shadow = 1; |
| 1269 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1270 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
| 1271 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1272 | ret = radeon_modeset_create_props(rdev); |
| 1273 | if (ret) { |
| 1274 | return ret; |
| 1275 | } |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1276 | |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1277 | /* init i2c buses */ |
| 1278 | radeon_i2c_init(rdev); |
| 1279 | |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 1280 | /* check combios for a valid hardcoded EDID - Sun servers */ |
| 1281 | if (!rdev->is_atom_bios) { |
| 1282 | /* check for hardcoded EDID in BIOS */ |
| 1283 | radeon_combios_check_hardcoded_edid(rdev); |
| 1284 | } |
| 1285 | |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1286 | /* allocate crtcs */ |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1287 | for (i = 0; i < rdev->num_crtc; i++) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1288 | radeon_crtc_init(rdev->ddev, i); |
| 1289 | } |
| 1290 | |
| 1291 | /* okay we should have all the bios connectors */ |
| 1292 | ret = radeon_setup_enc_conn(rdev->ddev); |
| 1293 | if (!ret) { |
| 1294 | return ret; |
| 1295 | } |
Alex Deucher | ac89af1 | 2011-05-22 13:20:36 -0400 | [diff] [blame] | 1296 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1297 | /* init dig PHYs, disp eng pll */ |
| 1298 | if (rdev->is_atom_bios) { |
Alex Deucher | ac89af1 | 2011-05-22 13:20:36 -0400 | [diff] [blame] | 1299 | radeon_atom_encoder_init(rdev); |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 1300 | radeon_atom_disp_eng_pll_init(rdev); |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1301 | } |
Alex Deucher | ac89af1 | 2011-05-22 13:20:36 -0400 | [diff] [blame] | 1302 | |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1303 | /* initialize hpd */ |
| 1304 | radeon_hpd_init(rdev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1305 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1306 | /* Initialize power management */ |
| 1307 | radeon_pm_init(rdev); |
| 1308 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1309 | radeon_fbdev_init(rdev); |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1310 | drm_kms_helper_poll_init(rdev->ddev); |
| 1311 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | void radeon_modeset_fini(struct radeon_device *rdev) |
| 1316 | { |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1317 | radeon_fbdev_fini(rdev); |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 1318 | kfree(rdev->mode_info.bios_hardcoded_edid); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1319 | radeon_pm_fini(rdev); |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 1320 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1321 | if (rdev->mode_info.mode_config_initialized) { |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1322 | drm_kms_helper_poll_fini(rdev->ddev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1323 | radeon_hpd_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1324 | drm_mode_config_cleanup(rdev->ddev); |
| 1325 | rdev->mode_info.mode_config_initialized = false; |
| 1326 | } |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1327 | /* free i2c buses */ |
| 1328 | radeon_i2c_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1329 | } |
| 1330 | |
Alex Deucher | 039ed2d | 2010-08-20 11:57:19 -0400 | [diff] [blame] | 1331 | static bool is_hdtv_mode(struct drm_display_mode *mode) |
| 1332 | { |
| 1333 | /* try and guess if this is a tv or a monitor */ |
| 1334 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
| 1335 | (mode->vdisplay == 576) || /* 576p */ |
| 1336 | (mode->vdisplay == 720) || /* 720p */ |
| 1337 | (mode->vdisplay == 1080)) /* 1080p */ |
| 1338 | return true; |
| 1339 | else |
| 1340 | return false; |
| 1341 | } |
| 1342 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1343 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
| 1344 | struct drm_display_mode *mode, |
| 1345 | struct drm_display_mode *adjusted_mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1346 | { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1347 | struct drm_device *dev = crtc->dev; |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1348 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1349 | struct drm_encoder *encoder; |
| 1350 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1351 | struct radeon_encoder *radeon_encoder; |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1352 | struct drm_connector *connector; |
| 1353 | struct radeon_connector *radeon_connector; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1354 | bool first = true; |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1355 | u32 src_v = 1, dst_v = 1; |
| 1356 | u32 src_h = 1, dst_h = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1357 | |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1358 | radeon_crtc->h_border = 0; |
| 1359 | radeon_crtc->v_border = 0; |
| 1360 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1361 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1362 | if (encoder->crtc != crtc) |
| 1363 | continue; |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1364 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1365 | connector = radeon_get_connector_for_encoder(encoder); |
| 1366 | radeon_connector = to_radeon_connector(connector); |
| 1367 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1368 | if (first) { |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 1369 | /* set scaling */ |
| 1370 | if (radeon_encoder->rmx_type == RMX_OFF) |
| 1371 | radeon_crtc->rmx_type = RMX_OFF; |
| 1372 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
| 1373 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
| 1374 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
| 1375 | else |
| 1376 | radeon_crtc->rmx_type = RMX_OFF; |
| 1377 | /* copy native mode */ |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1378 | memcpy(&radeon_crtc->native_mode, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 1379 | &radeon_encoder->native_mode, |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1380 | sizeof(struct drm_display_mode)); |
Alex Deucher | ff32a59 | 2010-09-07 13:26:39 -0400 | [diff] [blame] | 1381 | src_v = crtc->mode.vdisplay; |
| 1382 | dst_v = radeon_crtc->native_mode.vdisplay; |
| 1383 | src_h = crtc->mode.hdisplay; |
| 1384 | dst_h = radeon_crtc->native_mode.hdisplay; |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1385 | |
| 1386 | /* fix up for overscan on hdmi */ |
| 1387 | if (ASIC_IS_AVIVO(rdev) && |
Alex Deucher | e6db0da | 2010-09-10 03:19:05 -0400 | [diff] [blame] | 1388 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1389 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
| 1390 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
Alex Deucher | 039ed2d | 2010-08-20 11:57:19 -0400 | [diff] [blame] | 1391 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
| 1392 | is_hdtv_mode(mode)))) { |
Marius Gröger | 5bccf5e | 2010-09-21 21:30:59 +0200 | [diff] [blame] | 1393 | if (radeon_encoder->underscan_hborder != 0) |
| 1394 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
| 1395 | else |
| 1396 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
| 1397 | if (radeon_encoder->underscan_vborder != 0) |
| 1398 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
| 1399 | else |
| 1400 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 1401 | radeon_crtc->rmx_type = RMX_FULL; |
| 1402 | src_v = crtc->mode.vdisplay; |
| 1403 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
| 1404 | src_h = crtc->mode.hdisplay; |
| 1405 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
| 1406 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1407 | first = false; |
| 1408 | } else { |
| 1409 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
| 1410 | /* WARNING: Right now this can't happen but |
| 1411 | * in the future we need to check that scaling |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1412 | * are consistent across different encoder |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1413 | * (ie all encoder can work with the same |
| 1414 | * scaling). |
| 1415 | */ |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1416 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1417 | return false; |
| 1418 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1419 | } |
| 1420 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1421 | if (radeon_crtc->rmx_type != RMX_OFF) { |
| 1422 | fixed20_12 a, b; |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1423 | a.full = dfixed_const(src_v); |
| 1424 | b.full = dfixed_const(dst_v); |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 1425 | radeon_crtc->vsc.full = dfixed_div(a, b); |
Alex Deucher | d65d65b | 2010-08-03 19:58:49 -0400 | [diff] [blame] | 1426 | a.full = dfixed_const(src_h); |
| 1427 | b.full = dfixed_const(dst_h); |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 1428 | radeon_crtc->hsc.full = dfixed_div(a, b); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1429 | } else { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 1430 | radeon_crtc->vsc.full = dfixed_const(1); |
| 1431 | radeon_crtc->hsc.full = dfixed_const(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1432 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1433 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1434 | } |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1435 | |
| 1436 | /* |
| 1437 | * Retrieve current video scanout position of crtc on a given gpu. |
| 1438 | * |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1439 | * \param dev Device to query. |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1440 | * \param crtc Crtc to query. |
| 1441 | * \param *vpos Location where vertical scanout position should be stored. |
| 1442 | * \param *hpos Location where horizontal scanout position should go. |
| 1443 | * |
| 1444 | * Returns vpos as a positive number while in active scanout area. |
| 1445 | * Returns vpos as a negative number inside vblank, counting the number |
| 1446 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
| 1447 | * until start of active scanout / end of vblank." |
| 1448 | * |
| 1449 | * \return Flags, or'ed together as follows: |
| 1450 | * |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1451 | * DRM_SCANOUTPOS_VALID = Query successful. |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1452 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
| 1453 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1454 | * this flag means that returned position may be offset by a constant but |
| 1455 | * unknown small number of scanlines wrt. real scanout position. |
| 1456 | * |
| 1457 | */ |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1458 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1459 | { |
| 1460 | u32 stat_crtc = 0, vbl = 0, position = 0; |
| 1461 | int vbl_start, vbl_end, vtotal, ret = 0; |
| 1462 | bool in_vbl = true; |
| 1463 | |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1464 | struct radeon_device *rdev = dev->dev_private; |
| 1465 | |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1466 | if (ASIC_IS_DCE4(rdev)) { |
| 1467 | if (crtc == 0) { |
| 1468 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1469 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
| 1470 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1471 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1472 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1473 | } |
| 1474 | if (crtc == 1) { |
| 1475 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1476 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
| 1477 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1478 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1479 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1480 | } |
| 1481 | if (crtc == 2) { |
| 1482 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1483 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
| 1484 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1485 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1486 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1487 | } |
| 1488 | if (crtc == 3) { |
| 1489 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1490 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
| 1491 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1492 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1493 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1494 | } |
| 1495 | if (crtc == 4) { |
| 1496 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1497 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
| 1498 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1499 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1500 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1501 | } |
| 1502 | if (crtc == 5) { |
| 1503 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
| 1504 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
| 1505 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
| 1506 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1507 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1508 | } |
| 1509 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 1510 | if (crtc == 0) { |
| 1511 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
| 1512 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1513 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1514 | } |
| 1515 | if (crtc == 1) { |
| 1516 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
| 1517 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1518 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1519 | } |
| 1520 | } else { |
| 1521 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
| 1522 | if (crtc == 0) { |
| 1523 | /* Assume vbl_end == 0, get vbl_start from |
| 1524 | * upper 16 bits. |
| 1525 | */ |
| 1526 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
| 1527 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
| 1528 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
| 1529 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
| 1530 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
| 1531 | if (!(stat_crtc & 1)) |
| 1532 | in_vbl = false; |
| 1533 | |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1534 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1535 | } |
| 1536 | if (crtc == 1) { |
| 1537 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
| 1538 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
| 1539 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
| 1540 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
| 1541 | if (!(stat_crtc & 1)) |
| 1542 | in_vbl = false; |
| 1543 | |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1544 | ret |= DRM_SCANOUTPOS_VALID; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1545 | } |
| 1546 | } |
| 1547 | |
| 1548 | /* Decode into vertical and horizontal scanout position. */ |
| 1549 | *vpos = position & 0x1fff; |
| 1550 | *hpos = (position >> 16) & 0x1fff; |
| 1551 | |
| 1552 | /* Valid vblank area boundaries from gpu retrieved? */ |
| 1553 | if (vbl > 0) { |
| 1554 | /* Yes: Decode. */ |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1555 | ret |= DRM_SCANOUTPOS_ACCURATE; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1556 | vbl_start = vbl & 0x1fff; |
| 1557 | vbl_end = (vbl >> 16) & 0x1fff; |
| 1558 | } |
| 1559 | else { |
| 1560 | /* No: Fake something reasonable which gives at least ok results. */ |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1561 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1562 | vbl_end = 0; |
| 1563 | } |
| 1564 | |
| 1565 | /* Test scanout position against vblank region. */ |
| 1566 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
| 1567 | in_vbl = false; |
| 1568 | |
| 1569 | /* Check if inside vblank area and apply corrective offsets: |
| 1570 | * vpos will then be >=0 in video scanout area, but negative |
| 1571 | * within vblank area, counting down the number of lines until |
| 1572 | * start of scanout. |
| 1573 | */ |
| 1574 | |
| 1575 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
| 1576 | if (in_vbl && (*vpos >= vbl_start)) { |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1577 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1578 | *vpos = *vpos - vtotal; |
| 1579 | } |
| 1580 | |
| 1581 | /* Correct for shifted end of vbl at vbl_end. */ |
| 1582 | *vpos = *vpos - vbl_end; |
| 1583 | |
| 1584 | /* In vblank? */ |
| 1585 | if (in_vbl) |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 1586 | ret |= DRM_SCANOUTPOS_INVBL; |
Mario Kleiner | 6383cf7 | 2010-10-05 19:57:36 -0400 | [diff] [blame] | 1587 | |
| 1588 | return ret; |
| 1589 | } |