blob: 5ac46f5226f3c5b4b1d35e3450ec922326902896 [file] [log] [blame]
Michael Barkowski0cefeeb2007-05-11 18:24:51 -05001/*
2 * Driver for ICPlus PHYs
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/errno.h>
15#include <linux/unistd.h>
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050016#include <linux/interrupt.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/skbuff.h>
22#include <linux/spinlock.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/mii.h>
26#include <linux/ethtool.h>
27#include <linux/phy.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/uaccess.h>
32
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +000033MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050034MODULE_AUTHOR("Michael Barkowski");
35MODULE_LICENSE("GPL");
36
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +000037/* IP101A/G - IP1001 */
38#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
39#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
40#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
41#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
42#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
Giuseppe CAVALLARO996f7392012-04-17 21:16:40 +000043#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +000044
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050045static int ip175c_config_init(struct phy_device *phydev)
46{
47 int err, i;
48 static int full_reset_performed = 0;
49
50 if (full_reset_performed == 0) {
51
52 /* master reset */
David Daney76231e02011-09-30 12:17:48 +000053 err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050054 if (err < 0)
55 return err;
56
57 /* ensure no bus delays overlap reset period */
David Daney76231e02011-09-30 12:17:48 +000058 err = mdiobus_read(phydev->bus, 30, 0);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050059
60 /* data sheet specifies reset period is 2 msec */
61 mdelay(2);
62
63 /* enable IP175C mode */
David Daney76231e02011-09-30 12:17:48 +000064 err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050065 if (err < 0)
66 return err;
67
68 /* Set MII0 speed and duplex (in PHY mode) */
David Daney76231e02011-09-30 12:17:48 +000069 err = mdiobus_write(phydev->bus, 29, 22, 0x420);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050070 if (err < 0)
71 return err;
72
73 /* reset switch ports */
74 for (i = 0; i < 5; i++) {
David Daney76231e02011-09-30 12:17:48 +000075 err = mdiobus_write(phydev->bus, i,
76 MII_BMCR, BMCR_RESET);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050077 if (err < 0)
78 return err;
79 }
80
81 for (i = 0; i < 5; i++)
David Daney76231e02011-09-30 12:17:48 +000082 err = mdiobus_read(phydev->bus, i, MII_BMCR);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050083
84 mdelay(2);
85
86 full_reset_performed = 1;
87 }
88
89 if (phydev->addr != 4) {
90 phydev->state = PHY_RUNNING;
91 phydev->speed = SPEED_100;
92 phydev->duplex = DUPLEX_FULL;
93 phydev->link = 1;
94 netif_carrier_on(phydev->attached_dev);
95 }
96
97 return 0;
98}
99
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000100static int ip1xx_reset(struct phy_device *phydev)
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000101{
David McKayb8e39952012-02-21 21:24:57 +0000102 int bmcr;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000103
104 /* Software Reset PHY */
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000105 bmcr = phy_read(phydev, MII_BMCR);
David McKayb8e39952012-02-21 21:24:57 +0000106 if (bmcr < 0)
107 return bmcr;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000108 bmcr |= BMCR_RESET;
David McKayb8e39952012-02-21 21:24:57 +0000109 bmcr = phy_write(phydev, MII_BMCR, bmcr);
110 if (bmcr < 0)
111 return bmcr;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000112
113 do {
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000114 bmcr = phy_read(phydev, MII_BMCR);
David McKayb8e39952012-02-21 21:24:57 +0000115 if (bmcr < 0)
116 return bmcr;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000117 } while (bmcr & BMCR_RESET);
118
David McKayb8e39952012-02-21 21:24:57 +0000119 return 0;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000120}
121
122static int ip1001_config_init(struct phy_device *phydev)
123{
124 int c;
125
126 c = ip1xx_reset(phydev);
127 if (c < 0)
128 return c;
129
130 /* Enable Auto Power Saving mode */
131 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
David McKayb8e39952012-02-21 21:24:57 +0000132 if (c < 0)
133 return c;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000134 c |= IP1001_APS_ON;
David McKayb8e39952012-02-21 21:24:57 +0000135 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000136 if (c < 0)
137 return c;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000138
Giuseppe CAVALLAROa4886d52011-10-10 21:37:56 +0000139 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
140 /* Additional delay (2ns) used to adjust RX clock phase
141 * at RGMII interface */
142 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
David McKayb8e39952012-02-21 21:24:57 +0000143 if (c < 0)
144 return c;
145
Giuseppe CAVALLAROa4886d52011-10-10 21:37:56 +0000146 c |= IP1001_PHASE_SEL_MASK;
147 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
David McKayb8e39952012-02-21 21:24:57 +0000148 if (c < 0)
149 return c;
Giuseppe CAVALLAROa4886d52011-10-10 21:37:56 +0000150 }
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000151
David McKayb8e39952012-02-21 21:24:57 +0000152 return 0;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000153}
154
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000155static int ip101a_g_config_init(struct phy_device *phydev)
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000156{
157 int c;
158
159 c = ip1xx_reset(phydev);
160 if (c < 0)
161 return c;
162
163 /* Enable Auto Power Saving mode */
164 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000165 c |= IP101A_G_APS_ON;
Srinivas Kandagatlab3300142012-04-02 00:02:09 +0000166
167 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000168}
169
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500170static int ip175c_read_status(struct phy_device *phydev)
171{
172 if (phydev->addr == 4) /* WAN port */
173 genphy_read_status(phydev);
174 else
175 /* Don't need to read status for switch ports */
176 phydev->irq = PHY_IGNORE_INTERRUPT;
177
178 return 0;
179}
180
181static int ip175c_config_aneg(struct phy_device *phydev)
182{
183 if (phydev->addr == 4) /* WAN port */
184 genphy_config_aneg(phydev);
185
186 return 0;
187}
188
Giuseppe CAVALLARO996f7392012-04-17 21:16:40 +0000189static int ip101a_g_ack_interrupt(struct phy_device *phydev)
190{
191 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
192 if (err < 0)
193 return err;
194
195 return 0;
196}
197
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500198static struct phy_driver ip175c_driver = {
199 .phy_id = 0x02430d80,
200 .name = "ICPlus IP175C",
201 .phy_id_mask = 0x0ffffff0,
202 .features = PHY_BASIC_FEATURES,
203 .config_init = &ip175c_config_init,
204 .config_aneg = &ip175c_config_aneg,
205 .read_status = &ip175c_read_status,
Giuseppe Cavallarodab10862010-07-20 13:24:25 -0700206 .suspend = genphy_suspend,
207 .resume = genphy_resume,
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500208 .driver = { .owner = THIS_MODULE,},
209};
210
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000211static struct phy_driver ip1001_driver = {
212 .phy_id = 0x02430d90,
213 .name = "ICPlus IP1001",
214 .phy_id_mask = 0x0ffffff0,
215 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
216 SUPPORTED_Asym_Pause,
217 .config_init = &ip1001_config_init,
218 .config_aneg = &genphy_config_aneg,
219 .read_status = &genphy_read_status,
220 .suspend = genphy_suspend,
221 .resume = genphy_resume,
222 .driver = { .owner = THIS_MODULE,},
223};
224
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000225static struct phy_driver ip101a_g_driver = {
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000226 .phy_id = 0x02430c54,
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000227 .name = "ICPlus IP101A/G",
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000228 .phy_id_mask = 0x0ffffff0,
229 .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
230 SUPPORTED_Asym_Pause,
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000231 .flags = PHY_HAS_INTERRUPT,
Giuseppe CAVALLARO996f7392012-04-17 21:16:40 +0000232 .ack_interrupt = ip101a_g_ack_interrupt,
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000233 .config_init = &ip101a_g_config_init,
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000234 .config_aneg = &genphy_config_aneg,
235 .read_status = &genphy_read_status,
236 .suspend = genphy_suspend,
237 .resume = genphy_resume,
238 .driver = { .owner = THIS_MODULE,},
239};
240
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000241static int __init icplus_init(void)
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500242{
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000243 int ret = 0;
244
245 ret = phy_driver_register(&ip1001_driver);
246 if (ret < 0)
247 return -ENODEV;
248
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000249 ret = phy_driver_register(&ip101a_g_driver);
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000250 if (ret < 0)
251 return -ENODEV;
252
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500253 return phy_driver_register(&ip175c_driver);
254}
255
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000256static void __exit icplus_exit(void)
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500257{
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000258 phy_driver_unregister(&ip1001_driver);
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000259 phy_driver_unregister(&ip101a_g_driver);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500260 phy_driver_unregister(&ip175c_driver);
261}
262
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000263module_init(icplus_init);
264module_exit(icplus_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000265
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000266static struct mdio_device_id __maybe_unused icplus_tbl[] = {
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000267 { 0x02430d80, 0x0ffffff0 },
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000268 { 0x02430d90, 0x0ffffff0 },
Giuseppe CAVALLAROe3e09f22012-02-21 21:26:28 +0000269 { 0x02430c54, 0x0ffffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000270 { }
271};
272
273MODULE_DEVICE_TABLE(mdio, icplus_tbl);