Afzal Mohammed | 2664946 | 2013-10-12 15:44:46 +0530 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright (C) 2013 Texas Instruments Incorporated |
| 4 | * |
| 5 | * Interconnects common for AM335x and AM43x |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation version 2. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/sizes.h> |
| 18 | #include "omap_hwmod.h" |
| 19 | #include "omap_hwmod_33xx_43xx_common_data.h" |
| 20 | |
| 21 | /* mpu -> l3 main */ |
| 22 | struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { |
| 23 | .master = &am33xx_mpu_hwmod, |
| 24 | .slave = &am33xx_l3_main_hwmod, |
| 25 | .clk = "dpll_mpu_m2_ck", |
| 26 | .user = OCP_USER_MPU, |
| 27 | }; |
| 28 | |
| 29 | /* l3 main -> l3 s */ |
| 30 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { |
| 31 | .master = &am33xx_l3_main_hwmod, |
| 32 | .slave = &am33xx_l3_s_hwmod, |
| 33 | .clk = "l3s_gclk", |
| 34 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 35 | }; |
| 36 | |
| 37 | /* l3 s -> l4 per/ls */ |
| 38 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { |
| 39 | .master = &am33xx_l3_s_hwmod, |
| 40 | .slave = &am33xx_l4_ls_hwmod, |
| 41 | .clk = "l3s_gclk", |
| 42 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 43 | }; |
| 44 | |
| 45 | /* l3 s -> l4 wkup */ |
| 46 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { |
| 47 | .master = &am33xx_l3_s_hwmod, |
| 48 | .slave = &am33xx_l4_wkup_hwmod, |
| 49 | .clk = "l3s_gclk", |
| 50 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 51 | }; |
| 52 | |
| 53 | /* l3 main -> l3 instr */ |
| 54 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { |
| 55 | .master = &am33xx_l3_main_hwmod, |
| 56 | .slave = &am33xx_l3_instr_hwmod, |
| 57 | .clk = "l3s_gclk", |
| 58 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 59 | }; |
| 60 | |
| 61 | /* mpu -> prcm */ |
| 62 | struct omap_hwmod_ocp_if am33xx_mpu__prcm = { |
| 63 | .master = &am33xx_mpu_hwmod, |
| 64 | .slave = &am33xx_prcm_hwmod, |
| 65 | .clk = "dpll_mpu_m2_ck", |
| 66 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 67 | }; |
| 68 | |
| 69 | /* l3 s -> l3 main*/ |
| 70 | struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { |
| 71 | .master = &am33xx_l3_s_hwmod, |
| 72 | .slave = &am33xx_l3_main_hwmod, |
| 73 | .clk = "l3s_gclk", |
| 74 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 75 | }; |
| 76 | |
| 77 | /* pru-icss -> l3 main */ |
| 78 | struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { |
| 79 | .master = &am33xx_pruss_hwmod, |
| 80 | .slave = &am33xx_l3_main_hwmod, |
| 81 | .clk = "l3_gclk", |
| 82 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 83 | }; |
| 84 | |
| 85 | /* gfx -> l3 main */ |
| 86 | struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { |
| 87 | .master = &am33xx_gfx_hwmod, |
| 88 | .slave = &am33xx_l3_main_hwmod, |
| 89 | .clk = "dpll_core_m4_ck", |
| 90 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 91 | }; |
| 92 | |
| 93 | /* l3 main -> gfx */ |
| 94 | struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { |
| 95 | .master = &am33xx_l3_main_hwmod, |
| 96 | .slave = &am33xx_gfx_hwmod, |
| 97 | .clk = "dpll_core_m4_ck", |
| 98 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 99 | }; |
| 100 | |
| 101 | /* l4 wkup -> rtc */ |
| 102 | struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { |
| 103 | .master = &am33xx_l4_wkup_hwmod, |
| 104 | .slave = &am33xx_rtc_hwmod, |
| 105 | .clk = "clkdiv32k_ick", |
| 106 | .user = OCP_USER_MPU, |
| 107 | }; |
| 108 | |
| 109 | /* l4 per/ls -> DCAN0 */ |
| 110 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { |
| 111 | .master = &am33xx_l4_ls_hwmod, |
| 112 | .slave = &am33xx_dcan0_hwmod, |
| 113 | .clk = "l4ls_gclk", |
| 114 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 115 | }; |
| 116 | |
| 117 | /* l4 per/ls -> DCAN1 */ |
| 118 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { |
| 119 | .master = &am33xx_l4_ls_hwmod, |
| 120 | .slave = &am33xx_dcan1_hwmod, |
| 121 | .clk = "l4ls_gclk", |
| 122 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 123 | }; |
| 124 | |
| 125 | /* l4 per/ls -> GPIO2 */ |
| 126 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { |
| 127 | .master = &am33xx_l4_ls_hwmod, |
| 128 | .slave = &am33xx_gpio1_hwmod, |
| 129 | .clk = "l4ls_gclk", |
| 130 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 131 | }; |
| 132 | |
| 133 | /* l4 per/ls -> gpio3 */ |
| 134 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { |
| 135 | .master = &am33xx_l4_ls_hwmod, |
| 136 | .slave = &am33xx_gpio2_hwmod, |
| 137 | .clk = "l4ls_gclk", |
| 138 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 139 | }; |
| 140 | |
| 141 | /* l4 per/ls -> gpio4 */ |
| 142 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { |
| 143 | .master = &am33xx_l4_ls_hwmod, |
| 144 | .slave = &am33xx_gpio3_hwmod, |
| 145 | .clk = "l4ls_gclk", |
| 146 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 147 | }; |
| 148 | |
| 149 | struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { |
| 150 | .master = &am33xx_cpgmac0_hwmod, |
| 151 | .slave = &am33xx_mdio_hwmod, |
| 152 | .user = OCP_USER_MPU, |
| 153 | }; |
| 154 | |
| 155 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { |
| 156 | { |
| 157 | .pa_start = 0x48080000, |
| 158 | .pa_end = 0x48080000 + SZ_8K - 1, |
| 159 | .flags = ADDR_TYPE_RT |
| 160 | }, |
| 161 | { } |
| 162 | }; |
| 163 | |
| 164 | struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { |
| 165 | .master = &am33xx_l4_ls_hwmod, |
| 166 | .slave = &am33xx_elm_hwmod, |
| 167 | .clk = "l4ls_gclk", |
| 168 | .addr = am33xx_elm_addr_space, |
| 169 | .user = OCP_USER_MPU, |
| 170 | }; |
| 171 | |
| 172 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { |
| 173 | { |
| 174 | .pa_start = 0x48300000, |
| 175 | .pa_end = 0x48300000 + SZ_16 - 1, |
| 176 | .flags = ADDR_TYPE_RT |
| 177 | }, |
| 178 | { } |
| 179 | }; |
| 180 | |
| 181 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { |
| 182 | .master = &am33xx_l4_ls_hwmod, |
| 183 | .slave = &am33xx_epwmss0_hwmod, |
| 184 | .clk = "l4ls_gclk", |
| 185 | .addr = am33xx_epwmss0_addr_space, |
| 186 | .user = OCP_USER_MPU, |
| 187 | }; |
| 188 | |
| 189 | struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { |
| 190 | .master = &am33xx_epwmss0_hwmod, |
| 191 | .slave = &am33xx_ecap0_hwmod, |
| 192 | .clk = "l4ls_gclk", |
| 193 | .user = OCP_USER_MPU, |
| 194 | }; |
| 195 | |
| 196 | struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { |
| 197 | .master = &am33xx_epwmss0_hwmod, |
| 198 | .slave = &am33xx_eqep0_hwmod, |
| 199 | .clk = "l4ls_gclk", |
| 200 | .user = OCP_USER_MPU, |
| 201 | }; |
| 202 | |
| 203 | struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { |
| 204 | .master = &am33xx_epwmss0_hwmod, |
| 205 | .slave = &am33xx_ehrpwm0_hwmod, |
| 206 | .clk = "l4ls_gclk", |
| 207 | .user = OCP_USER_MPU, |
| 208 | }; |
| 209 | |
| 210 | |
| 211 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { |
| 212 | { |
| 213 | .pa_start = 0x48302000, |
| 214 | .pa_end = 0x48302000 + SZ_16 - 1, |
| 215 | .flags = ADDR_TYPE_RT |
| 216 | }, |
| 217 | { } |
| 218 | }; |
| 219 | |
| 220 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { |
| 221 | .master = &am33xx_l4_ls_hwmod, |
| 222 | .slave = &am33xx_epwmss1_hwmod, |
| 223 | .clk = "l4ls_gclk", |
| 224 | .addr = am33xx_epwmss1_addr_space, |
| 225 | .user = OCP_USER_MPU, |
| 226 | }; |
| 227 | |
| 228 | struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { |
| 229 | .master = &am33xx_epwmss1_hwmod, |
| 230 | .slave = &am33xx_ecap1_hwmod, |
| 231 | .clk = "l4ls_gclk", |
| 232 | .user = OCP_USER_MPU, |
| 233 | }; |
| 234 | |
| 235 | struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { |
| 236 | .master = &am33xx_epwmss1_hwmod, |
| 237 | .slave = &am33xx_eqep1_hwmod, |
| 238 | .clk = "l4ls_gclk", |
| 239 | .user = OCP_USER_MPU, |
| 240 | }; |
| 241 | |
| 242 | struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { |
| 243 | .master = &am33xx_epwmss1_hwmod, |
| 244 | .slave = &am33xx_ehrpwm1_hwmod, |
| 245 | .clk = "l4ls_gclk", |
| 246 | .user = OCP_USER_MPU, |
| 247 | }; |
| 248 | |
| 249 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { |
| 250 | { |
| 251 | .pa_start = 0x48304000, |
| 252 | .pa_end = 0x48304000 + SZ_16 - 1, |
| 253 | .flags = ADDR_TYPE_RT |
| 254 | }, |
| 255 | { } |
| 256 | }; |
| 257 | |
| 258 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { |
| 259 | .master = &am33xx_l4_ls_hwmod, |
| 260 | .slave = &am33xx_epwmss2_hwmod, |
| 261 | .clk = "l4ls_gclk", |
| 262 | .addr = am33xx_epwmss2_addr_space, |
| 263 | .user = OCP_USER_MPU, |
| 264 | }; |
| 265 | |
| 266 | struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { |
| 267 | .master = &am33xx_epwmss2_hwmod, |
| 268 | .slave = &am33xx_ecap2_hwmod, |
| 269 | .clk = "l4ls_gclk", |
| 270 | .user = OCP_USER_MPU, |
| 271 | }; |
| 272 | |
| 273 | struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { |
| 274 | .master = &am33xx_epwmss2_hwmod, |
| 275 | .slave = &am33xx_eqep2_hwmod, |
| 276 | .clk = "l4ls_gclk", |
| 277 | .user = OCP_USER_MPU, |
| 278 | }; |
| 279 | |
| 280 | struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { |
| 281 | .master = &am33xx_epwmss2_hwmod, |
| 282 | .slave = &am33xx_ehrpwm2_hwmod, |
| 283 | .clk = "l4ls_gclk", |
| 284 | .user = OCP_USER_MPU, |
| 285 | }; |
| 286 | |
| 287 | /* l3s cfg -> gpmc */ |
| 288 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { |
| 289 | { |
| 290 | .pa_start = 0x50000000, |
| 291 | .pa_end = 0x50000000 + SZ_8K - 1, |
| 292 | .flags = ADDR_TYPE_RT, |
| 293 | }, |
| 294 | { } |
| 295 | }; |
| 296 | |
| 297 | struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { |
| 298 | .master = &am33xx_l3_s_hwmod, |
| 299 | .slave = &am33xx_gpmc_hwmod, |
| 300 | .clk = "l3s_gclk", |
| 301 | .addr = am33xx_gpmc_addr_space, |
| 302 | .user = OCP_USER_MPU, |
| 303 | }; |
| 304 | |
| 305 | /* i2c2 */ |
| 306 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { |
| 307 | .master = &am33xx_l4_ls_hwmod, |
| 308 | .slave = &am33xx_i2c2_hwmod, |
| 309 | .clk = "l4ls_gclk", |
| 310 | .user = OCP_USER_MPU, |
| 311 | }; |
| 312 | |
| 313 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { |
| 314 | .master = &am33xx_l4_ls_hwmod, |
| 315 | .slave = &am33xx_i2c3_hwmod, |
| 316 | .clk = "l4ls_gclk", |
| 317 | .user = OCP_USER_MPU, |
| 318 | }; |
| 319 | |
| 320 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { |
| 321 | { |
| 322 | .pa_start = 0x480C8000, |
| 323 | .pa_end = 0x480C8000 + (SZ_4K - 1), |
| 324 | .flags = ADDR_TYPE_RT |
| 325 | }, |
| 326 | { } |
| 327 | }; |
| 328 | |
| 329 | /* l4 ls -> mailbox */ |
| 330 | struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { |
| 331 | .master = &am33xx_l4_ls_hwmod, |
| 332 | .slave = &am33xx_mailbox_hwmod, |
| 333 | .clk = "l4ls_gclk", |
| 334 | .addr = am33xx_mailbox_addrs, |
| 335 | .user = OCP_USER_MPU, |
| 336 | }; |
| 337 | |
| 338 | /* l4 ls -> spinlock */ |
| 339 | struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { |
| 340 | .master = &am33xx_l4_ls_hwmod, |
| 341 | .slave = &am33xx_spinlock_hwmod, |
| 342 | .clk = "l4ls_gclk", |
| 343 | .user = OCP_USER_MPU, |
| 344 | }; |
| 345 | |
| 346 | /* l4 ls -> mcasp0 */ |
| 347 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { |
| 348 | { |
| 349 | .pa_start = 0x48038000, |
| 350 | .pa_end = 0x48038000 + SZ_8K - 1, |
| 351 | .flags = ADDR_TYPE_RT |
| 352 | }, |
| 353 | { } |
| 354 | }; |
| 355 | |
| 356 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { |
| 357 | .master = &am33xx_l4_ls_hwmod, |
| 358 | .slave = &am33xx_mcasp0_hwmod, |
| 359 | .clk = "l4ls_gclk", |
| 360 | .addr = am33xx_mcasp0_addr_space, |
| 361 | .user = OCP_USER_MPU, |
| 362 | }; |
| 363 | |
| 364 | /* l4 ls -> mcasp1 */ |
| 365 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { |
| 366 | { |
| 367 | .pa_start = 0x4803C000, |
| 368 | .pa_end = 0x4803C000 + SZ_8K - 1, |
| 369 | .flags = ADDR_TYPE_RT |
| 370 | }, |
| 371 | { } |
| 372 | }; |
| 373 | |
| 374 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { |
| 375 | .master = &am33xx_l4_ls_hwmod, |
| 376 | .slave = &am33xx_mcasp1_hwmod, |
| 377 | .clk = "l4ls_gclk", |
| 378 | .addr = am33xx_mcasp1_addr_space, |
| 379 | .user = OCP_USER_MPU, |
| 380 | }; |
| 381 | |
| 382 | /* l4 ls -> mmc0 */ |
| 383 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { |
| 384 | { |
| 385 | .pa_start = 0x48060100, |
| 386 | .pa_end = 0x48060100 + SZ_4K - 1, |
| 387 | .flags = ADDR_TYPE_RT, |
| 388 | }, |
| 389 | { } |
| 390 | }; |
| 391 | |
| 392 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { |
| 393 | .master = &am33xx_l4_ls_hwmod, |
| 394 | .slave = &am33xx_mmc0_hwmod, |
| 395 | .clk = "l4ls_gclk", |
| 396 | .addr = am33xx_mmc0_addr_space, |
| 397 | .user = OCP_USER_MPU, |
| 398 | }; |
| 399 | |
| 400 | /* l4 ls -> mmc1 */ |
| 401 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { |
| 402 | { |
| 403 | .pa_start = 0x481d8100, |
| 404 | .pa_end = 0x481d8100 + SZ_4K - 1, |
| 405 | .flags = ADDR_TYPE_RT, |
| 406 | }, |
| 407 | { } |
| 408 | }; |
| 409 | |
| 410 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { |
| 411 | .master = &am33xx_l4_ls_hwmod, |
| 412 | .slave = &am33xx_mmc1_hwmod, |
| 413 | .clk = "l4ls_gclk", |
| 414 | .addr = am33xx_mmc1_addr_space, |
| 415 | .user = OCP_USER_MPU, |
| 416 | }; |
| 417 | |
| 418 | /* l3 s -> mmc2 */ |
| 419 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { |
| 420 | { |
| 421 | .pa_start = 0x47810100, |
| 422 | .pa_end = 0x47810100 + SZ_64K - 1, |
| 423 | .flags = ADDR_TYPE_RT, |
| 424 | }, |
| 425 | { } |
| 426 | }; |
| 427 | |
| 428 | struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { |
| 429 | .master = &am33xx_l3_s_hwmod, |
| 430 | .slave = &am33xx_mmc2_hwmod, |
| 431 | .clk = "l3s_gclk", |
| 432 | .addr = am33xx_mmc2_addr_space, |
| 433 | .user = OCP_USER_MPU, |
| 434 | }; |
| 435 | |
| 436 | /* l4 ls -> mcspi0 */ |
| 437 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { |
| 438 | .master = &am33xx_l4_ls_hwmod, |
| 439 | .slave = &am33xx_spi0_hwmod, |
| 440 | .clk = "l4ls_gclk", |
| 441 | .user = OCP_USER_MPU, |
| 442 | }; |
| 443 | |
| 444 | /* l4 ls -> mcspi1 */ |
| 445 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { |
| 446 | .master = &am33xx_l4_ls_hwmod, |
| 447 | .slave = &am33xx_spi1_hwmod, |
| 448 | .clk = "l4ls_gclk", |
| 449 | .user = OCP_USER_MPU, |
| 450 | }; |
| 451 | |
| 452 | /* l4 per -> timer2 */ |
| 453 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { |
| 454 | .master = &am33xx_l4_ls_hwmod, |
| 455 | .slave = &am33xx_timer2_hwmod, |
| 456 | .clk = "l4ls_gclk", |
| 457 | .user = OCP_USER_MPU, |
| 458 | }; |
| 459 | |
| 460 | /* l4 per -> timer3 */ |
| 461 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { |
| 462 | .master = &am33xx_l4_ls_hwmod, |
| 463 | .slave = &am33xx_timer3_hwmod, |
| 464 | .clk = "l4ls_gclk", |
| 465 | .user = OCP_USER_MPU, |
| 466 | }; |
| 467 | |
| 468 | /* l4 per -> timer4 */ |
| 469 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { |
| 470 | .master = &am33xx_l4_ls_hwmod, |
| 471 | .slave = &am33xx_timer4_hwmod, |
| 472 | .clk = "l4ls_gclk", |
| 473 | .user = OCP_USER_MPU, |
| 474 | }; |
| 475 | |
| 476 | /* l4 per -> timer5 */ |
| 477 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { |
| 478 | .master = &am33xx_l4_ls_hwmod, |
| 479 | .slave = &am33xx_timer5_hwmod, |
| 480 | .clk = "l4ls_gclk", |
| 481 | .user = OCP_USER_MPU, |
| 482 | }; |
| 483 | |
| 484 | /* l4 per -> timer6 */ |
| 485 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { |
| 486 | .master = &am33xx_l4_ls_hwmod, |
| 487 | .slave = &am33xx_timer6_hwmod, |
| 488 | .clk = "l4ls_gclk", |
| 489 | .user = OCP_USER_MPU, |
| 490 | }; |
| 491 | |
| 492 | /* l4 per -> timer7 */ |
| 493 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { |
| 494 | .master = &am33xx_l4_ls_hwmod, |
| 495 | .slave = &am33xx_timer7_hwmod, |
| 496 | .clk = "l4ls_gclk", |
| 497 | .user = OCP_USER_MPU, |
| 498 | }; |
| 499 | |
| 500 | /* l3 main -> tpcc */ |
| 501 | struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { |
| 502 | .master = &am33xx_l3_main_hwmod, |
| 503 | .slave = &am33xx_tpcc_hwmod, |
| 504 | .clk = "l3_gclk", |
| 505 | .user = OCP_USER_MPU, |
| 506 | }; |
| 507 | |
| 508 | /* l3 main -> tpcc0 */ |
| 509 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { |
| 510 | { |
| 511 | .pa_start = 0x49800000, |
| 512 | .pa_end = 0x49800000 + SZ_8K - 1, |
| 513 | .flags = ADDR_TYPE_RT, |
| 514 | }, |
| 515 | { } |
| 516 | }; |
| 517 | |
| 518 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { |
| 519 | .master = &am33xx_l3_main_hwmod, |
| 520 | .slave = &am33xx_tptc0_hwmod, |
| 521 | .clk = "l3_gclk", |
| 522 | .addr = am33xx_tptc0_addr_space, |
| 523 | .user = OCP_USER_MPU, |
| 524 | }; |
| 525 | |
| 526 | /* l3 main -> tpcc1 */ |
| 527 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { |
| 528 | { |
| 529 | .pa_start = 0x49900000, |
| 530 | .pa_end = 0x49900000 + SZ_8K - 1, |
| 531 | .flags = ADDR_TYPE_RT, |
| 532 | }, |
| 533 | { } |
| 534 | }; |
| 535 | |
| 536 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { |
| 537 | .master = &am33xx_l3_main_hwmod, |
| 538 | .slave = &am33xx_tptc1_hwmod, |
| 539 | .clk = "l3_gclk", |
| 540 | .addr = am33xx_tptc1_addr_space, |
| 541 | .user = OCP_USER_MPU, |
| 542 | }; |
| 543 | |
| 544 | /* l3 main -> tpcc2 */ |
| 545 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { |
| 546 | { |
| 547 | .pa_start = 0x49a00000, |
| 548 | .pa_end = 0x49a00000 + SZ_8K - 1, |
| 549 | .flags = ADDR_TYPE_RT, |
| 550 | }, |
| 551 | { } |
| 552 | }; |
| 553 | |
| 554 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { |
| 555 | .master = &am33xx_l3_main_hwmod, |
| 556 | .slave = &am33xx_tptc2_hwmod, |
| 557 | .clk = "l3_gclk", |
| 558 | .addr = am33xx_tptc2_addr_space, |
| 559 | .user = OCP_USER_MPU, |
| 560 | }; |
| 561 | |
| 562 | /* l4 ls -> uart2 */ |
| 563 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { |
| 564 | .master = &am33xx_l4_ls_hwmod, |
| 565 | .slave = &am33xx_uart2_hwmod, |
| 566 | .clk = "l4ls_gclk", |
| 567 | .user = OCP_USER_MPU, |
| 568 | }; |
| 569 | |
| 570 | /* l4 ls -> uart3 */ |
| 571 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { |
| 572 | .master = &am33xx_l4_ls_hwmod, |
| 573 | .slave = &am33xx_uart3_hwmod, |
| 574 | .clk = "l4ls_gclk", |
| 575 | .user = OCP_USER_MPU, |
| 576 | }; |
| 577 | |
| 578 | /* l4 ls -> uart4 */ |
| 579 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { |
| 580 | .master = &am33xx_l4_ls_hwmod, |
| 581 | .slave = &am33xx_uart4_hwmod, |
| 582 | .clk = "l4ls_gclk", |
| 583 | .user = OCP_USER_MPU, |
| 584 | }; |
| 585 | |
| 586 | /* l4 ls -> uart5 */ |
| 587 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { |
| 588 | .master = &am33xx_l4_ls_hwmod, |
| 589 | .slave = &am33xx_uart5_hwmod, |
| 590 | .clk = "l4ls_gclk", |
| 591 | .user = OCP_USER_MPU, |
| 592 | }; |
| 593 | |
| 594 | /* l4 ls -> uart6 */ |
| 595 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { |
| 596 | .master = &am33xx_l4_ls_hwmod, |
| 597 | .slave = &am33xx_uart6_hwmod, |
| 598 | .clk = "l4ls_gclk", |
| 599 | .user = OCP_USER_MPU, |
| 600 | }; |
| 601 | |
| 602 | /* l3 main -> ocmc */ |
| 603 | struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { |
| 604 | .master = &am33xx_l3_main_hwmod, |
| 605 | .slave = &am33xx_ocmcram_hwmod, |
| 606 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 607 | }; |
| 608 | |
| 609 | /* l3 main -> sha0 HIB2 */ |
| 610 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { |
| 611 | { |
| 612 | .pa_start = 0x53100000, |
| 613 | .pa_end = 0x53100000 + SZ_512 - 1, |
| 614 | .flags = ADDR_TYPE_RT |
| 615 | }, |
| 616 | { } |
| 617 | }; |
| 618 | |
| 619 | struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { |
| 620 | .master = &am33xx_l3_main_hwmod, |
| 621 | .slave = &am33xx_sha0_hwmod, |
| 622 | .clk = "sha0_fck", |
| 623 | .addr = am33xx_sha0_addrs, |
| 624 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 625 | }; |
| 626 | |
| 627 | /* l3 main -> AES0 HIB2 */ |
| 628 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { |
| 629 | { |
| 630 | .pa_start = 0x53500000, |
| 631 | .pa_end = 0x53500000 + SZ_1M - 1, |
| 632 | .flags = ADDR_TYPE_RT |
| 633 | }, |
| 634 | { } |
| 635 | }; |
| 636 | |
| 637 | struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { |
| 638 | .master = &am33xx_l3_main_hwmod, |
| 639 | .slave = &am33xx_aes0_hwmod, |
| 640 | .clk = "aes0_fck", |
| 641 | .addr = am33xx_aes0_addrs, |
| 642 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 643 | }; |