Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 6 | * Paul Walmsley |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 14 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 15 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 16 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 17 | #include <plat/cpu.h> |
| 18 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 19 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 20 | #include <plat/i2c.h> |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 21 | #include <plat/gpio.h> |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 22 | #include <plat/mcbsp.h> |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 23 | #include <plat/mcspi.h> |
Thara Gopinath | b6b5822 | 2011-02-23 00:14:05 -0700 | [diff] [blame] | 24 | #include <plat/dmtimer.h> |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 25 | #include <plat/mmc.h> |
Senthilvadivu Guruswamy | de56dbb | 2011-02-22 09:51:15 +0200 | [diff] [blame] | 26 | #include <plat/l3_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 27 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 28 | #include "omap_hwmod_common_data.h" |
| 29 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 30 | #include "prm-regbits-24xx.h" |
Varadarajan, Charulatha | 165e216 | 2010-09-23 20:02:40 +0530 | [diff] [blame] | 31 | #include "cm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 32 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 33 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 34 | /* |
| 35 | * OMAP2430 hardware module integration data |
| 36 | * |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 37 | * All of the data in this section should be autogeneratable from the |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 38 | * TI hardware database or other technical documentation. Data that |
| 39 | * is driver-specific or driver-kernel integration-specific belongs |
| 40 | * elsewhere. |
| 41 | */ |
| 42 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 43 | /* |
| 44 | * IP blocks |
| 45 | */ |
Senthilvadivu Guruswamy | de56dbb | 2011-02-22 09:51:15 +0200 | [diff] [blame] | 46 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 47 | /* IVA2 (IVA2) */ |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 48 | static struct omap_hwmod omap2430_iva_hwmod = { |
| 49 | .name = "iva", |
| 50 | .class = &iva_hwmod_class, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 51 | }; |
| 52 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 53 | /* I2C common */ |
| 54 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 55 | .rev_offs = 0x00, |
| 56 | .sysc_offs = 0x20, |
| 57 | .syss_offs = 0x10, |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 58 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 59 | SYSS_HAS_RESET_STATUS), |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 60 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 61 | }; |
| 62 | |
| 63 | static struct omap_hwmod_class i2c_class = { |
| 64 | .name = "i2c", |
| 65 | .sysc = &i2c_sysc, |
Andy Green | db791a7 | 2011-07-10 05:27:15 -0600 | [diff] [blame] | 66 | .rev = OMAP_I2C_IP_VERSION_1, |
Avinash.H.M | 6d3c55f | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 67 | .reset = &omap_i2c_reset, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 68 | }; |
| 69 | |
Benoit Cousson | 50ebb77 | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 70 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 71 | .fifo_depth = 8, /* bytes */ |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 72 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
| 73 | OMAP_I2C_FLAG_BUS_SHIFT_2 | |
| 74 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 75 | }; |
| 76 | |
Benoit Cousson | 50ebb77 | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 77 | /* I2C1 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 78 | static struct omap_hwmod omap2430_i2c1_hwmod = { |
| 79 | .name = "i2c1", |
Andy Green | 3e60052 | 2011-07-10 05:27:14 -0600 | [diff] [blame] | 80 | .flags = HWMOD_16BIT_REG, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 81 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 82 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 83 | .main_clk = "i2chs1_fck", |
| 84 | .prcm = { |
| 85 | .omap2 = { |
| 86 | /* |
| 87 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for |
| 88 | * I2CHS IP's do not follow the usual pattern. |
| 89 | * prcm_reg_id alone cannot be used to program |
| 90 | * the iclk and fclk. Needs to be handled using |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 91 | * additional flags when clk handling is moved |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 92 | * to hwmod framework. |
| 93 | */ |
| 94 | .module_offs = CORE_MOD, |
| 95 | .prcm_reg_id = 1, |
| 96 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, |
| 97 | .idlest_reg_id = 1, |
| 98 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, |
| 99 | }, |
| 100 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 101 | .class = &i2c_class, |
Benoit Cousson | 50ebb77 | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 102 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | /* I2C2 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 106 | static struct omap_hwmod omap2430_i2c2_hwmod = { |
| 107 | .name = "i2c2", |
Andy Green | 3e60052 | 2011-07-10 05:27:14 -0600 | [diff] [blame] | 108 | .flags = HWMOD_16BIT_REG, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 109 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 110 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 111 | .main_clk = "i2chs2_fck", |
| 112 | .prcm = { |
| 113 | .omap2 = { |
| 114 | .module_offs = CORE_MOD, |
| 115 | .prcm_reg_id = 1, |
| 116 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, |
| 117 | .idlest_reg_id = 1, |
| 118 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, |
| 119 | }, |
| 120 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 121 | .class = &i2c_class, |
Benoit Cousson | 50ebb77 | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 122 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 123 | }; |
| 124 | |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 125 | /* gpio5 */ |
| 126 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { |
| 127 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 128 | { .irq = -1 } |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 129 | }; |
| 130 | |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 131 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
| 132 | .name = "gpio5", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 133 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 134 | .mpu_irqs = omap243x_gpio5_irqs, |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 135 | .main_clk = "gpio5_fck", |
| 136 | .prcm = { |
| 137 | .omap2 = { |
| 138 | .prcm_reg_id = 2, |
| 139 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, |
| 140 | .module_offs = CORE_MOD, |
| 141 | .idlest_reg_id = 2, |
| 142 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, |
| 143 | }, |
| 144 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 145 | .class = &omap2xxx_gpio_hwmod_class, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 146 | .dev_attr = &omap2xxx_gpio_dev_attr, |
Varadarajan, Charulatha | aeac0e4 | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 147 | }; |
| 148 | |
G, Manjunath Kondaiah | 82cbd1a | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 149 | /* dma attributes */ |
| 150 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 151 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 152 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, |
| 153 | .lch_count = 32, |
| 154 | }; |
| 155 | |
G, Manjunath Kondaiah | 82cbd1a | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 156 | static struct omap_hwmod omap2430_dma_system_hwmod = { |
| 157 | .name = "dma", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 158 | .class = &omap2xxx_dma_hwmod_class, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 159 | .mpu_irqs = omap2_dma_system_irqs, |
G, Manjunath Kondaiah | 82cbd1a | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 160 | .main_clk = "core_l3_ck", |
G, Manjunath Kondaiah | 82cbd1a | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 161 | .dev_attr = &dma_dev_attr, |
G, Manjunath Kondaiah | 82cbd1a | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 162 | .flags = HWMOD_NO_IDLEST, |
| 163 | }; |
| 164 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 165 | /* mailbox */ |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 166 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { |
| 167 | { .irq = 26 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 168 | { .irq = -1 } |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 169 | }; |
| 170 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 171 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
| 172 | .name = "mailbox", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 173 | .class = &omap2xxx_mailbox_hwmod_class, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 174 | .mpu_irqs = omap2430_mailbox_irqs, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 175 | .main_clk = "mailboxes_ick", |
| 176 | .prcm = { |
| 177 | .omap2 = { |
| 178 | .prcm_reg_id = 1, |
| 179 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 180 | .module_offs = CORE_MOD, |
| 181 | .idlest_reg_id = 1, |
| 182 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
| 183 | }, |
| 184 | }, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 187 | /* mcspi3 */ |
| 188 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { |
| 189 | { .irq = 91 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 190 | { .irq = -1 } |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { |
| 194 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ |
| 195 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ |
| 196 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ |
| 197 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 198 | { .dma_req = -1 } |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 199 | }; |
| 200 | |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 201 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
| 202 | .num_chipselect = 2, |
| 203 | }; |
| 204 | |
| 205 | static struct omap_hwmod omap2430_mcspi3_hwmod = { |
Paul Walmsley | bec9381 | 2012-04-19 04:03:50 -0600 | [diff] [blame] | 206 | .name = "mcspi3", |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 207 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 208 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 209 | .main_clk = "mcspi3_fck", |
| 210 | .prcm = { |
| 211 | .omap2 = { |
| 212 | .module_offs = CORE_MOD, |
| 213 | .prcm_reg_id = 2, |
| 214 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| 215 | .idlest_reg_id = 2, |
| 216 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, |
| 217 | }, |
| 218 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 219 | .class = &omap2xxx_mcspi_class, |
| 220 | .dev_attr = &omap_mcspi3_dev_attr, |
Charulatha V | 7f904c7 | 2011-02-17 09:53:10 -0800 | [diff] [blame] | 221 | }; |
| 222 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 223 | /* usbhsotg */ |
Hema HK | 44d02ac | 2011-02-17 12:07:17 +0530 | [diff] [blame] | 224 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
| 225 | .rev_offs = 0x0400, |
| 226 | .sysc_offs = 0x0404, |
| 227 | .syss_offs = 0x0408, |
| 228 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| |
| 229 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 230 | SYSC_HAS_AUTOIDLE), |
| 231 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 232 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 233 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 234 | }; |
| 235 | |
| 236 | static struct omap_hwmod_class usbotg_class = { |
| 237 | .name = "usbotg", |
| 238 | .sysc = &omap2430_usbhsotg_sysc, |
| 239 | }; |
| 240 | |
| 241 | /* usb_otg_hs */ |
| 242 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { |
| 243 | |
| 244 | { .name = "mc", .irq = 92 }, |
| 245 | { .name = "dma", .irq = 93 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 246 | { .irq = -1 } |
Hema HK | 44d02ac | 2011-02-17 12:07:17 +0530 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { |
| 250 | .name = "usb_otg_hs", |
| 251 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, |
Hema HK | 44d02ac | 2011-02-17 12:07:17 +0530 | [diff] [blame] | 252 | .main_clk = "usbhs_ick", |
| 253 | .prcm = { |
| 254 | .omap2 = { |
| 255 | .prcm_reg_id = 1, |
| 256 | .module_bit = OMAP2430_EN_USBHS_MASK, |
| 257 | .module_offs = CORE_MOD, |
| 258 | .idlest_reg_id = 1, |
| 259 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, |
| 260 | }, |
| 261 | }, |
Hema HK | 44d02ac | 2011-02-17 12:07:17 +0530 | [diff] [blame] | 262 | .class = &usbotg_class, |
| 263 | /* |
| 264 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially |
| 265 | * broken when autoidle is enabled |
| 266 | * workaround is to disable the autoidle bit at module level. |
| 267 | */ |
| 268 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
| 269 | | HWMOD_SWSUP_MSTANDBY, |
Hema HK | 44d02ac | 2011-02-17 12:07:17 +0530 | [diff] [blame] | 270 | }; |
| 271 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 272 | /* |
| 273 | * 'mcbsp' class |
| 274 | * multi channel buffered serial port controller |
| 275 | */ |
Tony Lindgren | 04aa67d | 2011-02-22 10:54:12 -0800 | [diff] [blame] | 276 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 277 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { |
| 278 | .rev_offs = 0x007C, |
| 279 | .sysc_offs = 0x008C, |
| 280 | .sysc_flags = (SYSC_HAS_SOFTRESET), |
| 281 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 282 | }; |
| 283 | |
| 284 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { |
| 285 | .name = "mcbsp", |
| 286 | .sysc = &omap2430_mcbsp_sysc, |
| 287 | .rev = MCBSP_CONFIG_TYPE2, |
| 288 | }; |
| 289 | |
| 290 | /* mcbsp1 */ |
| 291 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { |
| 292 | { .name = "tx", .irq = 59 }, |
| 293 | { .name = "rx", .irq = 60 }, |
| 294 | { .name = "ovr", .irq = 61 }, |
| 295 | { .name = "common", .irq = 64 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 296 | { .irq = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 297 | }; |
| 298 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 299 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
| 300 | .name = "mcbsp1", |
| 301 | .class = &omap2430_mcbsp_hwmod_class, |
| 302 | .mpu_irqs = omap2430_mcbsp1_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 303 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 304 | .main_clk = "mcbsp1_fck", |
| 305 | .prcm = { |
| 306 | .omap2 = { |
| 307 | .prcm_reg_id = 1, |
| 308 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 309 | .module_offs = CORE_MOD, |
| 310 | .idlest_reg_id = 1, |
| 311 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 312 | }, |
| 313 | }, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | /* mcbsp2 */ |
| 317 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { |
| 318 | { .name = "tx", .irq = 62 }, |
| 319 | { .name = "rx", .irq = 63 }, |
| 320 | { .name = "common", .irq = 16 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 321 | { .irq = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 322 | }; |
| 323 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 324 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
| 325 | .name = "mcbsp2", |
| 326 | .class = &omap2430_mcbsp_hwmod_class, |
| 327 | .mpu_irqs = omap2430_mcbsp2_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 328 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 329 | .main_clk = "mcbsp2_fck", |
| 330 | .prcm = { |
| 331 | .omap2 = { |
| 332 | .prcm_reg_id = 1, |
| 333 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 334 | .module_offs = CORE_MOD, |
| 335 | .idlest_reg_id = 1, |
| 336 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 337 | }, |
| 338 | }, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | /* mcbsp3 */ |
| 342 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { |
| 343 | { .name = "tx", .irq = 89 }, |
| 344 | { .name = "rx", .irq = 90 }, |
| 345 | { .name = "common", .irq = 17 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 346 | { .irq = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 347 | }; |
| 348 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 349 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
| 350 | .name = "mcbsp3", |
| 351 | .class = &omap2430_mcbsp_hwmod_class, |
| 352 | .mpu_irqs = omap2430_mcbsp3_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 353 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 354 | .main_clk = "mcbsp3_fck", |
| 355 | .prcm = { |
| 356 | .omap2 = { |
| 357 | .prcm_reg_id = 1, |
| 358 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| 359 | .module_offs = CORE_MOD, |
| 360 | .idlest_reg_id = 2, |
| 361 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, |
| 362 | }, |
| 363 | }, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 364 | }; |
| 365 | |
| 366 | /* mcbsp4 */ |
| 367 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { |
| 368 | { .name = "tx", .irq = 54 }, |
| 369 | { .name = "rx", .irq = 55 }, |
| 370 | { .name = "common", .irq = 18 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 371 | { .irq = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 372 | }; |
| 373 | |
| 374 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { |
| 375 | { .name = "rx", .dma_req = 20 }, |
| 376 | { .name = "tx", .dma_req = 19 }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 377 | { .dma_req = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 378 | }; |
| 379 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 380 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
| 381 | .name = "mcbsp4", |
| 382 | .class = &omap2430_mcbsp_hwmod_class, |
| 383 | .mpu_irqs = omap2430_mcbsp4_irqs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 384 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 385 | .main_clk = "mcbsp4_fck", |
| 386 | .prcm = { |
| 387 | .omap2 = { |
| 388 | .prcm_reg_id = 1, |
| 389 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| 390 | .module_offs = CORE_MOD, |
| 391 | .idlest_reg_id = 2, |
| 392 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, |
| 393 | }, |
| 394 | }, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 395 | }; |
| 396 | |
| 397 | /* mcbsp5 */ |
| 398 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { |
| 399 | { .name = "tx", .irq = 81 }, |
| 400 | { .name = "rx", .irq = 82 }, |
| 401 | { .name = "common", .irq = 19 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 402 | { .irq = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { |
| 406 | { .name = "rx", .dma_req = 22 }, |
| 407 | { .name = "tx", .dma_req = 21 }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 408 | { .dma_req = -1 } |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 409 | }; |
| 410 | |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 411 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
| 412 | .name = "mcbsp5", |
| 413 | .class = &omap2430_mcbsp_hwmod_class, |
| 414 | .mpu_irqs = omap2430_mcbsp5_irqs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 415 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 416 | .main_clk = "mcbsp5_fck", |
| 417 | .prcm = { |
| 418 | .omap2 = { |
| 419 | .prcm_reg_id = 1, |
| 420 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| 421 | .module_offs = CORE_MOD, |
| 422 | .idlest_reg_id = 2, |
| 423 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, |
| 424 | }, |
| 425 | }, |
Charulatha V | 37801b3 | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 426 | }; |
Tony Lindgren | 04aa67d | 2011-02-22 10:54:12 -0800 | [diff] [blame] | 427 | |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 428 | /* MMC/SD/SDIO common */ |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 429 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
| 430 | .rev_offs = 0x1fc, |
| 431 | .sysc_offs = 0x10, |
| 432 | .syss_offs = 0x14, |
| 433 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 434 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 435 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 436 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 437 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 438 | }; |
| 439 | |
| 440 | static struct omap_hwmod_class omap2430_mmc_class = { |
| 441 | .name = "mmc", |
| 442 | .sysc = &omap2430_mmc_sysc, |
| 443 | }; |
| 444 | |
| 445 | /* MMC/SD/SDIO1 */ |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 446 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { |
| 447 | { .irq = 83 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 448 | { .irq = -1 } |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 449 | }; |
| 450 | |
| 451 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { |
| 452 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ |
| 453 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 454 | { .dma_req = -1 } |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 455 | }; |
| 456 | |
| 457 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { |
| 458 | { .role = "dbck", .clk = "mmchsdb1_fck" }, |
| 459 | }; |
| 460 | |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 461 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
| 462 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 463 | }; |
| 464 | |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 465 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
| 466 | .name = "mmc1", |
| 467 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 468 | .mpu_irqs = omap2430_mmc1_mpu_irqs, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 469 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 470 | .opt_clks = omap2430_mmc1_opt_clks, |
| 471 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), |
| 472 | .main_clk = "mmchs1_fck", |
| 473 | .prcm = { |
| 474 | .omap2 = { |
| 475 | .module_offs = CORE_MOD, |
| 476 | .prcm_reg_id = 2, |
| 477 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| 478 | .idlest_reg_id = 2, |
| 479 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, |
| 480 | }, |
| 481 | }, |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 482 | .dev_attr = &mmc1_dev_attr, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 483 | .class = &omap2430_mmc_class, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 484 | }; |
| 485 | |
| 486 | /* MMC/SD/SDIO2 */ |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 487 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { |
| 488 | { .irq = 86 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 489 | { .irq = -1 } |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 490 | }; |
| 491 | |
| 492 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { |
| 493 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ |
| 494 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 495 | { .dma_req = -1 } |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { |
| 499 | { .role = "dbck", .clk = "mmchsdb2_fck" }, |
| 500 | }; |
| 501 | |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 502 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
| 503 | .name = "mmc2", |
| 504 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 505 | .mpu_irqs = omap2430_mmc2_mpu_irqs, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 506 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 507 | .opt_clks = omap2430_mmc2_opt_clks, |
| 508 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), |
| 509 | .main_clk = "mmchs2_fck", |
| 510 | .prcm = { |
| 511 | .omap2 = { |
| 512 | .module_offs = CORE_MOD, |
| 513 | .prcm_reg_id = 2, |
| 514 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 515 | .idlest_reg_id = 2, |
| 516 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, |
| 517 | }, |
| 518 | }, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 519 | .class = &omap2430_mmc_class, |
Paul Walmsley | bce06f3 | 2011-03-01 13:12:55 -0800 | [diff] [blame] | 520 | }; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 521 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 522 | /* |
| 523 | * interfaces |
| 524 | */ |
| 525 | |
| 526 | /* L3 -> L4_CORE interface */ |
| 527 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 528 | .master = &omap2xxx_l3_main_hwmod, |
| 529 | .slave = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 530 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 531 | }; |
| 532 | |
| 533 | /* MPU -> L3 interface */ |
| 534 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 535 | .master = &omap2xxx_mpu_hwmod, |
| 536 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 537 | .user = OCP_USER_MPU, |
| 538 | }; |
| 539 | |
| 540 | /* DSS -> l3 */ |
| 541 | static struct omap_hwmod_ocp_if omap2430_dss__l3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 542 | .master = &omap2xxx_dss_core_hwmod, |
| 543 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 544 | .fw = { |
| 545 | .omap2 = { |
| 546 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 547 | .flags = OMAP_FIREWALL_L3, |
| 548 | } |
| 549 | }, |
| 550 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 551 | }; |
| 552 | |
| 553 | /* l3_core -> usbhsotg interface */ |
| 554 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { |
| 555 | .master = &omap2430_usbhsotg_hwmod, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 556 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 557 | .clk = "core_l3_ck", |
| 558 | .user = OCP_USER_MPU, |
| 559 | }; |
| 560 | |
| 561 | /* L4 CORE -> I2C1 interface */ |
| 562 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 563 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 564 | .slave = &omap2430_i2c1_hwmod, |
| 565 | .clk = "i2c1_ick", |
| 566 | .addr = omap2_i2c1_addr_space, |
| 567 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 568 | }; |
| 569 | |
| 570 | /* L4 CORE -> I2C2 interface */ |
| 571 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 572 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 573 | .slave = &omap2430_i2c2_hwmod, |
| 574 | .clk = "i2c2_ick", |
| 575 | .addr = omap2_i2c2_addr_space, |
| 576 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 577 | }; |
| 578 | |
| 579 | /* L4_CORE -> L4_WKUP interface */ |
| 580 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 581 | .master = &omap2xxx_l4_core_hwmod, |
| 582 | .slave = &omap2xxx_l4_wkup_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 583 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 584 | }; |
| 585 | |
| 586 | /* L4 CORE -> UART1 interface */ |
| 587 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 588 | .master = &omap2xxx_l4_core_hwmod, |
| 589 | .slave = &omap2xxx_uart1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 590 | .clk = "uart1_ick", |
| 591 | .addr = omap2xxx_uart1_addr_space, |
| 592 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 593 | }; |
| 594 | |
| 595 | /* L4 CORE -> UART2 interface */ |
| 596 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 597 | .master = &omap2xxx_l4_core_hwmod, |
| 598 | .slave = &omap2xxx_uart2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 599 | .clk = "uart2_ick", |
| 600 | .addr = omap2xxx_uart2_addr_space, |
| 601 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 602 | }; |
| 603 | |
| 604 | /* L4 PER -> UART3 interface */ |
| 605 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 606 | .master = &omap2xxx_l4_core_hwmod, |
| 607 | .slave = &omap2xxx_uart3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 608 | .clk = "uart3_ick", |
| 609 | .addr = omap2xxx_uart3_addr_space, |
| 610 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 611 | }; |
| 612 | |
| 613 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { |
| 614 | { |
| 615 | .pa_start = OMAP243X_HS_BASE, |
| 616 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, |
| 617 | .flags = ADDR_TYPE_RT |
| 618 | }, |
| 619 | { } |
| 620 | }; |
| 621 | |
| 622 | /* l4_core ->usbhsotg interface */ |
| 623 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 624 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 625 | .slave = &omap2430_usbhsotg_hwmod, |
| 626 | .clk = "usb_l4_ick", |
| 627 | .addr = omap2430_usbhsotg_addrs, |
| 628 | .user = OCP_USER_MPU, |
| 629 | }; |
| 630 | |
| 631 | /* L4 CORE -> MMC1 interface */ |
| 632 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 633 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 634 | .slave = &omap2430_mmc1_hwmod, |
| 635 | .clk = "mmchs1_ick", |
| 636 | .addr = omap2430_mmc1_addr_space, |
| 637 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 638 | }; |
| 639 | |
| 640 | /* L4 CORE -> MMC2 interface */ |
| 641 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 642 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 643 | .slave = &omap2430_mmc2_hwmod, |
| 644 | .clk = "mmchs2_ick", |
| 645 | .addr = omap2430_mmc2_addr_space, |
| 646 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 647 | }; |
| 648 | |
| 649 | /* l4 core -> mcspi1 interface */ |
| 650 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 651 | .master = &omap2xxx_l4_core_hwmod, |
| 652 | .slave = &omap2xxx_mcspi1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 653 | .clk = "mcspi1_ick", |
| 654 | .addr = omap2_mcspi1_addr_space, |
| 655 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 656 | }; |
| 657 | |
| 658 | /* l4 core -> mcspi2 interface */ |
| 659 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 660 | .master = &omap2xxx_l4_core_hwmod, |
| 661 | .slave = &omap2xxx_mcspi2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 662 | .clk = "mcspi2_ick", |
| 663 | .addr = omap2_mcspi2_addr_space, |
| 664 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 665 | }; |
| 666 | |
| 667 | /* l4 core -> mcspi3 interface */ |
| 668 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 669 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 670 | .slave = &omap2430_mcspi3_hwmod, |
| 671 | .clk = "mcspi3_ick", |
| 672 | .addr = omap2430_mcspi3_addr_space, |
| 673 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 674 | }; |
| 675 | |
| 676 | /* IVA2 <- L3 interface */ |
| 677 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 678 | .master = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 679 | .slave = &omap2430_iva_hwmod, |
| 680 | .clk = "dsp_fck", |
| 681 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 682 | }; |
| 683 | |
| 684 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { |
| 685 | { |
| 686 | .pa_start = 0x49018000, |
| 687 | .pa_end = 0x49018000 + SZ_1K - 1, |
| 688 | .flags = ADDR_TYPE_RT |
| 689 | }, |
| 690 | { } |
| 691 | }; |
| 692 | |
| 693 | /* l4_wkup -> timer1 */ |
| 694 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 695 | .master = &omap2xxx_l4_wkup_hwmod, |
| 696 | .slave = &omap2xxx_timer1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 697 | .clk = "gpt1_ick", |
| 698 | .addr = omap2430_timer1_addrs, |
| 699 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 700 | }; |
| 701 | |
| 702 | /* l4_core -> timer2 */ |
| 703 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 704 | .master = &omap2xxx_l4_core_hwmod, |
| 705 | .slave = &omap2xxx_timer2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 706 | .clk = "gpt2_ick", |
| 707 | .addr = omap2xxx_timer2_addrs, |
| 708 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 709 | }; |
| 710 | |
| 711 | /* l4_core -> timer3 */ |
| 712 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 713 | .master = &omap2xxx_l4_core_hwmod, |
| 714 | .slave = &omap2xxx_timer3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 715 | .clk = "gpt3_ick", |
| 716 | .addr = omap2xxx_timer3_addrs, |
| 717 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 718 | }; |
| 719 | |
| 720 | /* l4_core -> timer4 */ |
| 721 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 722 | .master = &omap2xxx_l4_core_hwmod, |
| 723 | .slave = &omap2xxx_timer4_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 724 | .clk = "gpt4_ick", |
| 725 | .addr = omap2xxx_timer4_addrs, |
| 726 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 727 | }; |
| 728 | |
| 729 | /* l4_core -> timer5 */ |
| 730 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 731 | .master = &omap2xxx_l4_core_hwmod, |
| 732 | .slave = &omap2xxx_timer5_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 733 | .clk = "gpt5_ick", |
| 734 | .addr = omap2xxx_timer5_addrs, |
| 735 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 736 | }; |
| 737 | |
| 738 | /* l4_core -> timer6 */ |
| 739 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 740 | .master = &omap2xxx_l4_core_hwmod, |
| 741 | .slave = &omap2xxx_timer6_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 742 | .clk = "gpt6_ick", |
| 743 | .addr = omap2xxx_timer6_addrs, |
| 744 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 745 | }; |
| 746 | |
| 747 | /* l4_core -> timer7 */ |
| 748 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 749 | .master = &omap2xxx_l4_core_hwmod, |
| 750 | .slave = &omap2xxx_timer7_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 751 | .clk = "gpt7_ick", |
| 752 | .addr = omap2xxx_timer7_addrs, |
| 753 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 754 | }; |
| 755 | |
| 756 | /* l4_core -> timer8 */ |
| 757 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 758 | .master = &omap2xxx_l4_core_hwmod, |
| 759 | .slave = &omap2xxx_timer8_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 760 | .clk = "gpt8_ick", |
| 761 | .addr = omap2xxx_timer8_addrs, |
| 762 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 763 | }; |
| 764 | |
| 765 | /* l4_core -> timer9 */ |
| 766 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 767 | .master = &omap2xxx_l4_core_hwmod, |
| 768 | .slave = &omap2xxx_timer9_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 769 | .clk = "gpt9_ick", |
| 770 | .addr = omap2xxx_timer9_addrs, |
| 771 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 772 | }; |
| 773 | |
| 774 | /* l4_core -> timer10 */ |
| 775 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 776 | .master = &omap2xxx_l4_core_hwmod, |
| 777 | .slave = &omap2xxx_timer10_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 778 | .clk = "gpt10_ick", |
| 779 | .addr = omap2_timer10_addrs, |
| 780 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 781 | }; |
| 782 | |
| 783 | /* l4_core -> timer11 */ |
| 784 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 785 | .master = &omap2xxx_l4_core_hwmod, |
| 786 | .slave = &omap2xxx_timer11_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 787 | .clk = "gpt11_ick", |
| 788 | .addr = omap2_timer11_addrs, |
| 789 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 790 | }; |
| 791 | |
| 792 | /* l4_core -> timer12 */ |
| 793 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 794 | .master = &omap2xxx_l4_core_hwmod, |
| 795 | .slave = &omap2xxx_timer12_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 796 | .clk = "gpt12_ick", |
| 797 | .addr = omap2xxx_timer12_addrs, |
| 798 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 799 | }; |
| 800 | |
| 801 | /* l4_wkup -> wd_timer2 */ |
| 802 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { |
| 803 | { |
| 804 | .pa_start = 0x49016000, |
| 805 | .pa_end = 0x4901607f, |
| 806 | .flags = ADDR_TYPE_RT |
| 807 | }, |
| 808 | { } |
| 809 | }; |
| 810 | |
| 811 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 812 | .master = &omap2xxx_l4_wkup_hwmod, |
| 813 | .slave = &omap2xxx_wd_timer2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 814 | .clk = "mpu_wdt_ick", |
| 815 | .addr = omap2430_wd_timer2_addrs, |
| 816 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 817 | }; |
| 818 | |
| 819 | /* l4_core -> dss */ |
| 820 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 821 | .master = &omap2xxx_l4_core_hwmod, |
| 822 | .slave = &omap2xxx_dss_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 823 | .clk = "dss_ick", |
| 824 | .addr = omap2_dss_addrs, |
| 825 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 826 | }; |
| 827 | |
| 828 | /* l4_core -> dss_dispc */ |
| 829 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 830 | .master = &omap2xxx_l4_core_hwmod, |
| 831 | .slave = &omap2xxx_dss_dispc_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 832 | .clk = "dss_ick", |
| 833 | .addr = omap2_dss_dispc_addrs, |
| 834 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 835 | }; |
| 836 | |
| 837 | /* l4_core -> dss_rfbi */ |
| 838 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 839 | .master = &omap2xxx_l4_core_hwmod, |
| 840 | .slave = &omap2xxx_dss_rfbi_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 841 | .clk = "dss_ick", |
| 842 | .addr = omap2_dss_rfbi_addrs, |
| 843 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 844 | }; |
| 845 | |
| 846 | /* l4_core -> dss_venc */ |
| 847 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 848 | .master = &omap2xxx_l4_core_hwmod, |
| 849 | .slave = &omap2xxx_dss_venc_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 850 | .clk = "dss_ick", |
| 851 | .addr = omap2_dss_venc_addrs, |
| 852 | .flags = OCPIF_SWSUP_IDLE, |
| 853 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 854 | }; |
| 855 | |
| 856 | /* l4_wkup -> gpio1 */ |
| 857 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { |
| 858 | { |
| 859 | .pa_start = 0x4900C000, |
| 860 | .pa_end = 0x4900C1ff, |
| 861 | .flags = ADDR_TYPE_RT |
| 862 | }, |
| 863 | { } |
| 864 | }; |
| 865 | |
| 866 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 867 | .master = &omap2xxx_l4_wkup_hwmod, |
| 868 | .slave = &omap2xxx_gpio1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 869 | .clk = "gpios_ick", |
| 870 | .addr = omap2430_gpio1_addr_space, |
| 871 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 872 | }; |
| 873 | |
| 874 | /* l4_wkup -> gpio2 */ |
| 875 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { |
| 876 | { |
| 877 | .pa_start = 0x4900E000, |
| 878 | .pa_end = 0x4900E1ff, |
| 879 | .flags = ADDR_TYPE_RT |
| 880 | }, |
| 881 | { } |
| 882 | }; |
| 883 | |
| 884 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 885 | .master = &omap2xxx_l4_wkup_hwmod, |
| 886 | .slave = &omap2xxx_gpio2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 887 | .clk = "gpios_ick", |
| 888 | .addr = omap2430_gpio2_addr_space, |
| 889 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 890 | }; |
| 891 | |
| 892 | /* l4_wkup -> gpio3 */ |
| 893 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { |
| 894 | { |
| 895 | .pa_start = 0x49010000, |
| 896 | .pa_end = 0x490101ff, |
| 897 | .flags = ADDR_TYPE_RT |
| 898 | }, |
| 899 | { } |
| 900 | }; |
| 901 | |
| 902 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 903 | .master = &omap2xxx_l4_wkup_hwmod, |
| 904 | .slave = &omap2xxx_gpio3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 905 | .clk = "gpios_ick", |
| 906 | .addr = omap2430_gpio3_addr_space, |
| 907 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 908 | }; |
| 909 | |
| 910 | /* l4_wkup -> gpio4 */ |
| 911 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { |
| 912 | { |
| 913 | .pa_start = 0x49012000, |
| 914 | .pa_end = 0x490121ff, |
| 915 | .flags = ADDR_TYPE_RT |
| 916 | }, |
| 917 | { } |
| 918 | }; |
| 919 | |
| 920 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 921 | .master = &omap2xxx_l4_wkup_hwmod, |
| 922 | .slave = &omap2xxx_gpio4_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 923 | .clk = "gpios_ick", |
| 924 | .addr = omap2430_gpio4_addr_space, |
| 925 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 926 | }; |
| 927 | |
| 928 | /* l4_core -> gpio5 */ |
| 929 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { |
| 930 | { |
| 931 | .pa_start = 0x480B6000, |
| 932 | .pa_end = 0x480B61ff, |
| 933 | .flags = ADDR_TYPE_RT |
| 934 | }, |
| 935 | { } |
| 936 | }; |
| 937 | |
| 938 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 939 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 940 | .slave = &omap2430_gpio5_hwmod, |
| 941 | .clk = "gpio5_ick", |
| 942 | .addr = omap2430_gpio5_addr_space, |
| 943 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 944 | }; |
| 945 | |
| 946 | /* dma_system -> L3 */ |
| 947 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { |
| 948 | .master = &omap2430_dma_system_hwmod, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 949 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 950 | .clk = "core_l3_ck", |
| 951 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 952 | }; |
| 953 | |
| 954 | /* l4_core -> dma_system */ |
| 955 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 956 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 957 | .slave = &omap2430_dma_system_hwmod, |
| 958 | .clk = "sdma_ick", |
| 959 | .addr = omap2_dma_system_addrs, |
| 960 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 961 | }; |
| 962 | |
| 963 | /* l4_core -> mailbox */ |
| 964 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 965 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 966 | .slave = &omap2430_mailbox_hwmod, |
| 967 | .addr = omap2_mailbox_addrs, |
| 968 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 969 | }; |
| 970 | |
| 971 | /* l4_core -> mcbsp1 */ |
| 972 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 973 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 974 | .slave = &omap2430_mcbsp1_hwmod, |
| 975 | .clk = "mcbsp1_ick", |
| 976 | .addr = omap2_mcbsp1_addrs, |
| 977 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 978 | }; |
| 979 | |
| 980 | /* l4_core -> mcbsp2 */ |
| 981 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 982 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 983 | .slave = &omap2430_mcbsp2_hwmod, |
| 984 | .clk = "mcbsp2_ick", |
| 985 | .addr = omap2xxx_mcbsp2_addrs, |
| 986 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 987 | }; |
| 988 | |
| 989 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { |
| 990 | { |
| 991 | .name = "mpu", |
| 992 | .pa_start = 0x4808C000, |
| 993 | .pa_end = 0x4808C0ff, |
| 994 | .flags = ADDR_TYPE_RT |
| 995 | }, |
| 996 | { } |
| 997 | }; |
| 998 | |
| 999 | /* l4_core -> mcbsp3 */ |
| 1000 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 1001 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 1002 | .slave = &omap2430_mcbsp3_hwmod, |
| 1003 | .clk = "mcbsp3_ick", |
| 1004 | .addr = omap2430_mcbsp3_addrs, |
| 1005 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1006 | }; |
| 1007 | |
| 1008 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { |
| 1009 | { |
| 1010 | .name = "mpu", |
| 1011 | .pa_start = 0x4808E000, |
| 1012 | .pa_end = 0x4808E0ff, |
| 1013 | .flags = ADDR_TYPE_RT |
| 1014 | }, |
| 1015 | { } |
| 1016 | }; |
| 1017 | |
| 1018 | /* l4_core -> mcbsp4 */ |
| 1019 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 1020 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 1021 | .slave = &omap2430_mcbsp4_hwmod, |
| 1022 | .clk = "mcbsp4_ick", |
| 1023 | .addr = omap2430_mcbsp4_addrs, |
| 1024 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1025 | }; |
| 1026 | |
| 1027 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { |
| 1028 | { |
| 1029 | .name = "mpu", |
| 1030 | .pa_start = 0x48096000, |
| 1031 | .pa_end = 0x480960ff, |
| 1032 | .flags = ADDR_TYPE_RT |
| 1033 | }, |
| 1034 | { } |
| 1035 | }; |
| 1036 | |
| 1037 | /* l4_core -> mcbsp5 */ |
| 1038 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 1039 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 1040 | .slave = &omap2430_mcbsp5_hwmod, |
| 1041 | .clk = "mcbsp5_ick", |
| 1042 | .addr = omap2430_mcbsp5_addrs, |
| 1043 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1044 | }; |
| 1045 | |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 1046 | static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
| 1047 | &omap2430_l3_main__l4_core, |
| 1048 | &omap2430_mpu__l3_main, |
| 1049 | &omap2430_dss__l3, |
| 1050 | &omap2430_usbhsotg__l3, |
| 1051 | &omap2430_l4_core__i2c1, |
| 1052 | &omap2430_l4_core__i2c2, |
| 1053 | &omap2430_l4_core__l4_wkup, |
| 1054 | &omap2_l4_core__uart1, |
| 1055 | &omap2_l4_core__uart2, |
| 1056 | &omap2_l4_core__uart3, |
| 1057 | &omap2430_l4_core__usbhsotg, |
| 1058 | &omap2430_l4_core__mmc1, |
| 1059 | &omap2430_l4_core__mmc2, |
| 1060 | &omap2430_l4_core__mcspi1, |
| 1061 | &omap2430_l4_core__mcspi2, |
| 1062 | &omap2430_l4_core__mcspi3, |
| 1063 | &omap2430_l3__iva, |
| 1064 | &omap2430_l4_wkup__timer1, |
| 1065 | &omap2430_l4_core__timer2, |
| 1066 | &omap2430_l4_core__timer3, |
| 1067 | &omap2430_l4_core__timer4, |
| 1068 | &omap2430_l4_core__timer5, |
| 1069 | &omap2430_l4_core__timer6, |
| 1070 | &omap2430_l4_core__timer7, |
| 1071 | &omap2430_l4_core__timer8, |
| 1072 | &omap2430_l4_core__timer9, |
| 1073 | &omap2430_l4_core__timer10, |
| 1074 | &omap2430_l4_core__timer11, |
| 1075 | &omap2430_l4_core__timer12, |
| 1076 | &omap2430_l4_wkup__wd_timer2, |
| 1077 | &omap2430_l4_core__dss, |
| 1078 | &omap2430_l4_core__dss_dispc, |
| 1079 | &omap2430_l4_core__dss_rfbi, |
| 1080 | &omap2430_l4_core__dss_venc, |
| 1081 | &omap2430_l4_wkup__gpio1, |
| 1082 | &omap2430_l4_wkup__gpio2, |
| 1083 | &omap2430_l4_wkup__gpio3, |
| 1084 | &omap2430_l4_wkup__gpio4, |
| 1085 | &omap2430_l4_core__gpio5, |
| 1086 | &omap2430_dma_system__l3, |
| 1087 | &omap2430_l4_core__dma_system, |
| 1088 | &omap2430_l4_core__mailbox, |
| 1089 | &omap2430_l4_core__mcbsp1, |
| 1090 | &omap2430_l4_core__mcbsp2, |
| 1091 | &omap2430_l4_core__mcbsp3, |
| 1092 | &omap2430_l4_core__mcbsp4, |
| 1093 | &omap2430_l4_core__mcbsp5, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1094 | NULL, |
| 1095 | }; |
| 1096 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1097 | int __init omap2430_hwmod_init(void) |
| 1098 | { |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 1099 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1100 | } |