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Ben Dooksa21765a2007-02-11 18:31:01 +01001/* linux/arch/arm/mach-s3c2440/dma.c
Ben Dooks98c418a2006-09-15 23:45:17 +01002 *
Ben Dooksc16f7bd2006-12-17 20:05:21 +01003 * Copyright (c) 2006 Simtec Electronics
Ben Dooks98c418a2006-09-15 23:45:17 +01004 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
Kay Sievers4a858cf2011-12-21 16:01:38 -080017#include <linux/device.h>
Ben Dooksb6d1f542006-12-17 23:22:26 +010018#include <linux/serial_core.h>
Ben Dooks98c418a2006-09-15 23:45:17 +010019
Ben Dooks44dc9402009-03-19 15:02:35 +000020#include <mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/dma.h>
Ben Dooks98c418a2006-09-15 23:45:17 +010022
Ben Dooks992426b2010-02-20 23:01:33 +000023#include <plat/dma-s3c24xx.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010024#include <plat/cpu.h>
Ben Dooks98c418a2006-09-15 23:45:17 +010025
Ben Dooksa2b7ba92008-10-07 22:26:09 +010026#include <plat/regs-serial.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/regs-gpio.h>
Ben Dooksf74c95c2008-10-30 10:14:36 +000028#include <plat/regs-ac97.h>
Ben Dooks44dc9402009-03-19 15:02:35 +000029#include <plat/regs-dma.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
Ben Dooks8150bc82009-03-04 00:49:26 +000033#include <plat/regs-iis.h>
Ben Dooks13622702008-10-30 10:14:38 +000034#include <plat/regs-spi.h>
Ben Dooks98c418a2006-09-15 23:45:17 +010035
36static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
37 [DMACH_XD0] = {
38 .name = "xdreq0",
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 },
41 [DMACH_XD1] = {
42 .name = "xdreq1",
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 },
45 [DMACH_SDI] = {
46 .name = "sdi",
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010051 },
52 [DMACH_SPI0] = {
53 .name = "spi0",
54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010055 },
56 [DMACH_SPI1] = {
57 .name = "spi1",
58 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010059 },
60 [DMACH_UART0] = {
61 .name = "uart0",
62 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010063 },
64 [DMACH_UART1] = {
65 .name = "uart1",
66 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010067 },
68 [DMACH_UART2] = {
69 .name = "uart2",
70 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010071 },
72 [DMACH_TIMER] = {
73 .name = "timer",
74 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
75 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
76 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
77 },
78 [DMACH_I2S_IN] = {
79 .name = "i2s-sdi",
80 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
81 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010082 },
83 [DMACH_I2S_OUT] = {
84 .name = "i2s-sdo",
85 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
86 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010087 },
88 [DMACH_PCM_IN] = {
89 .name = "pcm-in",
90 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
91 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010092 },
93 [DMACH_PCM_OUT] = {
94 .name = "pcm-out",
95 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
96 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +010097 },
98 [DMACH_MIC_IN] = {
99 .name = "mic-in",
100 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
101 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
Ben Dooks98c418a2006-09-15 23:45:17 +0100102 },
103 [DMACH_USB_EP1] = {
104 .name = "usb-ep1",
105 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
106 },
107 [DMACH_USB_EP2] = {
108 .name = "usb-ep2",
109 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
110 },
111 [DMACH_USB_EP3] = {
112 .name = "usb-ep3",
113 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
114 },
115 [DMACH_USB_EP4] = {
116 .name = "usb-ep4",
117 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
118 },
119};
120
121static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
122 struct s3c24xx_dma_map *map)
123{
124 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
125}
126
127static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
128 .select = s3c2440_dma_select,
129 .dcon_mask = 7 << 24,
130 .map = s3c2440_dma_mappings,
131 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
132};
133
Ben Dooksbd65c822007-02-13 13:14:12 +0100134static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
135 .channels = {
136 [DMACH_SDI] = {
137 .list = {
138 [0] = 3 | DMA_CH_VALID,
139 [1] = 2 | DMA_CH_VALID,
140 [2] = 1 | DMA_CH_VALID,
141 [3] = 0 | DMA_CH_VALID,
142 },
143 },
144 [DMACH_I2S_IN] = {
145 .list = {
146 [0] = 1 | DMA_CH_VALID,
147 [1] = 2 | DMA_CH_VALID,
148 },
149 },
150 [DMACH_I2S_OUT] = {
151 .list = {
152 [0] = 2 | DMA_CH_VALID,
153 [1] = 1 | DMA_CH_VALID,
154 },
155 },
156 [DMACH_PCM_IN] = {
157 .list = {
158 [0] = 2 | DMA_CH_VALID,
159 [1] = 1 | DMA_CH_VALID,
160 },
161 },
162 [DMACH_PCM_OUT] = {
163 .list = {
164 [0] = 1 | DMA_CH_VALID,
165 [1] = 3 | DMA_CH_VALID,
166 },
167 },
168 [DMACH_MIC_IN] = {
169 .list = {
170 [0] = 3 | DMA_CH_VALID,
171 [1] = 2 | DMA_CH_VALID,
172 },
173 },
174 },
175};
176
Heiko Stuebner04511a62012-01-27 15:35:25 +0900177static int __init s3c2440_dma_add(struct device *dev,
178 struct subsys_interface *sif)
Ben Dooks98c418a2006-09-15 23:45:17 +0100179{
Ben Dooks48adbcf2007-02-17 15:37:14 +0100180 s3c2410_dma_init();
Ben Dooksbd65c822007-02-13 13:14:12 +0100181 s3c24xx_dma_order_set(&s3c2440_dma_order);
Ben Dooks98c418a2006-09-15 23:45:17 +0100182 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
183}
184
Kay Sievers4a858cf2011-12-21 16:01:38 -0800185static struct subsys_interface s3c2440_dma_interface = {
186 .name = "s3c2440_dma",
187 .subsys = &s3c2440_subsys,
188 .add_dev = s3c2440_dma_add,
Ben Dooks98c418a2006-09-15 23:45:17 +0100189};
190
191static int __init s3c2440_dma_init(void)
192{
Kay Sievers4a858cf2011-12-21 16:01:38 -0800193 return subsys_interface_register(&s3c2440_dma_interface);
Ben Dooks98c418a2006-09-15 23:45:17 +0100194}
195
196arch_initcall(s3c2440_dma_init);
197