Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008-2014, The Linux foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License rev 2 and |
| 6 | * only rev 2 as published by the free Software foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/pm_runtime.h> |
| 24 | #include <linux/spi/spi.h> |
| 25 | |
| 26 | #define QUP_CONFIG 0x0000 |
| 27 | #define QUP_STATE 0x0004 |
| 28 | #define QUP_IO_M_MODES 0x0008 |
| 29 | #define QUP_SW_RESET 0x000c |
| 30 | #define QUP_OPERATIONAL 0x0018 |
| 31 | #define QUP_ERROR_FLAGS 0x001c |
| 32 | #define QUP_ERROR_FLAGS_EN 0x0020 |
| 33 | #define QUP_OPERATIONAL_MASK 0x0028 |
| 34 | #define QUP_HW_VERSION 0x0030 |
| 35 | #define QUP_MX_OUTPUT_CNT 0x0100 |
| 36 | #define QUP_OUTPUT_FIFO 0x0110 |
| 37 | #define QUP_MX_WRITE_CNT 0x0150 |
| 38 | #define QUP_MX_INPUT_CNT 0x0200 |
| 39 | #define QUP_MX_READ_CNT 0x0208 |
| 40 | #define QUP_INPUT_FIFO 0x0218 |
| 41 | |
| 42 | #define SPI_CONFIG 0x0300 |
| 43 | #define SPI_IO_CONTROL 0x0304 |
| 44 | #define SPI_ERROR_FLAGS 0x0308 |
| 45 | #define SPI_ERROR_FLAGS_EN 0x030c |
| 46 | |
| 47 | /* QUP_CONFIG fields */ |
| 48 | #define QUP_CONFIG_SPI_MODE (1 << 8) |
| 49 | #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) |
| 50 | #define QUP_CONFIG_NO_INPUT BIT(7) |
| 51 | #define QUP_CONFIG_NO_OUTPUT BIT(6) |
| 52 | #define QUP_CONFIG_N 0x001f |
| 53 | |
| 54 | /* QUP_STATE fields */ |
| 55 | #define QUP_STATE_VALID BIT(2) |
| 56 | #define QUP_STATE_RESET 0 |
| 57 | #define QUP_STATE_RUN 1 |
| 58 | #define QUP_STATE_PAUSE 3 |
| 59 | #define QUP_STATE_MASK 3 |
| 60 | #define QUP_STATE_CLEAR 2 |
| 61 | |
| 62 | #define QUP_HW_VERSION_2_1_1 0x20010001 |
| 63 | |
| 64 | /* QUP_IO_M_MODES fields */ |
| 65 | #define QUP_IO_M_PACK_EN BIT(15) |
| 66 | #define QUP_IO_M_UNPACK_EN BIT(14) |
| 67 | #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12 |
| 68 | #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10 |
| 69 | #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT) |
| 70 | #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT) |
| 71 | |
| 72 | #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0) |
| 73 | #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2) |
| 74 | #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5) |
| 75 | #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7) |
| 76 | |
| 77 | #define QUP_IO_M_MODE_FIFO 0 |
| 78 | #define QUP_IO_M_MODE_BLOCK 1 |
| 79 | #define QUP_IO_M_MODE_DMOV 2 |
| 80 | #define QUP_IO_M_MODE_BAM 3 |
| 81 | |
| 82 | /* QUP_OPERATIONAL fields */ |
| 83 | #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) |
| 84 | #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) |
| 85 | #define QUP_OP_IN_SERVICE_FLAG BIT(9) |
| 86 | #define QUP_OP_OUT_SERVICE_FLAG BIT(8) |
| 87 | #define QUP_OP_IN_FIFO_FULL BIT(7) |
| 88 | #define QUP_OP_OUT_FIFO_FULL BIT(6) |
| 89 | #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) |
| 90 | #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) |
| 91 | |
| 92 | /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */ |
| 93 | #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) |
| 94 | #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) |
| 95 | #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) |
| 96 | #define QUP_ERROR_INPUT_OVER_RUN BIT(2) |
| 97 | |
| 98 | /* SPI_CONFIG fields */ |
| 99 | #define SPI_CONFIG_HS_MODE BIT(10) |
| 100 | #define SPI_CONFIG_INPUT_FIRST BIT(9) |
| 101 | #define SPI_CONFIG_LOOPBACK BIT(8) |
| 102 | |
| 103 | /* SPI_IO_CONTROL fields */ |
| 104 | #define SPI_IO_C_FORCE_CS BIT(11) |
| 105 | #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) |
| 106 | #define SPI_IO_C_MX_CS_MODE BIT(8) |
| 107 | #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) |
| 108 | #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2) |
| 109 | #define SPI_IO_C_CS_SELECT_MASK 0x000c |
| 110 | #define SPI_IO_C_TRISTATE_CS BIT(1) |
| 111 | #define SPI_IO_C_NO_TRI_STATE BIT(0) |
| 112 | |
| 113 | /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */ |
| 114 | #define SPI_ERROR_CLK_OVER_RUN BIT(1) |
| 115 | #define SPI_ERROR_CLK_UNDER_RUN BIT(0) |
| 116 | |
| 117 | #define SPI_NUM_CHIPSELECTS 4 |
| 118 | |
| 119 | /* high speed mode is when bus rate is greater then 26MHz */ |
| 120 | #define SPI_HS_MIN_RATE 26000000 |
| 121 | #define SPI_MAX_RATE 50000000 |
| 122 | |
| 123 | #define SPI_DELAY_THRESHOLD 1 |
| 124 | #define SPI_DELAY_RETRY 10 |
| 125 | |
| 126 | struct spi_qup_device { |
| 127 | int select; |
| 128 | u16 mode; |
| 129 | }; |
| 130 | |
| 131 | struct spi_qup { |
| 132 | void __iomem *base; |
| 133 | struct device *dev; |
| 134 | struct clk *cclk; /* core clock */ |
| 135 | struct clk *iclk; /* interface clock */ |
| 136 | int irq; |
Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 137 | spinlock_t lock; |
| 138 | |
| 139 | int in_fifo_sz; |
| 140 | int out_fifo_sz; |
| 141 | int in_blk_sz; |
| 142 | int out_blk_sz; |
| 143 | |
| 144 | struct spi_transfer *xfer; |
| 145 | struct completion done; |
| 146 | int error; |
| 147 | int w_size; /* bytes per SPI word */ |
| 148 | int tx_bytes; |
| 149 | int rx_bytes; |
| 150 | }; |
| 151 | |
| 152 | |
| 153 | static inline bool spi_qup_is_valid_state(struct spi_qup *controller) |
| 154 | { |
| 155 | u32 opstate = readl_relaxed(controller->base + QUP_STATE); |
| 156 | |
| 157 | return opstate & QUP_STATE_VALID; |
| 158 | } |
| 159 | |
| 160 | static int spi_qup_set_state(struct spi_qup *controller, u32 state) |
| 161 | { |
| 162 | unsigned long loop; |
| 163 | u32 cur_state; |
| 164 | |
| 165 | loop = 0; |
| 166 | while (!spi_qup_is_valid_state(controller)) { |
| 167 | |
| 168 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); |
| 169 | |
| 170 | if (++loop > SPI_DELAY_RETRY) |
| 171 | return -EIO; |
| 172 | } |
| 173 | |
| 174 | if (loop) |
| 175 | dev_dbg(controller->dev, "invalid state for %ld,us %d\n", |
| 176 | loop, state); |
| 177 | |
| 178 | cur_state = readl_relaxed(controller->base + QUP_STATE); |
| 179 | /* |
| 180 | * Per spec: for PAUSE_STATE to RESET_STATE, two writes |
| 181 | * of (b10) are required |
| 182 | */ |
| 183 | if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) && |
| 184 | (state == QUP_STATE_RESET)) { |
| 185 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); |
| 186 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); |
| 187 | } else { |
| 188 | cur_state &= ~QUP_STATE_MASK; |
| 189 | cur_state |= state; |
| 190 | writel_relaxed(cur_state, controller->base + QUP_STATE); |
| 191 | } |
| 192 | |
| 193 | loop = 0; |
| 194 | while (!spi_qup_is_valid_state(controller)) { |
| 195 | |
| 196 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); |
| 197 | |
| 198 | if (++loop > SPI_DELAY_RETRY) |
| 199 | return -EIO; |
| 200 | } |
| 201 | |
| 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | |
| 206 | static void spi_qup_fifo_read(struct spi_qup *controller, |
| 207 | struct spi_transfer *xfer) |
| 208 | { |
| 209 | u8 *rx_buf = xfer->rx_buf; |
| 210 | u32 word, state; |
| 211 | int idx, shift, w_size; |
| 212 | |
| 213 | w_size = controller->w_size; |
| 214 | |
| 215 | while (controller->rx_bytes < xfer->len) { |
| 216 | |
| 217 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); |
| 218 | if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) |
| 219 | break; |
| 220 | |
| 221 | word = readl_relaxed(controller->base + QUP_INPUT_FIFO); |
| 222 | |
| 223 | if (!rx_buf) { |
| 224 | controller->rx_bytes += w_size; |
| 225 | continue; |
| 226 | } |
| 227 | |
| 228 | for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) { |
| 229 | /* |
| 230 | * The data format depends on bytes per SPI word: |
| 231 | * 4 bytes: 0x12345678 |
| 232 | * 2 bytes: 0x00001234 |
| 233 | * 1 byte : 0x00000012 |
| 234 | */ |
| 235 | shift = BITS_PER_BYTE; |
| 236 | shift *= (w_size - idx - 1); |
| 237 | rx_buf[controller->rx_bytes] = word >> shift; |
| 238 | } |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | static void spi_qup_fifo_write(struct spi_qup *controller, |
| 243 | struct spi_transfer *xfer) |
| 244 | { |
| 245 | const u8 *tx_buf = xfer->tx_buf; |
| 246 | u32 word, state, data; |
| 247 | int idx, w_size; |
| 248 | |
| 249 | w_size = controller->w_size; |
| 250 | |
| 251 | while (controller->tx_bytes < xfer->len) { |
| 252 | |
| 253 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); |
| 254 | if (state & QUP_OP_OUT_FIFO_FULL) |
| 255 | break; |
| 256 | |
| 257 | word = 0; |
| 258 | for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) { |
| 259 | |
| 260 | if (!tx_buf) { |
| 261 | controller->tx_bytes += w_size; |
| 262 | break; |
| 263 | } |
| 264 | |
| 265 | data = tx_buf[controller->tx_bytes]; |
| 266 | word |= data << (BITS_PER_BYTE * (3 - idx)); |
| 267 | } |
| 268 | |
| 269 | writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); |
| 270 | } |
| 271 | } |
| 272 | |
| 273 | static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) |
| 274 | { |
| 275 | struct spi_qup *controller = dev_id; |
| 276 | struct spi_transfer *xfer; |
| 277 | u32 opflags, qup_err, spi_err; |
| 278 | unsigned long flags; |
| 279 | int error = 0; |
| 280 | |
| 281 | spin_lock_irqsave(&controller->lock, flags); |
| 282 | xfer = controller->xfer; |
| 283 | controller->xfer = NULL; |
| 284 | spin_unlock_irqrestore(&controller->lock, flags); |
| 285 | |
| 286 | qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); |
| 287 | spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); |
| 288 | opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); |
| 289 | |
| 290 | writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); |
| 291 | writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); |
| 292 | writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); |
| 293 | |
| 294 | if (!xfer) { |
| 295 | dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n", |
| 296 | qup_err, spi_err, opflags); |
| 297 | return IRQ_HANDLED; |
| 298 | } |
| 299 | |
| 300 | if (qup_err) { |
| 301 | if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) |
| 302 | dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); |
| 303 | if (qup_err & QUP_ERROR_INPUT_UNDER_RUN) |
| 304 | dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); |
| 305 | if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN) |
| 306 | dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); |
| 307 | if (qup_err & QUP_ERROR_INPUT_OVER_RUN) |
| 308 | dev_warn(controller->dev, "INPUT_OVER_RUN\n"); |
| 309 | |
| 310 | error = -EIO; |
| 311 | } |
| 312 | |
| 313 | if (spi_err) { |
| 314 | if (spi_err & SPI_ERROR_CLK_OVER_RUN) |
| 315 | dev_warn(controller->dev, "CLK_OVER_RUN\n"); |
| 316 | if (spi_err & SPI_ERROR_CLK_UNDER_RUN) |
| 317 | dev_warn(controller->dev, "CLK_UNDER_RUN\n"); |
| 318 | |
| 319 | error = -EIO; |
| 320 | } |
| 321 | |
| 322 | if (opflags & QUP_OP_IN_SERVICE_FLAG) |
| 323 | spi_qup_fifo_read(controller, xfer); |
| 324 | |
| 325 | if (opflags & QUP_OP_OUT_SERVICE_FLAG) |
| 326 | spi_qup_fifo_write(controller, xfer); |
| 327 | |
| 328 | spin_lock_irqsave(&controller->lock, flags); |
| 329 | controller->error = error; |
| 330 | controller->xfer = xfer; |
| 331 | spin_unlock_irqrestore(&controller->lock, flags); |
| 332 | |
| 333 | if (controller->rx_bytes == xfer->len || error) |
| 334 | complete(&controller->done); |
| 335 | |
| 336 | return IRQ_HANDLED; |
| 337 | } |
| 338 | |
| 339 | |
| 340 | /* set clock freq ... bits per word */ |
| 341 | static int spi_qup_io_config(struct spi_qup *controller, |
| 342 | struct spi_qup_device *chip, |
| 343 | struct spi_transfer *xfer) |
| 344 | { |
| 345 | u32 config, iomode, mode; |
| 346 | int ret, n_words, w_size; |
| 347 | |
| 348 | if (chip->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { |
| 349 | dev_err(controller->dev, "too big size for loopback %d > %d\n", |
| 350 | xfer->len, controller->in_fifo_sz); |
| 351 | return -EIO; |
| 352 | } |
| 353 | |
| 354 | ret = clk_set_rate(controller->cclk, xfer->speed_hz); |
| 355 | if (ret) { |
| 356 | dev_err(controller->dev, "fail to set frequency %d", |
| 357 | xfer->speed_hz); |
| 358 | return -EIO; |
| 359 | } |
| 360 | |
| 361 | if (spi_qup_set_state(controller, QUP_STATE_RESET)) { |
| 362 | dev_err(controller->dev, "cannot set RESET state\n"); |
| 363 | return -EIO; |
| 364 | } |
| 365 | |
| 366 | w_size = 4; |
| 367 | if (xfer->bits_per_word <= 8) |
| 368 | w_size = 1; |
| 369 | else if (xfer->bits_per_word <= 16) |
| 370 | w_size = 2; |
| 371 | |
| 372 | n_words = xfer->len / w_size; |
| 373 | controller->w_size = w_size; |
| 374 | |
| 375 | if (n_words <= controller->in_fifo_sz) { |
| 376 | mode = QUP_IO_M_MODE_FIFO; |
| 377 | writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); |
| 378 | writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); |
| 379 | /* must be zero for FIFO */ |
| 380 | writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); |
| 381 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); |
| 382 | } else { |
| 383 | mode = QUP_IO_M_MODE_BLOCK; |
| 384 | writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); |
| 385 | writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); |
| 386 | /* must be zero for BLOCK and BAM */ |
| 387 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); |
| 388 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); |
| 389 | } |
| 390 | |
| 391 | iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); |
| 392 | /* Set input and output transfer mode */ |
| 393 | iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); |
| 394 | iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); |
| 395 | iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); |
| 396 | iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); |
| 397 | |
| 398 | writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); |
| 399 | |
| 400 | config = readl_relaxed(controller->base + SPI_CONFIG); |
| 401 | |
| 402 | if (chip->mode & SPI_LOOP) |
| 403 | config |= SPI_CONFIG_LOOPBACK; |
| 404 | else |
| 405 | config &= ~SPI_CONFIG_LOOPBACK; |
| 406 | |
| 407 | if (chip->mode & SPI_CPHA) |
| 408 | config &= ~SPI_CONFIG_INPUT_FIRST; |
| 409 | else |
| 410 | config |= SPI_CONFIG_INPUT_FIRST; |
| 411 | |
| 412 | /* |
| 413 | * HS_MODE improves signal stability for spi-clk high rates, |
| 414 | * but is invalid in loop back mode. |
| 415 | */ |
| 416 | if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(chip->mode & SPI_LOOP)) |
| 417 | config |= SPI_CONFIG_HS_MODE; |
| 418 | else |
| 419 | config &= ~SPI_CONFIG_HS_MODE; |
| 420 | |
| 421 | writel_relaxed(config, controller->base + SPI_CONFIG); |
| 422 | |
| 423 | config = readl_relaxed(controller->base + QUP_CONFIG); |
| 424 | config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); |
| 425 | config |= xfer->bits_per_word - 1; |
| 426 | config |= QUP_CONFIG_SPI_MODE; |
| 427 | writel_relaxed(config, controller->base + QUP_CONFIG); |
| 428 | |
| 429 | writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK); |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | static void spi_qup_set_cs(struct spi_device *spi, bool enable) |
| 434 | { |
| 435 | struct spi_qup *controller = spi_master_get_devdata(spi->master); |
| 436 | struct spi_qup_device *chip = spi_get_ctldata(spi); |
| 437 | |
| 438 | u32 iocontol, mask; |
| 439 | |
| 440 | iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL); |
| 441 | |
| 442 | /* Disable auto CS toggle and use manual */ |
| 443 | iocontol &= ~SPI_IO_C_MX_CS_MODE; |
| 444 | iocontol |= SPI_IO_C_FORCE_CS; |
| 445 | |
| 446 | iocontol &= ~SPI_IO_C_CS_SELECT_MASK; |
| 447 | iocontol |= SPI_IO_C_CS_SELECT(chip->select); |
| 448 | |
| 449 | mask = SPI_IO_C_CS_N_POLARITY_0 << chip->select; |
| 450 | |
| 451 | if (enable) |
| 452 | iocontol |= mask; |
| 453 | else |
| 454 | iocontol &= ~mask; |
| 455 | |
| 456 | writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL); |
| 457 | } |
| 458 | |
| 459 | static int spi_qup_transfer_one(struct spi_master *master, |
| 460 | struct spi_device *spi, |
| 461 | struct spi_transfer *xfer) |
| 462 | { |
| 463 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 464 | struct spi_qup_device *chip = spi_get_ctldata(spi); |
| 465 | unsigned long timeout, flags; |
| 466 | int ret = -EIO; |
| 467 | |
| 468 | ret = spi_qup_io_config(controller, chip, xfer); |
| 469 | if (ret) |
| 470 | return ret; |
| 471 | |
| 472 | timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); |
| 473 | timeout = DIV_ROUND_UP(xfer->len * 8, timeout); |
| 474 | timeout = 100 * msecs_to_jiffies(timeout); |
| 475 | |
| 476 | reinit_completion(&controller->done); |
| 477 | |
| 478 | spin_lock_irqsave(&controller->lock, flags); |
| 479 | controller->xfer = xfer; |
| 480 | controller->error = 0; |
| 481 | controller->rx_bytes = 0; |
| 482 | controller->tx_bytes = 0; |
| 483 | spin_unlock_irqrestore(&controller->lock, flags); |
| 484 | |
| 485 | if (spi_qup_set_state(controller, QUP_STATE_RUN)) { |
| 486 | dev_warn(controller->dev, "cannot set RUN state\n"); |
| 487 | goto exit; |
| 488 | } |
| 489 | |
| 490 | if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) { |
| 491 | dev_warn(controller->dev, "cannot set PAUSE state\n"); |
| 492 | goto exit; |
| 493 | } |
| 494 | |
| 495 | spi_qup_fifo_write(controller, xfer); |
| 496 | |
| 497 | if (spi_qup_set_state(controller, QUP_STATE_RUN)) { |
| 498 | dev_warn(controller->dev, "cannot set EXECUTE state\n"); |
| 499 | goto exit; |
| 500 | } |
| 501 | |
| 502 | if (!wait_for_completion_timeout(&controller->done, timeout)) |
| 503 | ret = -ETIMEDOUT; |
| 504 | exit: |
| 505 | spi_qup_set_state(controller, QUP_STATE_RESET); |
| 506 | spin_lock_irqsave(&controller->lock, flags); |
| 507 | controller->xfer = NULL; |
| 508 | if (!ret) |
| 509 | ret = controller->error; |
| 510 | spin_unlock_irqrestore(&controller->lock, flags); |
| 511 | return ret; |
| 512 | } |
| 513 | |
| 514 | static int spi_qup_setup(struct spi_device *spi) |
| 515 | { |
| 516 | struct spi_qup *controller = spi_master_get_devdata(spi->master); |
| 517 | struct spi_qup_device *chip = spi_get_ctldata(spi); |
| 518 | |
Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 519 | if (!chip) { |
| 520 | /* First setup */ |
| 521 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
| 522 | if (!chip) { |
| 523 | dev_err(controller->dev, "no memory for chip data\n"); |
| 524 | return -ENOMEM; |
| 525 | } |
| 526 | |
| 527 | chip->mode = spi->mode; |
| 528 | chip->select = spi->chip_select; |
| 529 | spi_set_ctldata(spi, chip); |
| 530 | } |
| 531 | |
| 532 | return 0; |
| 533 | } |
| 534 | |
| 535 | static void spi_qup_cleanup(struct spi_device *spi) |
| 536 | { |
| 537 | struct spi_qup_device *chip = spi_get_ctldata(spi); |
| 538 | |
| 539 | if (!chip) |
| 540 | return; |
| 541 | |
| 542 | spi_set_ctldata(spi, NULL); |
| 543 | kfree(chip); |
| 544 | } |
| 545 | |
| 546 | static int spi_qup_probe(struct platform_device *pdev) |
| 547 | { |
| 548 | struct spi_master *master; |
| 549 | struct clk *iclk, *cclk; |
| 550 | struct spi_qup *controller; |
| 551 | struct resource *res; |
| 552 | struct device *dev; |
| 553 | void __iomem *base; |
| 554 | u32 data, max_freq, iomode; |
| 555 | int ret, irq, size; |
| 556 | |
| 557 | dev = &pdev->dev; |
| 558 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 559 | base = devm_ioremap_resource(dev, res); |
| 560 | if (IS_ERR(base)) |
| 561 | return PTR_ERR(base); |
| 562 | |
| 563 | irq = platform_get_irq(pdev, 0); |
| 564 | |
| 565 | if (irq < 0) |
| 566 | return irq; |
| 567 | |
| 568 | cclk = devm_clk_get(dev, "core"); |
| 569 | if (IS_ERR(cclk)) |
| 570 | return PTR_ERR(cclk); |
| 571 | |
| 572 | iclk = devm_clk_get(dev, "iface"); |
| 573 | if (IS_ERR(iclk)) |
| 574 | return PTR_ERR(iclk); |
| 575 | |
| 576 | /* This is optional parameter */ |
| 577 | if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) |
| 578 | max_freq = SPI_MAX_RATE; |
| 579 | |
| 580 | if (!max_freq || max_freq > SPI_MAX_RATE) { |
| 581 | dev_err(dev, "invalid clock frequency %d\n", max_freq); |
| 582 | return -ENXIO; |
| 583 | } |
| 584 | |
| 585 | ret = clk_prepare_enable(cclk); |
| 586 | if (ret) { |
| 587 | dev_err(dev, "cannot enable core clock\n"); |
| 588 | return ret; |
| 589 | } |
| 590 | |
| 591 | ret = clk_prepare_enable(iclk); |
| 592 | if (ret) { |
| 593 | clk_disable_unprepare(cclk); |
| 594 | dev_err(dev, "cannot enable iface clock\n"); |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | data = readl_relaxed(base + QUP_HW_VERSION); |
| 599 | |
| 600 | if (data < QUP_HW_VERSION_2_1_1) { |
| 601 | clk_disable_unprepare(cclk); |
| 602 | clk_disable_unprepare(iclk); |
| 603 | dev_err(dev, "v.%08x is not supported\n", data); |
| 604 | return -ENXIO; |
| 605 | } |
| 606 | |
| 607 | master = spi_alloc_master(dev, sizeof(struct spi_qup)); |
| 608 | if (!master) { |
| 609 | clk_disable_unprepare(cclk); |
| 610 | clk_disable_unprepare(iclk); |
| 611 | dev_err(dev, "cannot allocate master\n"); |
| 612 | return -ENOMEM; |
| 613 | } |
| 614 | |
| 615 | master->bus_num = pdev->id; |
| 616 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
| 617 | master->num_chipselect = SPI_NUM_CHIPSELECTS; |
| 618 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
Axel Lin | cb64ca5 | 2014-02-21 09:34:16 +0800 | [diff] [blame^] | 619 | master->max_speed_hz = max_freq; |
Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 620 | master->setup = spi_qup_setup; |
| 621 | master->cleanup = spi_qup_cleanup; |
| 622 | master->set_cs = spi_qup_set_cs; |
| 623 | master->transfer_one = spi_qup_transfer_one; |
| 624 | master->dev.of_node = pdev->dev.of_node; |
| 625 | master->auto_runtime_pm = true; |
| 626 | |
| 627 | platform_set_drvdata(pdev, master); |
| 628 | |
| 629 | controller = spi_master_get_devdata(master); |
| 630 | |
| 631 | controller->dev = dev; |
| 632 | controller->base = base; |
| 633 | controller->iclk = iclk; |
| 634 | controller->cclk = cclk; |
| 635 | controller->irq = irq; |
Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 636 | |
| 637 | spin_lock_init(&controller->lock); |
| 638 | init_completion(&controller->done); |
| 639 | |
| 640 | iomode = readl_relaxed(base + QUP_IO_M_MODES); |
| 641 | |
| 642 | size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); |
| 643 | if (size) |
| 644 | controller->out_blk_sz = size * 16; |
| 645 | else |
| 646 | controller->out_blk_sz = 4; |
| 647 | |
| 648 | size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); |
| 649 | if (size) |
| 650 | controller->in_blk_sz = size * 16; |
| 651 | else |
| 652 | controller->in_blk_sz = 4; |
| 653 | |
| 654 | size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); |
| 655 | controller->out_fifo_sz = controller->out_blk_sz * (2 << size); |
| 656 | |
| 657 | size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); |
| 658 | controller->in_fifo_sz = controller->in_blk_sz * (2 << size); |
| 659 | |
| 660 | dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", |
| 661 | data, controller->in_blk_sz, controller->in_fifo_sz, |
| 662 | controller->out_blk_sz, controller->out_fifo_sz); |
| 663 | |
| 664 | writel_relaxed(1, base + QUP_SW_RESET); |
| 665 | |
| 666 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); |
| 667 | if (ret) { |
| 668 | dev_err(dev, "cannot set RESET state\n"); |
| 669 | goto error; |
| 670 | } |
| 671 | |
| 672 | writel_relaxed(0, base + QUP_OPERATIONAL); |
| 673 | writel_relaxed(0, base + QUP_IO_M_MODES); |
| 674 | writel_relaxed(0, base + QUP_OPERATIONAL_MASK); |
| 675 | writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, |
| 676 | base + SPI_ERROR_FLAGS_EN); |
| 677 | |
| 678 | writel_relaxed(0, base + SPI_CONFIG); |
| 679 | writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); |
| 680 | |
| 681 | ret = devm_request_irq(dev, irq, spi_qup_qup_irq, |
| 682 | IRQF_TRIGGER_HIGH, pdev->name, controller); |
| 683 | if (ret) |
| 684 | goto error; |
| 685 | |
| 686 | ret = devm_spi_register_master(dev, master); |
| 687 | if (ret) |
| 688 | goto error; |
| 689 | |
| 690 | pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); |
| 691 | pm_runtime_use_autosuspend(dev); |
| 692 | pm_runtime_set_active(dev); |
| 693 | pm_runtime_enable(dev); |
| 694 | return 0; |
| 695 | |
| 696 | error: |
| 697 | clk_disable_unprepare(cclk); |
| 698 | clk_disable_unprepare(iclk); |
| 699 | spi_master_put(master); |
| 700 | return ret; |
| 701 | } |
| 702 | |
| 703 | #ifdef CONFIG_PM_RUNTIME |
| 704 | static int spi_qup_pm_suspend_runtime(struct device *device) |
| 705 | { |
| 706 | struct spi_master *master = dev_get_drvdata(device); |
| 707 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 708 | u32 config; |
| 709 | |
| 710 | /* Enable clocks auto gaiting */ |
| 711 | config = readl(controller->base + QUP_CONFIG); |
| 712 | config |= QUP_CLOCK_AUTO_GATE; |
| 713 | writel_relaxed(config, controller->base + QUP_CONFIG); |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | static int spi_qup_pm_resume_runtime(struct device *device) |
| 718 | { |
| 719 | struct spi_master *master = dev_get_drvdata(device); |
| 720 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 721 | u32 config; |
| 722 | |
| 723 | /* Disable clocks auto gaiting */ |
| 724 | config = readl_relaxed(controller->base + QUP_CONFIG); |
| 725 | config &= ~QUP_CLOCK_AUTO_GATE; |
| 726 | writel_relaxed(config, controller->base + QUP_CONFIG); |
| 727 | return 0; |
| 728 | } |
| 729 | #endif /* CONFIG_PM_RUNTIME */ |
| 730 | |
| 731 | #ifdef CONFIG_PM_SLEEP |
| 732 | static int spi_qup_suspend(struct device *device) |
| 733 | { |
| 734 | struct spi_master *master = dev_get_drvdata(device); |
| 735 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 736 | int ret; |
| 737 | |
| 738 | ret = spi_master_suspend(master); |
| 739 | if (ret) |
| 740 | return ret; |
| 741 | |
| 742 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); |
| 743 | if (ret) |
| 744 | return ret; |
| 745 | |
| 746 | clk_disable_unprepare(controller->cclk); |
| 747 | clk_disable_unprepare(controller->iclk); |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | static int spi_qup_resume(struct device *device) |
| 752 | { |
| 753 | struct spi_master *master = dev_get_drvdata(device); |
| 754 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 755 | int ret; |
| 756 | |
| 757 | ret = clk_prepare_enable(controller->iclk); |
| 758 | if (ret) |
| 759 | return ret; |
| 760 | |
| 761 | ret = clk_prepare_enable(controller->cclk); |
| 762 | if (ret) |
| 763 | return ret; |
| 764 | |
| 765 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); |
| 766 | if (ret) |
| 767 | return ret; |
| 768 | |
| 769 | return spi_master_resume(master); |
| 770 | } |
| 771 | #endif /* CONFIG_PM_SLEEP */ |
| 772 | |
| 773 | static int spi_qup_remove(struct platform_device *pdev) |
| 774 | { |
| 775 | struct spi_master *master = dev_get_drvdata(&pdev->dev); |
| 776 | struct spi_qup *controller = spi_master_get_devdata(master); |
| 777 | int ret; |
| 778 | |
| 779 | ret = pm_runtime_get_sync(&pdev->dev); |
| 780 | if (ret) |
| 781 | return ret; |
| 782 | |
| 783 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); |
| 784 | if (ret) |
| 785 | return ret; |
| 786 | |
| 787 | clk_disable_unprepare(controller->cclk); |
| 788 | clk_disable_unprepare(controller->iclk); |
| 789 | |
| 790 | pm_runtime_put_noidle(&pdev->dev); |
| 791 | pm_runtime_disable(&pdev->dev); |
Ivan T. Ivanov | 64ff247 | 2014-02-13 18:21:38 +0200 | [diff] [blame] | 792 | return 0; |
| 793 | } |
| 794 | |
| 795 | static struct of_device_id spi_qup_dt_match[] = { |
| 796 | { .compatible = "qcom,spi-qup-v2.1.1", }, |
| 797 | { .compatible = "qcom,spi-qup-v2.2.1", }, |
| 798 | { } |
| 799 | }; |
| 800 | MODULE_DEVICE_TABLE(of, spi_qup_dt_match); |
| 801 | |
| 802 | static const struct dev_pm_ops spi_qup_dev_pm_ops = { |
| 803 | SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume) |
| 804 | SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime, |
| 805 | spi_qup_pm_resume_runtime, |
| 806 | NULL) |
| 807 | }; |
| 808 | |
| 809 | static struct platform_driver spi_qup_driver = { |
| 810 | .driver = { |
| 811 | .name = "spi_qup", |
| 812 | .owner = THIS_MODULE, |
| 813 | .pm = &spi_qup_dev_pm_ops, |
| 814 | .of_match_table = spi_qup_dt_match, |
| 815 | }, |
| 816 | .probe = spi_qup_probe, |
| 817 | .remove = spi_qup_remove, |
| 818 | }; |
| 819 | module_platform_driver(spi_qup_driver); |
| 820 | |
| 821 | MODULE_LICENSE("GPL v2"); |
| 822 | MODULE_VERSION("0.4"); |
| 823 | MODULE_ALIAS("platform:spi_qup"); |