Larry Finger | 94a7994 | 2011-08-23 19:00:42 -0500 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. |
| 3 | * |
| 4 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 5 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 6 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 7 | * more details. |
| 8 | * |
| 9 | * You should have received a copy of the GNU General Public License along with |
| 10 | * this program; if not, write to the Free Software Foundation, Inc., |
| 11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in the |
| 14 | * file called LICENSE. |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * wlanfae <wlanfae@realtek.com> |
| 18 | ******************************************************************************/ |
| 19 | #if (defined(RTL8192E) || defined(RTL8190P)) |
| 20 | |
| 21 | |
| 22 | #include "rtl_core.h" |
| 23 | #include "r8192E_hw.h" |
| 24 | #include "r8192E_phyreg.h" |
| 25 | #include "r8190P_rtl8256.h" |
| 26 | #include "r8192E_phy.h" |
| 27 | #include "rtl_dm.h" |
| 28 | #ifdef ENABLE_DOT11D |
| 29 | #include "dot11d.h" |
| 30 | #endif |
| 31 | |
| 32 | #ifdef RTL8190P |
| 33 | #include "r8190P_hwimg.h" |
| 34 | #endif |
| 35 | |
| 36 | #ifdef RTL8192E |
| 37 | #include "r8192E_hwimg.h" |
| 38 | #endif |
| 39 | |
| 40 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { |
| 41 | 0, |
| 42 | 0x085c, |
| 43 | 0x08dc, |
| 44 | 0x095c, |
| 45 | 0x09dc, |
| 46 | 0x0a5c, |
| 47 | 0x0adc, |
| 48 | 0x0b5c, |
| 49 | 0x0bdc, |
| 50 | 0x0c5c, |
| 51 | 0x0cdc, |
| 52 | 0x0d5c, |
| 53 | 0x0ddc, |
| 54 | 0x0e5c, |
| 55 | 0x0f72, |
| 56 | }; |
| 57 | |
| 58 | /*************************Define local function prototype**********************/ |
| 59 | |
| 60 | static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); |
| 61 | static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data); |
| 62 | u32 rtl8192_CalculateBitShift(u32 dwBitMask) |
| 63 | { |
| 64 | u32 i; |
| 65 | for (i=0; i<=31; i++) |
| 66 | { |
| 67 | if (((dwBitMask>>i)&0x1) == 1) |
| 68 | break; |
| 69 | } |
| 70 | return i; |
| 71 | } |
| 72 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) |
| 73 | { |
| 74 | u8 ret = 1; |
| 75 | struct r8192_priv *priv = rtllib_priv(dev); |
| 76 | #ifdef RTL8190P |
| 77 | if (priv->rf_type == RF_2T4R) |
| 78 | { |
| 79 | ret= 1; |
| 80 | } |
| 81 | else if (priv->rf_type == RF_1T2R) |
| 82 | { |
| 83 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
| 84 | ret = 0; |
| 85 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) |
| 86 | ret = 1; |
| 87 | } |
| 88 | #else |
| 89 | #ifdef RTL8192E |
| 90 | if (priv->rf_type == RF_2T4R) |
| 91 | ret = 0; |
| 92 | else if (priv->rf_type == RF_1T2R) |
| 93 | { |
| 94 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
| 95 | ret = 1; |
| 96 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) |
| 97 | ret = 0; |
| 98 | } |
| 99 | #endif |
| 100 | #endif |
| 101 | return ret; |
| 102 | } |
| 103 | void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) |
| 104 | { |
| 105 | |
| 106 | u32 OriginalValue, BitShift, NewValue; |
| 107 | |
| 108 | if (dwBitMask!= bMaskDWord) |
| 109 | { |
| 110 | OriginalValue = read_nic_dword(dev, dwRegAddr); |
| 111 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
| 112 | NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); |
| 113 | write_nic_dword(dev, dwRegAddr, NewValue); |
| 114 | }else |
| 115 | write_nic_dword(dev, dwRegAddr, dwData); |
| 116 | return; |
| 117 | } |
| 118 | u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) |
| 119 | { |
| 120 | u32 Ret = 0, OriginalValue, BitShift; |
| 121 | |
| 122 | OriginalValue = read_nic_dword(dev, dwRegAddr); |
| 123 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
| 124 | Ret = (OriginalValue & dwBitMask) >> BitShift; |
| 125 | |
| 126 | return (Ret); |
| 127 | } |
| 128 | u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) |
| 129 | { |
| 130 | struct r8192_priv *priv = rtllib_priv(dev); |
| 131 | u32 ret = 0; |
| 132 | u32 NewOffset = 0; |
| 133 | BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; |
| 134 | Offset &= 0x3f; |
| 135 | |
| 136 | if (priv->rf_chip == RF_8256) |
| 137 | { |
| 138 | #ifdef RTL8190P |
| 139 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
| 140 | #else |
| 141 | #ifdef RTL8192E |
| 142 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
| 143 | #endif |
| 144 | #endif |
| 145 | if (Offset >= 31) |
| 146 | { |
| 147 | priv->RfReg0Value[eRFPath] |= 0x140; |
| 148 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); |
| 149 | NewOffset = Offset -30; |
| 150 | } |
| 151 | else if (Offset >= 16) |
| 152 | { |
| 153 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 154 | priv->RfReg0Value[eRFPath] &= (~0x40); |
| 155 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); |
| 156 | |
| 157 | NewOffset = Offset - 15; |
| 158 | } |
| 159 | else |
| 160 | NewOffset = Offset; |
| 161 | } |
| 162 | else |
| 163 | { |
| 164 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); |
| 165 | NewOffset = Offset; |
| 166 | } |
| 167 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); |
| 168 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
| 169 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); |
| 170 | |
| 171 | |
| 172 | msleep(1); |
| 173 | |
| 174 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); |
| 175 | |
| 176 | |
| 177 | if (priv->rf_chip == RF_8256) |
| 178 | { |
| 179 | priv->RfReg0Value[eRFPath] &= 0xebf; |
| 180 | |
| 181 | rtl8192_setBBreg( |
| 182 | dev, |
| 183 | pPhyReg->rf3wireOffset, |
| 184 | bMaskDWord, |
| 185 | (priv->RfReg0Value[eRFPath] << 16)); |
| 186 | |
| 187 | #ifdef RTL8190P |
| 188 | if (priv->rf_type == RF_2T4R) |
| 189 | { |
| 190 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf); |
| 191 | } |
| 192 | else if (priv->rf_type == RF_1T2R) |
| 193 | { |
| 194 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3); |
| 195 | } |
| 196 | #else |
| 197 | #ifdef RTL8192E |
| 198 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
| 199 | #endif |
| 200 | #endif |
| 201 | } |
| 202 | |
| 203 | |
| 204 | return ret; |
| 205 | |
| 206 | } |
| 207 | |
| 208 | void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) |
| 209 | { |
| 210 | struct r8192_priv *priv = rtllib_priv(dev); |
| 211 | u32 DataAndAddr = 0, NewOffset = 0; |
| 212 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
| 213 | |
| 214 | Offset &= 0x3f; |
| 215 | if (priv->rf_chip == RF_8256) |
| 216 | { |
| 217 | |
| 218 | #ifdef RTL8190P |
| 219 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
| 220 | #else |
| 221 | #ifdef RTL8192E |
| 222 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
| 223 | #endif |
| 224 | #endif |
| 225 | |
| 226 | if (Offset >= 31) |
| 227 | { |
| 228 | priv->RfReg0Value[eRFPath] |= 0x140; |
| 229 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); |
| 230 | NewOffset = Offset - 30; |
| 231 | } |
| 232 | else if (Offset >= 16) |
| 233 | { |
| 234 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 235 | priv->RfReg0Value[eRFPath] &= (~0x40); |
| 236 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); |
| 237 | NewOffset = Offset - 15; |
| 238 | } |
| 239 | else |
| 240 | NewOffset = Offset; |
| 241 | } |
| 242 | else |
| 243 | { |
| 244 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); |
| 245 | NewOffset = Offset; |
| 246 | } |
| 247 | |
| 248 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); |
| 249 | |
| 250 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); |
| 251 | |
| 252 | |
| 253 | if (Offset==0x0) |
| 254 | priv->RfReg0Value[eRFPath] = Data; |
| 255 | |
| 256 | if (priv->rf_chip == RF_8256) |
| 257 | { |
| 258 | if (Offset != 0) |
| 259 | { |
| 260 | priv->RfReg0Value[eRFPath] &= 0xebf; |
| 261 | rtl8192_setBBreg( |
| 262 | dev, |
| 263 | pPhyReg->rf3wireOffset, |
| 264 | bMaskDWord, |
| 265 | (priv->RfReg0Value[eRFPath] << 16)); |
| 266 | } |
| 267 | #ifdef RTL8190P |
| 268 | if (priv->rf_type == RF_2T4R) |
| 269 | { |
| 270 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf); |
| 271 | } |
| 272 | else if (priv->rf_type == RF_1T2R) |
| 273 | { |
| 274 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3); |
| 275 | } |
| 276 | #else |
| 277 | #ifdef RTL8192E |
| 278 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
| 279 | #endif |
| 280 | #endif |
| 281 | } |
| 282 | |
| 283 | return; |
| 284 | } |
| 285 | |
| 286 | void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) |
| 287 | { |
| 288 | struct r8192_priv *priv = rtllib_priv(dev); |
| 289 | u32 Original_Value, BitShift, New_Value; |
| 290 | |
| 291 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 292 | return; |
| 293 | #ifdef RTL8192E |
| 294 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
| 295 | return; |
| 296 | #endif |
| 297 | |
| 298 | RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); |
| 299 | if (priv->Rf_Mode == RF_OP_By_FW) |
| 300 | { |
| 301 | if (BitMask != bMask12Bits) |
| 302 | { |
| 303 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
| 304 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 305 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); |
| 306 | |
| 307 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); |
| 308 | }else |
| 309 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); |
| 310 | udelay(200); |
| 311 | |
| 312 | } |
| 313 | else |
| 314 | { |
| 315 | if (BitMask != bMask12Bits) |
| 316 | { |
| 317 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); |
| 318 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 319 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); |
| 320 | |
| 321 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); |
| 322 | }else |
| 323 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); |
| 324 | } |
| 325 | return; |
| 326 | } |
| 327 | |
| 328 | u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) |
| 329 | { |
| 330 | u32 Original_Value, Readback_Value, BitShift; |
| 331 | struct r8192_priv *priv = rtllib_priv(dev); |
| 332 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 333 | return 0; |
| 334 | #ifdef RTL8192E |
| 335 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
| 336 | return 0; |
| 337 | #endif |
| 338 | down(&priv->rf_sem); |
| 339 | if (priv->Rf_Mode == RF_OP_By_FW) |
| 340 | { |
| 341 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
| 342 | udelay(200); |
| 343 | } |
| 344 | else |
| 345 | { |
| 346 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); |
| 347 | |
| 348 | } |
| 349 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 350 | Readback_Value = (Original_Value & BitMask) >> BitShift; |
| 351 | up(&priv->rf_sem); |
| 352 | return (Readback_Value); |
| 353 | } |
| 354 | |
| 355 | static u32 phy_FwRFSerialRead( |
| 356 | struct net_device* dev, |
| 357 | RF90_RADIO_PATH_E eRFPath, |
| 358 | u32 Offset ) |
| 359 | { |
| 360 | u32 retValue = 0; |
| 361 | u32 Data = 0; |
| 362 | u8 time = 0; |
| 363 | Data |= ((Offset&0xFF)<<12); |
| 364 | Data |= ((eRFPath&0x3)<<20); |
| 365 | Data |= 0x80000000; |
| 366 | while (read_nic_dword(dev, QPNR)&0x80000000) |
| 367 | { |
| 368 | if (time++ < 100) |
| 369 | { |
| 370 | udelay(10); |
| 371 | } |
| 372 | else |
| 373 | break; |
| 374 | } |
| 375 | write_nic_dword(dev, QPNR, Data); |
| 376 | while (read_nic_dword(dev, QPNR)&0x80000000) |
| 377 | { |
| 378 | if (time++ < 100) |
| 379 | { |
| 380 | udelay(10); |
| 381 | } |
| 382 | else |
| 383 | return (0); |
| 384 | } |
| 385 | retValue = read_nic_dword(dev, RF_DATA); |
| 386 | |
| 387 | return (retValue); |
| 388 | |
| 389 | } /* phy_FwRFSerialRead */ |
| 390 | |
| 391 | static void |
| 392 | phy_FwRFSerialWrite( |
| 393 | struct net_device* dev, |
| 394 | RF90_RADIO_PATH_E eRFPath, |
| 395 | u32 Offset, |
| 396 | u32 Data ) |
| 397 | { |
| 398 | u8 time = 0; |
| 399 | |
| 400 | |
| 401 | Data |= ((Offset&0xFF)<<12); |
| 402 | Data |= ((eRFPath&0x3)<<20); |
| 403 | Data |= 0x400000; |
| 404 | Data |= 0x80000000; |
| 405 | |
| 406 | while (read_nic_dword(dev, QPNR)&0x80000000) |
| 407 | { |
| 408 | if (time++ < 100) |
| 409 | { |
| 410 | udelay(10); |
| 411 | } |
| 412 | else |
| 413 | break; |
| 414 | } |
| 415 | write_nic_dword(dev, QPNR, Data); |
| 416 | |
| 417 | } /* phy_FwRFSerialWrite */ |
| 418 | |
| 419 | |
| 420 | void rtl8192_phy_configmac(struct net_device* dev) |
| 421 | { |
| 422 | u32 dwArrayLen = 0, i = 0; |
| 423 | u32* pdwArray = NULL; |
| 424 | struct r8192_priv *priv = rtllib_priv(dev); |
| 425 | #ifdef TO_DO_LIST |
| 426 | if (dev->bInHctTest) |
| 427 | { |
| 428 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n"); |
| 429 | dwArrayLen = MACPHY_ArrayLengthDTM; |
| 430 | pdwArray = Rtl819XMACPHY_ArrayDTM; |
| 431 | } |
| 432 | else if (priv->bTXPowerDataReadFromEEPORM) |
| 433 | #endif |
| 434 | if (priv->bTXPowerDataReadFromEEPORM) |
| 435 | { |
| 436 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
| 437 | dwArrayLen = MACPHY_Array_PGLength; |
| 438 | pdwArray = Rtl819XMACPHY_Array_PG; |
| 439 | |
| 440 | } |
| 441 | else |
| 442 | { |
| 443 | RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n"); |
| 444 | dwArrayLen = MACPHY_ArrayLength; |
| 445 | pdwArray = Rtl819XMACPHY_Array; |
| 446 | } |
| 447 | for (i = 0; i<dwArrayLen; i=i+3){ |
| 448 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", |
| 449 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
| 450 | if (pdwArray[i] == 0x318) |
| 451 | { |
| 452 | pdwArray[i+2] = 0x00000800; |
| 453 | } |
| 454 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
| 455 | } |
| 456 | return; |
| 457 | |
| 458 | } |
| 459 | |
| 460 | void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) |
| 461 | { |
| 462 | int i; |
| 463 | u32* Rtl819XPHY_REGArray_Table = NULL; |
| 464 | u32* Rtl819XAGCTAB_Array_Table = NULL; |
| 465 | u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; |
| 466 | struct r8192_priv *priv = rtllib_priv(dev); |
| 467 | #ifdef TO_DO_LIST |
| 468 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; |
| 469 | if (dev->bInHctTest) |
| 470 | { |
| 471 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; |
| 472 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; |
| 473 | |
| 474 | if (priv->RF_Type == RF_2T4R) |
| 475 | { |
| 476 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; |
| 477 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; |
| 478 | } |
| 479 | else if (priv->RF_Type == RF_1T2R) |
| 480 | { |
| 481 | PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM; |
| 482 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM; |
| 483 | } |
| 484 | } |
| 485 | else |
| 486 | #endif |
| 487 | { |
| 488 | AGCTAB_ArrayLen = AGCTAB_ArrayLength; |
| 489 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; |
| 490 | if (priv->rf_type == RF_2T4R) |
| 491 | { |
| 492 | PHY_REGArrayLen = PHY_REGArrayLength; |
| 493 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; |
| 494 | } |
| 495 | else if (priv->rf_type == RF_1T2R) |
| 496 | { |
| 497 | PHY_REGArrayLen = PHY_REG_1T2RArrayLength; |
| 498 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | if (ConfigType == BaseBand_Config_PHY_REG) |
| 503 | { |
| 504 | for (i=0; i<PHY_REGArrayLen; i+=2) |
| 505 | { |
| 506 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); |
| 507 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); |
| 508 | } |
| 509 | } |
| 510 | else if (ConfigType == BaseBand_Config_AGC_TAB) |
| 511 | { |
| 512 | for (i=0; i<AGCTAB_ArrayLen; i+=2) |
| 513 | { |
| 514 | rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); |
| 515 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); |
| 516 | } |
| 517 | } |
| 518 | return; |
| 519 | |
| 520 | |
| 521 | } |
| 522 | void rtl8192_InitBBRFRegDef(struct net_device* dev) |
| 523 | { |
| 524 | struct r8192_priv *priv = rtllib_priv(dev); |
| 525 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
| 526 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
| 527 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; |
| 528 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; |
| 529 | |
| 530 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; |
| 531 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; |
| 532 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; |
| 533 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; |
| 534 | |
| 535 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; |
| 536 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; |
| 537 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; |
| 538 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; |
| 539 | |
| 540 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; |
| 541 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; |
| 542 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; |
| 543 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; |
| 544 | |
| 545 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; |
| 546 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; |
| 547 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; |
| 548 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; |
| 549 | |
| 550 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
| 551 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
| 552 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 553 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 554 | |
| 555 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; |
| 556 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; |
| 557 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; |
| 558 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; |
| 559 | |
| 560 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; |
| 561 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; |
| 562 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; |
| 563 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; |
| 564 | |
| 565 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; |
| 566 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; |
| 567 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; |
| 568 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; |
| 569 | |
| 570 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
| 571 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
| 572 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 573 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 574 | |
| 575 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; |
| 576 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; |
| 577 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; |
| 578 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; |
| 579 | |
| 580 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; |
| 581 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; |
| 582 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; |
| 583 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; |
| 584 | |
| 585 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; |
| 586 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; |
| 587 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; |
| 588 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; |
| 589 | |
| 590 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; |
| 591 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; |
| 592 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; |
| 593 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; |
| 594 | |
| 595 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; |
| 596 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; |
| 597 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; |
| 598 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; |
| 599 | |
| 600 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; |
| 601 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; |
| 602 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; |
| 603 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; |
| 604 | |
| 605 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; |
| 606 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; |
| 607 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; |
| 608 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; |
| 609 | |
| 610 | } |
| 611 | bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) |
| 612 | { |
| 613 | bool ret = true; |
| 614 | u32 i, CheckTimes = 4, dwRegRead = 0; |
| 615 | u32 WriteAddr[4]; |
| 616 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; |
| 617 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
| 618 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; |
| 619 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; |
| 620 | WriteAddr[HW90_BLOCK_RF] = 0x3; |
| 621 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock); |
| 622 | for (i=0 ; i < CheckTimes ; i++) |
| 623 | { |
| 624 | |
| 625 | switch (CheckBlock) |
| 626 | { |
| 627 | case HW90_BLOCK_MAC: |
| 628 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); |
| 629 | break; |
| 630 | |
| 631 | case HW90_BLOCK_PHY0: |
| 632 | case HW90_BLOCK_PHY1: |
| 633 | write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); |
| 634 | dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); |
| 635 | break; |
| 636 | |
| 637 | case HW90_BLOCK_RF: |
| 638 | WriteData[i] &= 0xfff; |
| 639 | rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); |
| 640 | mdelay(10); |
| 641 | dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); |
| 642 | mdelay(10); |
| 643 | break; |
| 644 | |
| 645 | default: |
| 646 | ret = false; |
| 647 | break; |
| 648 | } |
| 649 | |
| 650 | |
| 651 | if (dwRegRead != WriteData[i]) |
| 652 | { |
| 653 | RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); |
| 654 | ret = false; |
| 655 | break; |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | return ret; |
| 660 | } |
| 661 | |
| 662 | bool rtl8192_BB_Config_ParaFile(struct net_device* dev) |
| 663 | { |
| 664 | struct r8192_priv *priv = rtllib_priv(dev); |
| 665 | bool rtStatus = true; |
| 666 | u8 bRegValue = 0, eCheckItem = 0; |
| 667 | u32 dwRegValue = 0; |
| 668 | /************************************** |
| 669 | **************************************/ |
| 670 | |
| 671 | bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); |
| 672 | write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); |
| 673 | |
| 674 | dwRegValue = read_nic_dword(dev, CPU_GEN); |
| 675 | write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); |
| 676 | |
| 677 | for (eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) |
| 678 | { |
| 679 | rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); |
| 680 | if (rtStatus != true) |
| 681 | { |
| 682 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); |
| 683 | return rtStatus; |
| 684 | } |
| 685 | } |
| 686 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); |
| 687 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); |
| 688 | |
| 689 | dwRegValue = read_nic_dword(dev, CPU_GEN); |
| 690 | write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); |
| 691 | |
| 692 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); |
| 693 | |
| 694 | if (priv->IC_Cut > VERSION_8190_BD) |
| 695 | { |
| 696 | if (priv->rf_type == RF_2T4R) |
| 697 | { |
| 698 | dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 | |
| 699 | priv->AntennaTxPwDiff[1]<<4 | |
| 700 | priv->AntennaTxPwDiff[0]); |
| 701 | } |
| 702 | else |
| 703 | dwRegValue = 0x0; |
| 704 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, |
| 705 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); |
| 706 | |
| 707 | |
| 708 | #ifdef RTL8190P |
| 709 | dwRegValue = priv->CrystalCap & 0x3; |
| 710 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue); |
| 711 | dwRegValue = ((priv->CrystalCap & 0xc)>>2); |
| 712 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue); |
| 713 | #else |
| 714 | #ifdef RTL8192E |
| 715 | dwRegValue = priv->CrystalCap; |
| 716 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); |
| 717 | #endif |
| 718 | #endif |
| 719 | |
| 720 | } |
| 721 | |
| 722 | return rtStatus; |
| 723 | } |
| 724 | bool rtl8192_BBConfig(struct net_device* dev) |
| 725 | { |
| 726 | bool rtStatus = true; |
| 727 | rtl8192_InitBBRFRegDef(dev); |
| 728 | rtStatus = rtl8192_BB_Config_ParaFile(dev); |
| 729 | return rtStatus; |
| 730 | } |
| 731 | |
| 732 | void rtl8192_phy_getTxPower(struct net_device* dev) |
| 733 | { |
| 734 | struct r8192_priv *priv = rtllib_priv(dev); |
| 735 | #ifdef RTL8190P |
| 736 | priv->MCSTxPowerLevelOriginalOffset[0] = |
| 737 | read_nic_dword(dev, MCS_TXAGC); |
| 738 | priv->MCSTxPowerLevelOriginalOffset[1] = |
| 739 | read_nic_dword(dev, (MCS_TXAGC+4)); |
| 740 | priv->CCKTxPowerLevelOriginalOffset = |
| 741 | read_nic_dword(dev, CCK_TXAGC); |
| 742 | #else |
| 743 | #ifdef RTL8192E |
| 744 | priv->MCSTxPowerLevelOriginalOffset[0] = |
| 745 | read_nic_dword(dev, rTxAGC_Rate18_06); |
| 746 | priv->MCSTxPowerLevelOriginalOffset[1] = |
| 747 | read_nic_dword(dev, rTxAGC_Rate54_24); |
| 748 | priv->MCSTxPowerLevelOriginalOffset[2] = |
| 749 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); |
| 750 | priv->MCSTxPowerLevelOriginalOffset[3] = |
| 751 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); |
| 752 | priv->MCSTxPowerLevelOriginalOffset[4] = |
| 753 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); |
| 754 | priv->MCSTxPowerLevelOriginalOffset[5] = |
| 755 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); |
| 756 | #endif |
| 757 | #endif |
| 758 | |
| 759 | priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); |
| 760 | priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); |
| 761 | priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); |
| 762 | priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); |
| 763 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", |
| 764 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
| 765 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); |
| 766 | |
| 767 | priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); |
| 768 | priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); |
| 769 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", |
| 770 | rOFDM0_RxDetector3, priv->framesync); |
| 771 | priv->SifsTime = read_nic_word(dev, SIFS); |
| 772 | return; |
| 773 | } |
| 774 | |
| 775 | void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) |
| 776 | { |
| 777 | struct r8192_priv *priv = rtllib_priv(dev); |
| 778 | u8 powerlevel = 0,powerlevelOFDM24G = 0; |
| 779 | char ant_pwr_diff; |
| 780 | u32 u4RegValue; |
| 781 | |
| 782 | if (priv->epromtype == EEPROM_93C46) |
| 783 | { |
| 784 | powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 785 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 786 | } |
| 787 | else if (priv->epromtype == EEPROM_93C56) |
| 788 | { |
| 789 | if (priv->rf_type == RF_1T2R) |
| 790 | { |
| 791 | powerlevel = priv->TxPowerLevelCCK_C[channel-1]; |
| 792 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; |
| 793 | } |
| 794 | else if (priv->rf_type == RF_2T4R) |
| 795 | { |
| 796 | powerlevel = priv->TxPowerLevelCCK_A[channel-1]; |
| 797 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; |
| 798 | |
| 799 | ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] |
| 800 | -priv->TxPowerLevelOFDM24G_A[channel-1]; |
| 801 | |
| 802 | priv->RF_C_TxPwDiff = ant_pwr_diff; |
| 803 | |
| 804 | ant_pwr_diff &= 0xf; |
| 805 | |
| 806 | priv->AntennaTxPwDiff[2] = 0; |
| 807 | priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); |
| 808 | priv->AntennaTxPwDiff[0] = 0; |
| 809 | |
| 810 | u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | |
| 811 | priv->AntennaTxPwDiff[1]<<4 | |
| 812 | priv->AntennaTxPwDiff[0]); |
| 813 | |
| 814 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, |
| 815 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); |
| 816 | } |
| 817 | } |
Mike McCormack | cb76215 | 2011-07-11 08:56:20 +0900 | [diff] [blame^] | 818 | switch (priv->rf_chip) { |
Larry Finger | 94a7994 | 2011-08-23 19:00:42 -0500 | [diff] [blame] | 819 | case RF_8225: |
| 820 | break; |
| 821 | case RF_8256: |
| 822 | PHY_SetRF8256CCKTxPower(dev, powerlevel); |
| 823 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 824 | break; |
| 825 | case RF_8258: |
| 826 | break; |
| 827 | default: |
| 828 | RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __func__); |
| 829 | break; |
| 830 | } |
| 831 | return; |
| 832 | } |
| 833 | |
| 834 | bool rtl8192_phy_RFConfig(struct net_device* dev) |
| 835 | { |
| 836 | struct r8192_priv *priv = rtllib_priv(dev); |
| 837 | bool rtStatus = true; |
| 838 | switch (priv->rf_chip) |
| 839 | { |
| 840 | case RF_8225: |
| 841 | break; |
| 842 | case RF_8256: |
| 843 | rtStatus = PHY_RF8256_Config(dev); |
| 844 | break; |
| 845 | |
| 846 | case RF_8258: |
| 847 | break; |
| 848 | case RF_PSEUDO_11N: |
| 849 | break; |
| 850 | |
| 851 | default: |
| 852 | RT_TRACE(COMP_ERR, "error chip id\n"); |
| 853 | break; |
| 854 | } |
| 855 | return rtStatus; |
| 856 | } |
| 857 | |
| 858 | void rtl8192_phy_updateInitGain(struct net_device* dev) |
| 859 | { |
| 860 | return; |
| 861 | } |
| 862 | |
| 863 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) |
| 864 | { |
| 865 | |
| 866 | int i; |
| 867 | u8 ret = 0; |
| 868 | |
| 869 | switch (eRFPath){ |
| 870 | case RF90_PATH_A: |
| 871 | for (i = 0;i<RadioA_ArrayLength; i=i+2){ |
| 872 | |
| 873 | if (Rtl819XRadioA_Array[i] == 0xfe){ |
| 874 | msleep(100); |
| 875 | continue; |
| 876 | } |
| 877 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]); |
| 878 | |
| 879 | } |
| 880 | break; |
| 881 | case RF90_PATH_B: |
| 882 | for (i = 0;i<RadioB_ArrayLength; i=i+2){ |
| 883 | |
| 884 | if (Rtl819XRadioB_Array[i] == 0xfe){ |
| 885 | msleep(100); |
| 886 | continue; |
| 887 | } |
| 888 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]); |
| 889 | |
| 890 | } |
| 891 | break; |
| 892 | case RF90_PATH_C: |
| 893 | for (i = 0;i<RadioC_ArrayLength; i=i+2){ |
| 894 | |
| 895 | if (Rtl819XRadioC_Array[i] == 0xfe){ |
| 896 | msleep(100); |
| 897 | continue; |
| 898 | } |
| 899 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]); |
| 900 | |
| 901 | } |
| 902 | break; |
| 903 | case RF90_PATH_D: |
| 904 | for (i = 0;i<RadioD_ArrayLength; i=i+2){ |
| 905 | |
| 906 | if (Rtl819XRadioD_Array[i] == 0xfe){ |
| 907 | msleep(100); |
| 908 | continue; |
| 909 | } |
| 910 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]); |
| 911 | |
| 912 | } |
| 913 | break; |
| 914 | default: |
| 915 | break; |
| 916 | } |
| 917 | |
| 918 | return ret;; |
| 919 | |
| 920 | } |
| 921 | void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
| 922 | { |
| 923 | struct r8192_priv *priv = rtllib_priv(dev); |
| 924 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 925 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 926 | |
| 927 | switch (priv->rf_chip) |
| 928 | { |
| 929 | case RF_8225: |
| 930 | #ifdef TO_DO_LIST |
| 931 | PHY_SetRF8225CckTxPower(dev, powerlevel); |
| 932 | PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G); |
| 933 | #endif |
| 934 | break; |
| 935 | |
| 936 | case RF_8256: |
| 937 | PHY_SetRF8256CCKTxPower(dev, powerlevel); |
| 938 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 939 | break; |
| 940 | |
| 941 | case RF_8258: |
| 942 | break; |
| 943 | default: |
| 944 | RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); |
| 945 | break; |
| 946 | } |
| 947 | return; |
| 948 | } |
| 949 | u8 rtl8192_phy_SetSwChnlCmdArray( |
| 950 | SwChnlCmd* CmdTable, |
| 951 | u32 CmdTableIdx, |
| 952 | u32 CmdTableSz, |
| 953 | SwChnlCmdID CmdID, |
| 954 | u32 Para1, |
| 955 | u32 Para2, |
| 956 | u32 msDelay |
| 957 | ) |
| 958 | { |
| 959 | SwChnlCmd* pCmd; |
| 960 | |
| 961 | if (CmdTable == NULL) |
| 962 | { |
| 963 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); |
| 964 | return false; |
| 965 | } |
| 966 | if (CmdTableIdx >= CmdTableSz) |
| 967 | { |
| 968 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", |
| 969 | CmdTableIdx, CmdTableSz); |
| 970 | return false; |
| 971 | } |
| 972 | |
| 973 | pCmd = CmdTable + CmdTableIdx; |
| 974 | pCmd->CmdID = CmdID; |
| 975 | pCmd->Para1 = Para1; |
| 976 | pCmd->Para2 = Para2; |
| 977 | pCmd->msDelay = msDelay; |
| 978 | |
| 979 | return true; |
| 980 | } |
| 981 | u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) |
| 982 | { |
| 983 | struct r8192_priv *priv = rtllib_priv(dev); |
| 984 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; |
| 985 | u32 PreCommonCmdCnt; |
| 986 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; |
| 987 | u32 PostCommonCmdCnt; |
| 988 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; |
| 989 | u32 RfDependCmdCnt; |
| 990 | SwChnlCmd *CurrentCmd = NULL; |
| 991 | u8 eRFPath; |
| 992 | |
| 993 | RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel); |
| 994 | |
| 995 | #ifdef ENABLE_DOT11D |
| 996 | if (!IsLegalChannel(priv->rtllib, channel)) |
| 997 | { |
| 998 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); |
| 999 | return true; |
| 1000 | } |
| 1001 | #endif |
| 1002 | |
| 1003 | { |
| 1004 | PreCommonCmdCnt = 0; |
| 1005 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 1006 | CmdID_SetTxPowerLevel, 0, 0, 0); |
| 1007 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 1008 | CmdID_End, 0, 0, 0); |
| 1009 | |
| 1010 | PostCommonCmdCnt = 0; |
| 1011 | |
| 1012 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, |
| 1013 | CmdID_End, 0, 0, 0); |
| 1014 | |
| 1015 | RfDependCmdCnt = 0; |
| 1016 | switch ( priv->rf_chip ) |
| 1017 | { |
| 1018 | case RF_8225: |
| 1019 | if (!(channel >= 1 && channel <= 14)) |
| 1020 | { |
| 1021 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); |
| 1022 | return false; |
| 1023 | } |
| 1024 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1025 | CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); |
| 1026 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1027 | CmdID_End, 0, 0, 0); |
| 1028 | break; |
| 1029 | |
| 1030 | case RF_8256: |
| 1031 | if (!(channel >= 1 && channel <= 14)) |
| 1032 | { |
| 1033 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); |
| 1034 | return false; |
| 1035 | } |
| 1036 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1037 | CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); |
| 1038 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1039 | CmdID_End, 0, 0, 0); |
| 1040 | break; |
| 1041 | |
| 1042 | case RF_8258: |
| 1043 | break; |
| 1044 | |
| 1045 | default: |
| 1046 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1047 | return false; |
| 1048 | break; |
| 1049 | } |
| 1050 | |
| 1051 | |
| 1052 | do{ |
| 1053 | switch (*stage) |
| 1054 | { |
| 1055 | case 0: |
| 1056 | CurrentCmd=&PreCommonCmd[*step]; |
| 1057 | break; |
| 1058 | case 1: |
| 1059 | CurrentCmd=&RfDependCmd[*step]; |
| 1060 | break; |
| 1061 | case 2: |
| 1062 | CurrentCmd=&PostCommonCmd[*step]; |
| 1063 | break; |
| 1064 | } |
| 1065 | |
| 1066 | if (CurrentCmd->CmdID==CmdID_End) |
| 1067 | { |
| 1068 | if ((*stage)==2) |
| 1069 | { |
| 1070 | return true; |
| 1071 | } |
| 1072 | else |
| 1073 | { |
| 1074 | (*stage)++; |
| 1075 | (*step)=0; |
| 1076 | continue; |
| 1077 | } |
| 1078 | } |
| 1079 | |
| 1080 | switch (CurrentCmd->CmdID) |
| 1081 | { |
| 1082 | case CmdID_SetTxPowerLevel: |
| 1083 | if (priv->IC_Cut > (u8)VERSION_8190_BD) |
| 1084 | rtl8192_SetTxPowerLevel(dev,channel); |
| 1085 | break; |
| 1086 | case CmdID_WritePortUlong: |
| 1087 | write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); |
| 1088 | break; |
| 1089 | case CmdID_WritePortUshort: |
| 1090 | write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); |
| 1091 | break; |
| 1092 | case CmdID_WritePortUchar: |
| 1093 | write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); |
| 1094 | break; |
| 1095 | case CmdID_RF_WriteReg: |
| 1096 | for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) |
| 1097 | rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); |
| 1098 | break; |
| 1099 | default: |
| 1100 | break; |
| 1101 | } |
| 1102 | |
| 1103 | break; |
| 1104 | }while(true); |
| 1105 | }/*for (Number of RF paths)*/ |
| 1106 | |
| 1107 | (*delay)=CurrentCmd->msDelay; |
| 1108 | (*step)++; |
| 1109 | return false; |
| 1110 | } |
| 1111 | |
| 1112 | void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
| 1113 | { |
| 1114 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1115 | u32 delay = 0; |
| 1116 | |
| 1117 | while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) |
| 1118 | { |
| 1119 | if (delay>0) |
| 1120 | msleep(delay); |
| 1121 | if (IS_NIC_DOWN(priv)) |
| 1122 | break; |
| 1123 | } |
| 1124 | } |
| 1125 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) |
| 1126 | { |
| 1127 | |
| 1128 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1129 | |
| 1130 | RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); |
| 1131 | |
| 1132 | RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv); |
| 1133 | |
| 1134 | rtl8192_phy_FinishSwChnlNow(dev , priv->chan); |
| 1135 | |
| 1136 | RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); |
| 1137 | } |
| 1138 | |
| 1139 | u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) |
| 1140 | { |
| 1141 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1142 | RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); |
| 1143 | if (IS_NIC_DOWN(priv)) |
| 1144 | { |
| 1145 | RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n",__func__); |
| 1146 | return false; |
| 1147 | } |
| 1148 | if (priv->SwChnlInProgress) |
| 1149 | return false; |
| 1150 | |
| 1151 | |
| 1152 | switch (priv->rtllib->mode) |
| 1153 | { |
| 1154 | case WIRELESS_MODE_A: |
| 1155 | case WIRELESS_MODE_N_5G: |
| 1156 | if (channel<=14){ |
| 1157 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); |
| 1158 | return false; |
| 1159 | } |
| 1160 | break; |
| 1161 | case WIRELESS_MODE_B: |
| 1162 | if (channel>14){ |
| 1163 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); |
| 1164 | return false; |
| 1165 | } |
| 1166 | break; |
| 1167 | case WIRELESS_MODE_G: |
| 1168 | case WIRELESS_MODE_N_24G: |
| 1169 | if (channel>14){ |
| 1170 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); |
| 1171 | return false; |
| 1172 | } |
| 1173 | break; |
| 1174 | } |
| 1175 | |
| 1176 | priv->SwChnlInProgress = true; |
| 1177 | if (channel == 0) |
| 1178 | channel = 1; |
| 1179 | |
| 1180 | priv->chan=channel; |
| 1181 | |
| 1182 | priv->SwChnlStage=0; |
| 1183 | priv->SwChnlStep=0; |
| 1184 | |
| 1185 | if (!IS_NIC_DOWN(priv)){ |
| 1186 | rtl8192_SwChnl_WorkItem(dev); |
| 1187 | } |
| 1188 | priv->SwChnlInProgress = false; |
| 1189 | return true; |
| 1190 | } |
| 1191 | |
| 1192 | static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) |
| 1193 | { |
| 1194 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1195 | |
| 1196 | switch (priv->CurrentChannelBW) |
| 1197 | { |
| 1198 | case HT_CHANNEL_WIDTH_20: |
| 1199 | priv->CCKPresentAttentuation = |
| 1200 | priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; |
| 1201 | |
| 1202 | if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) |
| 1203 | priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; |
| 1204 | if (priv->CCKPresentAttentuation < 0) |
| 1205 | priv->CCKPresentAttentuation = 0; |
| 1206 | |
| 1207 | RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); |
| 1208 | |
| 1209 | if (priv->rtllib->current_network.channel== 14 && !priv->bcck_in_ch14) |
| 1210 | { |
| 1211 | priv->bcck_in_ch14 = true; |
| 1212 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1213 | } |
| 1214 | else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) |
| 1215 | { |
| 1216 | priv->bcck_in_ch14 = false; |
| 1217 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1218 | } |
| 1219 | else |
| 1220 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1221 | break; |
| 1222 | |
| 1223 | case HT_CHANNEL_WIDTH_20_40: |
| 1224 | priv->CCKPresentAttentuation = |
| 1225 | priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; |
| 1226 | |
| 1227 | RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); |
| 1228 | if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) |
| 1229 | priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; |
| 1230 | if (priv->CCKPresentAttentuation < 0) |
| 1231 | priv->CCKPresentAttentuation = 0; |
| 1232 | |
| 1233 | if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) |
| 1234 | { |
| 1235 | priv->bcck_in_ch14 = true; |
| 1236 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1237 | } |
| 1238 | else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) |
| 1239 | { |
| 1240 | priv->bcck_in_ch14 = false; |
| 1241 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1242 | } |
| 1243 | else |
| 1244 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
| 1245 | break; |
| 1246 | } |
| 1247 | } |
| 1248 | |
| 1249 | #ifndef RTL8190P |
| 1250 | static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) |
| 1251 | { |
| 1252 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1253 | |
| 1254 | if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) |
| 1255 | priv->bcck_in_ch14 = true; |
| 1256 | else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) |
| 1257 | priv->bcck_in_ch14 = false; |
| 1258 | |
| 1259 | switch (priv->CurrentChannelBW) |
| 1260 | { |
| 1261 | case HT_CHANNEL_WIDTH_20: |
| 1262 | if (priv->Record_CCK_20Mindex == 0) |
| 1263 | priv->Record_CCK_20Mindex = 6; |
| 1264 | priv->CCK_index = priv->Record_CCK_20Mindex; |
| 1265 | RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index); |
| 1266 | break; |
| 1267 | |
| 1268 | case HT_CHANNEL_WIDTH_20_40: |
| 1269 | priv->CCK_index = priv->Record_CCK_40Mindex; |
| 1270 | RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); |
| 1271 | break; |
| 1272 | } |
| 1273 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1274 | } |
| 1275 | #endif |
| 1276 | |
| 1277 | static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) |
| 1278 | { |
| 1279 | #ifdef RTL8192E |
| 1280 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1281 | #endif |
| 1282 | |
| 1283 | #ifdef RTL8190P |
| 1284 | CCK_Tx_Power_Track_BW_Switch_TSSI(dev); |
| 1285 | #else |
| 1286 | if (priv->IC_Cut >= IC_VersionCut_D) |
| 1287 | CCK_Tx_Power_Track_BW_Switch_TSSI(dev); |
| 1288 | else |
| 1289 | CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); |
| 1290 | #endif |
| 1291 | } |
| 1292 | |
| 1293 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) |
| 1294 | { |
| 1295 | |
| 1296 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1297 | u8 regBwOpMode; |
| 1298 | |
| 1299 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ |
| 1300 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") |
| 1301 | |
| 1302 | |
| 1303 | if (priv->rf_chip== RF_PSEUDO_11N) |
| 1304 | { |
| 1305 | priv->SetBWModeInProgress= false; |
| 1306 | return; |
| 1307 | } |
| 1308 | if (IS_NIC_DOWN(priv)){ |
| 1309 | RT_TRACE(COMP_ERR,"%s(): ERR!! driver is not up\n",__func__); |
| 1310 | return; |
| 1311 | } |
| 1312 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); |
| 1313 | |
| 1314 | switch (priv->CurrentChannelBW) |
| 1315 | { |
| 1316 | case HT_CHANNEL_WIDTH_20: |
| 1317 | regBwOpMode |= BW_OPMODE_20MHZ; |
| 1318 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1319 | break; |
| 1320 | |
| 1321 | case HT_CHANNEL_WIDTH_20_40: |
| 1322 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
| 1323 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1324 | break; |
| 1325 | |
| 1326 | default: |
| 1327 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); |
| 1328 | break; |
| 1329 | } |
| 1330 | |
| 1331 | switch (priv->CurrentChannelBW) |
| 1332 | { |
| 1333 | case HT_CHANNEL_WIDTH_20: |
| 1334 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 1335 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
| 1336 | |
| 1337 | if (!priv->btxpower_tracking) |
| 1338 | { |
| 1339 | write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); |
| 1340 | write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); |
| 1341 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); |
| 1342 | } |
| 1343 | else |
| 1344 | CCK_Tx_Power_Track_BW_Switch(dev); |
| 1345 | |
| 1346 | #ifdef RTL8190P |
| 1347 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); |
| 1348 | rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); |
| 1349 | #else |
| 1350 | #ifdef RTL8192E |
| 1351 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); |
| 1352 | #endif |
| 1353 | #endif |
| 1354 | |
| 1355 | break; |
| 1356 | case HT_CHANNEL_WIDTH_20_40: |
| 1357 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 1358 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
| 1359 | |
| 1360 | if (!priv->btxpower_tracking) |
| 1361 | { |
| 1362 | write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); |
| 1363 | write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); |
| 1364 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); |
| 1365 | } |
| 1366 | else |
| 1367 | CCK_Tx_Power_Track_BW_Switch(dev); |
| 1368 | |
| 1369 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
| 1370 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); |
| 1371 | |
| 1372 | |
| 1373 | #ifdef RTL8190P |
| 1374 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); |
| 1375 | rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); |
| 1376 | |
| 1377 | if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) |
| 1378 | { |
| 1379 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01); |
| 1380 | }else if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) |
| 1381 | { |
| 1382 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02); |
| 1383 | } |
| 1384 | |
| 1385 | #else |
| 1386 | #ifdef RTL8192E |
| 1387 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); |
| 1388 | #endif |
| 1389 | #endif |
| 1390 | break; |
| 1391 | default: |
| 1392 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); |
| 1393 | break; |
| 1394 | |
| 1395 | } |
| 1396 | |
| 1397 | #if 1 |
| 1398 | switch ( priv->rf_chip ) |
| 1399 | { |
| 1400 | case RF_8225: |
| 1401 | #ifdef TO_DO_LIST |
| 1402 | PHY_SetRF8225Bandwidth(dev, pHalData->CurrentChannelBW); |
| 1403 | #endif |
| 1404 | break; |
| 1405 | |
| 1406 | case RF_8256: |
| 1407 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 1408 | break; |
| 1409 | |
| 1410 | case RF_8258: |
| 1411 | break; |
| 1412 | |
| 1413 | case RF_PSEUDO_11N: |
| 1414 | break; |
| 1415 | |
| 1416 | default: |
| 1417 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1418 | break; |
| 1419 | } |
| 1420 | #endif |
| 1421 | atomic_dec(&(priv->rtllib->atm_swbw)); |
| 1422 | priv->SetBWModeInProgress= false; |
| 1423 | |
| 1424 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); |
| 1425 | } |
| 1426 | |
| 1427 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) |
| 1428 | { |
| 1429 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1430 | |
| 1431 | |
| 1432 | if (priv->SetBWModeInProgress) |
| 1433 | return; |
| 1434 | |
| 1435 | atomic_inc(&(priv->rtllib->atm_swbw)); |
| 1436 | priv->SetBWModeInProgress= true; |
| 1437 | |
| 1438 | priv->CurrentChannelBW = Bandwidth; |
| 1439 | |
| 1440 | if (Offset==HT_EXTCHNL_OFFSET_LOWER) |
| 1441 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
| 1442 | else if (Offset==HT_EXTCHNL_OFFSET_UPPER) |
| 1443 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
| 1444 | else |
| 1445 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; |
| 1446 | |
| 1447 | rtl8192_SetBWModeWorkItem(dev); |
| 1448 | |
| 1449 | } |
| 1450 | |
| 1451 | |
| 1452 | void InitialGain819xPci(struct net_device *dev, u8 Operation) |
| 1453 | { |
| 1454 | #define SCAN_RX_INITIAL_GAIN 0x17 |
| 1455 | #define POWER_DETECTION_TH 0x08 |
| 1456 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1457 | u32 BitMask; |
| 1458 | u8 initial_gain; |
| 1459 | |
| 1460 | if (!IS_NIC_DOWN(priv)){ |
| 1461 | switch (Operation) |
| 1462 | { |
| 1463 | case IG_Backup: |
| 1464 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); |
| 1465 | initial_gain = SCAN_RX_INITIAL_GAIN; |
| 1466 | BitMask = bMaskByte0; |
| 1467 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1468 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); |
| 1469 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); |
| 1470 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); |
| 1471 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); |
| 1472 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); |
| 1473 | BitMask = bMaskByte2; |
| 1474 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); |
| 1475 | |
| 1476 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 1477 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 1478 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 1479 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 1480 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); |
| 1481 | |
| 1482 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); |
| 1483 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); |
| 1484 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); |
| 1485 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); |
| 1486 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); |
| 1487 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); |
| 1488 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); |
| 1489 | break; |
| 1490 | case IG_Restore: |
| 1491 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); |
| 1492 | BitMask = 0x7f; |
| 1493 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1494 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); |
| 1495 | |
| 1496 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); |
| 1497 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); |
| 1498 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); |
| 1499 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); |
| 1500 | BitMask = bMaskByte2; |
| 1501 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); |
| 1502 | |
| 1503 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 1504 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 1505 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 1506 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 1507 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); |
| 1508 | |
| 1509 | rtl8192_phy_setTxPower(dev,priv->rtllib->current_network.channel); |
| 1510 | |
| 1511 | |
| 1512 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1513 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); |
| 1514 | break; |
| 1515 | default: |
| 1516 | RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); |
| 1517 | break; |
| 1518 | } |
| 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | #if defined RTL8190P |
| 1523 | extern void |
| 1524 | PHY_SetRtl8190pRfOff(struct net_device* dev ) |
| 1525 | { |
| 1526 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1527 | |
| 1528 | if (priv->rf_type == RF_2T4R) |
| 1529 | { |
| 1530 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); |
| 1531 | } |
| 1532 | rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0); |
| 1533 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
| 1534 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0); |
| 1535 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); |
| 1536 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); |
| 1537 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0); |
| 1538 | |
| 1539 | } |
| 1540 | #endif |
| 1541 | |
| 1542 | #if defined RTL8192E |
| 1543 | extern void |
| 1544 | PHY_SetRtl8192eRfOff(struct net_device* dev ) |
| 1545 | { |
| 1546 | |
| 1547 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); |
| 1548 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); |
| 1549 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); |
| 1550 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); |
| 1551 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); |
| 1552 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); |
| 1553 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); |
| 1554 | write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); |
| 1555 | |
| 1556 | } |
| 1557 | #endif |
| 1558 | |
| 1559 | #ifndef RTL8192SE |
| 1560 | bool |
| 1561 | SetRFPowerState8190( |
| 1562 | struct net_device* dev, |
| 1563 | RT_RF_POWER_STATE eRFPowerState |
| 1564 | ) |
| 1565 | { |
| 1566 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1567 | #if defined RTL8192E |
| 1568 | PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl)); |
| 1569 | #endif |
| 1570 | bool bResult = true; |
| 1571 | u8 i = 0, QueueID = 0; |
| 1572 | struct rtl8192_tx_ring *ring = NULL; |
| 1573 | |
| 1574 | if (priv->SetRFPowerStateInProgress == true) |
| 1575 | return false; |
| 1576 | RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); |
| 1577 | priv->SetRFPowerStateInProgress = true; |
| 1578 | |
| 1579 | switch (priv->rf_chip) |
| 1580 | { |
| 1581 | case RF_8256: |
| 1582 | switch ( eRFPowerState ) |
| 1583 | { |
| 1584 | case eRfOn: |
| 1585 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n"); |
| 1586 | #ifdef RTL8190P |
| 1587 | if (priv->rf_type == RF_2T4R) |
| 1588 | { |
| 1589 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); |
| 1590 | rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); |
| 1591 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf); |
| 1592 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); |
| 1593 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf); |
| 1594 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf); |
| 1595 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); |
| 1596 | } |
| 1597 | else if (priv->rf_type == RF_1T2R) |
| 1598 | { |
| 1599 | rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); |
| 1600 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3); |
| 1601 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); |
| 1602 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3); |
| 1603 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3); |
| 1604 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); |
| 1605 | } |
| 1606 | else if (priv->rf_type == RF_1T1R) |
| 1607 | { |
| 1608 | rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); |
| 1609 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1); |
| 1610 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); |
| 1611 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1); |
| 1612 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1); |
| 1613 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); |
| 1614 | } |
| 1615 | |
| 1616 | #elif defined RTL8192E |
| 1617 | if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) |
| 1618 | { |
| 1619 | bool rtstatus = true; |
| 1620 | u32 InitilizeCount = 3; |
| 1621 | do |
| 1622 | { |
| 1623 | InitilizeCount--; |
| 1624 | priv->RegRfOff = false; |
| 1625 | rtstatus = NicIFEnableNIC(dev); |
| 1626 | }while( (rtstatus != true) &&(InitilizeCount >0) ); |
| 1627 | |
| 1628 | if (rtstatus != true) |
| 1629 | { |
| 1630 | RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__func__); |
| 1631 | priv->SetRFPowerStateInProgress = false; |
| 1632 | return false; |
| 1633 | } |
| 1634 | |
| 1635 | RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); |
| 1636 | } else { |
| 1637 | write_nic_byte(dev, ANAPAR, 0x37); |
| 1638 | mdelay(1); |
| 1639 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); |
| 1640 | priv->bHwRfOffAction = 0; |
| 1641 | |
| 1642 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); |
| 1643 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
| 1644 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); |
| 1645 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); |
| 1646 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); |
| 1647 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); |
| 1648 | |
| 1649 | } |
| 1650 | |
| 1651 | #endif |
| 1652 | break; |
| 1653 | |
| 1654 | case eRfSleep: |
| 1655 | { |
| 1656 | if (priv->rtllib->eRFPowerState == eRfOff) |
| 1657 | break; |
| 1658 | |
| 1659 | |
| 1660 | { |
| 1661 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) |
| 1662 | { |
| 1663 | ring = &priv->tx_ring[QueueID]; |
| 1664 | |
| 1665 | if (skb_queue_len(&ring->queue) == 0) { |
| 1666 | QueueID++; |
| 1667 | continue; |
| 1668 | } |
| 1669 | #ifdef TO_DO_LIST |
| 1670 | else if (IsLowPowerState(Adapter)) |
| 1671 | { |
| 1672 | RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID); |
| 1673 | break; |
| 1674 | } |
| 1675 | #endif |
| 1676 | else |
| 1677 | { |
| 1678 | RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); |
| 1679 | udelay(10); |
| 1680 | i++; |
| 1681 | } |
| 1682 | |
| 1683 | if (i >= MAX_DOZE_WAITING_TIMES_9x) |
| 1684 | { |
| 1685 | RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); |
| 1686 | break; |
| 1687 | } |
| 1688 | } |
| 1689 | } |
| 1690 | |
| 1691 | #ifdef RTL8190P |
| 1692 | { |
| 1693 | PHY_SetRtl8190pRfOff(dev); |
| 1694 | } |
| 1695 | #elif defined RTL8192E |
| 1696 | { |
| 1697 | PHY_SetRtl8192eRfOff(dev); |
| 1698 | } |
| 1699 | #endif |
| 1700 | } |
| 1701 | break; |
| 1702 | |
| 1703 | case eRfOff: |
| 1704 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n"); |
| 1705 | |
| 1706 | |
| 1707 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { |
| 1708 | ring = &priv->tx_ring[QueueID]; |
| 1709 | |
| 1710 | if (skb_queue_len(&ring->queue) == 0) { |
| 1711 | QueueID++; |
| 1712 | continue; |
| 1713 | } |
| 1714 | #ifdef TO_DO_LIST |
| 1715 | else if (IsLowPowerState(Adapter)) |
| 1716 | { |
| 1717 | RT_TRACE(COMP_POWER, |
| 1718 | "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID); |
| 1719 | break; |
| 1720 | } |
| 1721 | #endif |
| 1722 | else |
| 1723 | { |
| 1724 | RT_TRACE(COMP_POWER, |
| 1725 | "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); |
| 1726 | udelay(10); |
| 1727 | i++; |
| 1728 | } |
| 1729 | |
| 1730 | if (i >= MAX_DOZE_WAITING_TIMES_9x) |
| 1731 | { |
| 1732 | RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); |
| 1733 | break; |
| 1734 | } |
| 1735 | } |
| 1736 | |
| 1737 | #if defined RTL8190P |
| 1738 | { |
| 1739 | PHY_SetRtl8190pRfOff(dev); |
| 1740 | } |
| 1741 | #elif defined RTL8192E |
| 1742 | { |
| 1743 | if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) |
| 1744 | { |
| 1745 | |
| 1746 | NicIFDisableNIC(dev); |
| 1747 | RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); |
| 1748 | } |
| 1749 | else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) |
| 1750 | { |
| 1751 | PHY_SetRtl8192eRfOff(dev); |
| 1752 | } |
| 1753 | #ifdef TO_DO_LIST |
| 1754 | if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS ) |
| 1755 | { |
| 1756 | Adapter->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK); |
| 1757 | } |
| 1758 | else |
| 1759 | { |
| 1760 | Adapter->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF); |
| 1761 | } |
| 1762 | #endif |
| 1763 | } |
| 1764 | #else |
| 1765 | else |
| 1766 | { |
| 1767 | RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n")); |
| 1768 | } |
| 1769 | #endif |
| 1770 | |
| 1771 | break; |
| 1772 | |
| 1773 | default: |
| 1774 | bResult = false; |
| 1775 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); |
| 1776 | break; |
| 1777 | } |
| 1778 | |
| 1779 | break; |
| 1780 | |
| 1781 | default: |
| 1782 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); |
| 1783 | break; |
| 1784 | } |
| 1785 | |
| 1786 | if (bResult) { |
| 1787 | priv->rtllib->eRFPowerState = eRFPowerState; |
| 1788 | |
| 1789 | switch (priv->rf_chip ) |
| 1790 | { |
| 1791 | case RF_8256: |
| 1792 | switch (priv->rtllib->eRFPowerState) |
| 1793 | { |
| 1794 | case eRfOff: |
| 1795 | if (priv->rtllib->RfOffReason==RF_CHANGE_BY_IPS ) { |
| 1796 | #ifdef TO_DO |
| 1797 | dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK); |
| 1798 | #endif |
| 1799 | } else { |
| 1800 | #ifdef TO_DO |
| 1801 | dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF); |
| 1802 | #endif |
| 1803 | } |
| 1804 | break; |
| 1805 | |
| 1806 | case eRfOn: |
| 1807 | if ( priv->rtllib->state == RTLLIB_LINKED) { |
| 1808 | #ifdef TO_DO |
| 1809 | dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK); |
| 1810 | #endif |
| 1811 | } else { |
| 1812 | #ifdef TO_DO |
| 1813 | dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK); |
| 1814 | #endif |
| 1815 | } |
| 1816 | break; |
| 1817 | |
| 1818 | default: |
| 1819 | break; |
| 1820 | } |
| 1821 | |
| 1822 | break; |
| 1823 | |
| 1824 | default: |
| 1825 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); |
| 1826 | break; |
| 1827 | } |
| 1828 | } |
| 1829 | |
| 1830 | priv->SetRFPowerStateInProgress = false; |
| 1831 | RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); |
| 1832 | return bResult; |
| 1833 | } |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | bool |
| 1838 | SetRFPowerState( |
| 1839 | struct net_device* dev, |
| 1840 | RT_RF_POWER_STATE eRFPowerState |
| 1841 | ) |
| 1842 | { |
| 1843 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1844 | |
| 1845 | bool bResult = false; |
| 1846 | |
| 1847 | RT_TRACE(COMP_PS,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); |
| 1848 | if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) { |
| 1849 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); |
| 1850 | return bResult; |
| 1851 | } |
| 1852 | |
| 1853 | bResult = SetRFPowerState8190(dev, eRFPowerState); |
| 1854 | |
| 1855 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", bResult); |
| 1856 | |
| 1857 | return bResult; |
| 1858 | } |
| 1859 | #endif |
| 1860 | |
| 1861 | extern void |
| 1862 | PHY_ScanOperationBackup8192( |
| 1863 | struct net_device* dev, |
| 1864 | u8 Operation |
| 1865 | ) |
| 1866 | { |
| 1867 | struct r8192_priv *priv = rtllib_priv(dev); |
| 1868 | |
| 1869 | if (priv->up) { |
| 1870 | switch (Operation) { |
| 1871 | case SCAN_OPT_BACKUP: |
| 1872 | priv->rtllib->InitialGainHandler(dev,IG_Backup); |
| 1873 | break; |
| 1874 | |
| 1875 | case SCAN_OPT_RESTORE: |
| 1876 | priv->rtllib->InitialGainHandler(dev,IG_Restore); |
| 1877 | break; |
| 1878 | |
| 1879 | default: |
| 1880 | RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n"); |
| 1881 | break; |
| 1882 | } |
| 1883 | } |
| 1884 | |
| 1885 | } |
| 1886 | |
| 1887 | #endif |