Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * sata_sil.c - Silicon Image SATA |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2003-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * Copyright 2003 Benjamin Herrenschmidt |
| 10 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2, or (at your option) |
| 15 | * any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; see the file COPYING. If not, write to |
| 24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
| 26 | * |
| 27 | * libata documentation is available via 'make {ps|pdf}docs', |
| 28 | * as Documentation/DocBook/libata.* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | * |
Jeff Garzik | 953d113 | 2005-08-26 19:46:24 -0400 | [diff] [blame] | 30 | * Documentation for SiI 3112: |
| 31 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 |
| 32 | * |
| 33 | * Other errata and documentation available under NDA. |
| 34 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | */ |
| 36 | |
| 37 | #include <linux/kernel.h> |
| 38 | #include <linux/module.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/init.h> |
| 41 | #include <linux/blkdev.h> |
| 42 | #include <linux/delay.h> |
| 43 | #include <linux/interrupt.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 44 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
| 46 | #include <linux/libata.h> |
| 47 | |
| 48 | #define DRV_NAME "sata_sil" |
Jeff Garzik | af64371 | 2006-04-02 20:41:36 -0400 | [diff] [blame] | 49 | #define DRV_VERSION "1.0" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | enum { |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 52 | /* |
| 53 | * host flags |
| 54 | */ |
Tejun Heo | e4e10e3 | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 55 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
Tejun Heo | e4deec6 | 2005-08-23 07:27:25 +0900 | [diff] [blame] | 56 | SIL_FLAG_MOD15WRITE = (1 << 30), |
Tejun Heo | 20888d8 | 2006-05-31 18:27:53 +0900 | [diff] [blame] | 57 | |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 58 | SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 59 | ATA_FLAG_MMIO, |
Tejun Heo | e4deec6 | 2005-08-23 07:27:25 +0900 | [diff] [blame] | 60 | |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 61 | /* |
| 62 | * Controller IDs |
| 63 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | sil_3112 = 0, |
Tejun Heo | 81c2af3 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 65 | sil_3512 = 1, |
| 66 | sil_3114 = 2, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 68 | /* |
| 69 | * Register offsets |
| 70 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | SIL_SYSCFG = 0x48, |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Register bits |
| 75 | */ |
| 76 | /* SYSCFG */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | SIL_MASK_IDE0_INT = (1 << 22), |
| 78 | SIL_MASK_IDE1_INT = (1 << 23), |
| 79 | SIL_MASK_IDE2_INT = (1 << 24), |
| 80 | SIL_MASK_IDE3_INT = (1 << 25), |
| 81 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, |
| 82 | SIL_MASK_4PORT = SIL_MASK_2PORT | |
| 83 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, |
| 84 | |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 85 | /* BMDMA/BMDMA2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | SIL_INTR_STEERING = (1 << 1), |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 87 | |
Tejun Heo | 20888d8 | 2006-05-31 18:27:53 +0900 | [diff] [blame] | 88 | SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
| 89 | SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ |
| 90 | SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ |
| 91 | SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ |
| 92 | SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ |
| 93 | SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ |
| 94 | SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ |
| 95 | SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ |
| 96 | SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ |
| 97 | SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ |
| 98 | |
| 99 | /* SIEN */ |
| 100 | SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ |
| 101 | |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 102 | /* |
| 103 | * Others |
| 104 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
| 106 | SIL_QUIRK_UDMA5MAX = (1 << 1), |
| 107 | }; |
| 108 | |
| 109 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
| 110 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); |
| 111 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 112 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 113 | static void sil_post_set_mode (struct ata_port *ap); |
Tejun Heo | cbe88fb | 2006-05-31 18:27:55 +0900 | [diff] [blame^] | 114 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, |
| 115 | struct pt_regs *regs); |
Tejun Heo | f6aae27 | 2006-05-15 20:58:27 +0900 | [diff] [blame] | 116 | static void sil_freeze(struct ata_port *ap); |
| 117 | static void sil_thaw(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 119 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 120 | static const struct pci_device_id sil_pci_tbl[] = { |
Tejun Heo | 81c2af3 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 121 | { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
| 122 | { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
Tejun Heo | 0ee304d | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 123 | { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 }, |
Tejun Heo | 81c2af3 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 125 | { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
| 126 | { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
| 127 | { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | { } /* terminate list */ |
| 129 | }; |
| 130 | |
| 131 | |
| 132 | /* TODO firmware versions should be added - eric */ |
| 133 | static const struct sil_drivelist { |
| 134 | const char * product; |
| 135 | unsigned int quirk; |
| 136 | } sil_blacklist [] = { |
| 137 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, |
| 138 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, |
| 139 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, |
| 140 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, |
| 141 | { "ST380013AS", SIL_QUIRK_MOD15WRITE }, |
| 142 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, |
| 143 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, |
| 144 | { "ST3160023AS", SIL_QUIRK_MOD15WRITE }, |
| 145 | { "ST3120026AS", SIL_QUIRK_MOD15WRITE }, |
| 146 | { "ST3200822AS", SIL_QUIRK_MOD15WRITE }, |
| 147 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, |
| 148 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, |
| 149 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, |
| 150 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, |
| 151 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, |
| 152 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, |
| 153 | { } |
| 154 | }; |
| 155 | |
| 156 | static struct pci_driver sil_pci_driver = { |
| 157 | .name = DRV_NAME, |
| 158 | .id_table = sil_pci_tbl, |
| 159 | .probe = sil_init_one, |
| 160 | .remove = ata_pci_remove_one, |
| 161 | }; |
| 162 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 163 | static struct scsi_host_template sil_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | .module = THIS_MODULE, |
| 165 | .name = DRV_NAME, |
| 166 | .ioctl = ata_scsi_ioctl, |
| 167 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | .can_queue = ATA_DEF_QUEUE, |
| 169 | .this_id = ATA_SHT_THIS_ID, |
| 170 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 172 | .emulated = ATA_SHT_EMULATED, |
| 173 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 174 | .proc_name = DRV_NAME, |
| 175 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 176 | .slave_configure = ata_scsi_slave_config, |
| 177 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | }; |
| 179 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 180 | static const struct ata_port_operations sil_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | .port_disable = ata_port_disable, |
| 182 | .dev_config = sil_dev_config, |
| 183 | .tf_load = ata_tf_load, |
| 184 | .tf_read = ata_tf_read, |
| 185 | .check_status = ata_check_status, |
| 186 | .exec_command = ata_exec_command, |
| 187 | .dev_select = ata_std_dev_select, |
Tejun Heo | 531db7a | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 188 | .probe_reset = ata_std_probe_reset, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | .post_set_mode = sil_post_set_mode, |
| 190 | .bmdma_setup = ata_bmdma_setup, |
| 191 | .bmdma_start = ata_bmdma_start, |
| 192 | .bmdma_stop = ata_bmdma_stop, |
| 193 | .bmdma_status = ata_bmdma_status, |
| 194 | .qc_prep = ata_qc_prep, |
| 195 | .qc_issue = ata_qc_issue_prot, |
Alan Cox | a6b2c5d | 2006-05-22 16:59:59 +0100 | [diff] [blame] | 196 | .data_xfer = ata_mmio_data_xfer, |
Tejun Heo | f6aae27 | 2006-05-15 20:58:27 +0900 | [diff] [blame] | 197 | .freeze = sil_freeze, |
| 198 | .thaw = sil_thaw, |
| 199 | .error_handler = ata_bmdma_error_handler, |
| 200 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Tejun Heo | cbe88fb | 2006-05-31 18:27:55 +0900 | [diff] [blame^] | 201 | .irq_handler = sil_interrupt, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | .irq_clear = ata_bmdma_irq_clear, |
| 203 | .scr_read = sil_scr_read, |
| 204 | .scr_write = sil_scr_write, |
| 205 | .port_start = ata_port_start, |
| 206 | .port_stop = ata_port_stop, |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 207 | .host_stop = ata_pci_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | }; |
| 209 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 210 | static const struct ata_port_info sil_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | /* sil_3112 */ |
| 212 | { |
| 213 | .sht = &sil_sht, |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 214 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE, |
Tejun Heo | e4deec6 | 2005-08-23 07:27:25 +0900 | [diff] [blame] | 215 | .pio_mask = 0x1f, /* pio0-4 */ |
| 216 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 217 | .udma_mask = 0x3f, /* udma0-5 */ |
| 218 | .port_ops = &sil_ops, |
Tejun Heo | 0ee304d | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 219 | }, |
| 220 | /* sil_3512 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | { |
| 222 | .sht = &sil_sht, |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 223 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
Tejun Heo | 0ee304d | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 224 | .pio_mask = 0x1f, /* pio0-4 */ |
| 225 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 226 | .udma_mask = 0x3f, /* udma0-5 */ |
| 227 | .port_ops = &sil_ops, |
| 228 | }, |
| 229 | /* sil_3114 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | { |
| 231 | .sht = &sil_sht, |
Tejun Heo | e653a1e | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 232 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | .pio_mask = 0x1f, /* pio0-4 */ |
| 234 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 235 | .udma_mask = 0x3f, /* udma0-5 */ |
| 236 | .port_ops = &sil_ops, |
| 237 | }, |
| 238 | }; |
| 239 | |
| 240 | /* per-port register offsets */ |
| 241 | /* TODO: we can probably calculate rather than use a table */ |
| 242 | static const struct { |
| 243 | unsigned long tf; /* ATA taskfile register block */ |
| 244 | unsigned long ctl; /* ATA control/altstatus register block */ |
| 245 | unsigned long bmdma; /* DMA register block */ |
Tejun Heo | 20888d8 | 2006-05-31 18:27:53 +0900 | [diff] [blame] | 246 | unsigned long bmdma2; /* DMA register block #2 */ |
Tejun Heo | 48d4ef2 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 247 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | unsigned long scr; /* SATA control register block */ |
| 249 | unsigned long sien; /* SATA Interrupt Enable register */ |
| 250 | unsigned long xfer_mode;/* data transfer mode register */ |
Tejun Heo | e4e10e3 | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 251 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | } sil_port[] = { |
| 253 | /* port 0 ... */ |
Tejun Heo | 20888d8 | 2006-05-31 18:27:53 +0900 | [diff] [blame] | 254 | { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, |
| 255 | { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, |
| 256 | { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, |
| 257 | { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | /* ... port 3 */ |
| 259 | }; |
| 260 | |
| 261 | MODULE_AUTHOR("Jeff Garzik"); |
| 262 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); |
| 263 | MODULE_LICENSE("GPL"); |
| 264 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); |
| 265 | MODULE_VERSION(DRV_VERSION); |
| 266 | |
Jeff Garzik | 51e9f2f | 2006-01-27 16:50:27 -0500 | [diff] [blame] | 267 | static int slow_down = 0; |
| 268 | module_param(slow_down, int, 0444); |
| 269 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); |
| 270 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
| 273 | { |
| 274 | u8 cache_line = 0; |
| 275 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); |
| 276 | return cache_line; |
| 277 | } |
| 278 | |
| 279 | static void sil_post_set_mode (struct ata_port *ap) |
| 280 | { |
| 281 | struct ata_host_set *host_set = ap->host_set; |
| 282 | struct ata_device *dev; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 283 | void __iomem *addr = |
| 284 | host_set->mmio_base + sil_port[ap->port_no].xfer_mode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | u32 tmp, dev_mode[2]; |
| 286 | unsigned int i; |
| 287 | |
| 288 | for (i = 0; i < 2; i++) { |
| 289 | dev = &ap->device[i]; |
Tejun Heo | e1211e3 | 2006-04-01 01:38:18 +0900 | [diff] [blame] | 290 | if (!ata_dev_enabled(dev)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | dev_mode[i] = 0; /* PIO0/1/2 */ |
| 292 | else if (dev->flags & ATA_DFLAG_PIO) |
| 293 | dev_mode[i] = 1; /* PIO3/4 */ |
| 294 | else |
| 295 | dev_mode[i] = 3; /* UDMA */ |
| 296 | /* value 2 indicates MDMA */ |
| 297 | } |
| 298 | |
| 299 | tmp = readl(addr); |
| 300 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); |
| 301 | tmp |= dev_mode[0]; |
| 302 | tmp |= (dev_mode[1] << 4); |
| 303 | writel(tmp, addr); |
| 304 | readl(addr); /* flush */ |
| 305 | } |
| 306 | |
| 307 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) |
| 308 | { |
| 309 | unsigned long offset = ap->ioaddr.scr_addr; |
| 310 | |
| 311 | switch (sc_reg) { |
| 312 | case SCR_STATUS: |
| 313 | return offset + 4; |
| 314 | case SCR_ERROR: |
| 315 | return offset + 8; |
| 316 | case SCR_CONTROL: |
| 317 | return offset; |
| 318 | default: |
| 319 | /* do nothing */ |
| 320 | break; |
| 321 | } |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) |
| 327 | { |
Al Viro | 9aa36e8 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 328 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | if (mmio) |
| 330 | return readl(mmio); |
| 331 | return 0xffffffffU; |
| 332 | } |
| 333 | |
| 334 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
| 335 | { |
Al Viro | 9aa36e8 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 336 | void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | if (mmio) |
| 338 | writel(val, mmio); |
| 339 | } |
| 340 | |
Tejun Heo | cbe88fb | 2006-05-31 18:27:55 +0900 | [diff] [blame^] | 341 | static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
| 342 | { |
| 343 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); |
| 344 | u8 status; |
| 345 | |
| 346 | if (unlikely(!qc || qc->tf.ctl & ATA_NIEN)) |
| 347 | goto freeze; |
| 348 | |
| 349 | /* Check whether we are expecting interrupt in this state */ |
| 350 | switch (ap->hsm_task_state) { |
| 351 | case HSM_ST_FIRST: |
| 352 | /* Some pre-ATAPI-4 devices assert INTRQ |
| 353 | * at this state when ready to receive CDB. |
| 354 | */ |
| 355 | |
| 356 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. |
| 357 | * The flag was turned on only for atapi devices. |
| 358 | * No need to check is_atapi_taskfile(&qc->tf) again. |
| 359 | */ |
| 360 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
| 361 | goto err_hsm; |
| 362 | break; |
| 363 | case HSM_ST_LAST: |
| 364 | if (qc->tf.protocol == ATA_PROT_DMA || |
| 365 | qc->tf.protocol == ATA_PROT_ATAPI_DMA) { |
| 366 | /* clear DMA-Start bit */ |
| 367 | ap->ops->bmdma_stop(qc); |
| 368 | |
| 369 | if (bmdma2 & SIL_DMA_ERROR) { |
| 370 | qc->err_mask |= AC_ERR_HOST_BUS; |
| 371 | ap->hsm_task_state = HSM_ST_ERR; |
| 372 | } |
| 373 | } |
| 374 | break; |
| 375 | case HSM_ST: |
| 376 | break; |
| 377 | default: |
| 378 | goto err_hsm; |
| 379 | } |
| 380 | |
| 381 | /* check main status, clearing INTRQ */ |
| 382 | status = ata_chk_status(ap); |
| 383 | if (unlikely(status & ATA_BUSY)) |
| 384 | goto err_hsm; |
| 385 | |
| 386 | /* ack bmdma irq events */ |
| 387 | ata_bmdma_irq_clear(ap); |
| 388 | |
| 389 | /* kick HSM in the ass */ |
| 390 | ata_hsm_move(ap, qc, status, 0); |
| 391 | |
| 392 | return; |
| 393 | |
| 394 | err_hsm: |
| 395 | qc->err_mask |= AC_ERR_HSM; |
| 396 | freeze: |
| 397 | ata_port_freeze(ap); |
| 398 | } |
| 399 | |
| 400 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, |
| 401 | struct pt_regs *regs) |
| 402 | { |
| 403 | struct ata_host_set *host_set = dev_instance; |
| 404 | void __iomem *mmio_base = host_set->mmio_base; |
| 405 | int handled = 0; |
| 406 | int i; |
| 407 | |
| 408 | spin_lock(&host_set->lock); |
| 409 | |
| 410 | for (i = 0; i < host_set->n_ports; i++) { |
| 411 | struct ata_port *ap = host_set->ports[i]; |
| 412 | u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); |
| 413 | |
| 414 | if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) |
| 415 | continue; |
| 416 | |
| 417 | if (!(bmdma2 & SIL_DMA_COMPLETE)) |
| 418 | continue; |
| 419 | |
| 420 | sil_host_intr(ap, bmdma2); |
| 421 | handled = 1; |
| 422 | } |
| 423 | |
| 424 | spin_unlock(&host_set->lock); |
| 425 | |
| 426 | return IRQ_RETVAL(handled); |
| 427 | } |
| 428 | |
Tejun Heo | f6aae27 | 2006-05-15 20:58:27 +0900 | [diff] [blame] | 429 | static void sil_freeze(struct ata_port *ap) |
| 430 | { |
| 431 | void __iomem *mmio_base = ap->host_set->mmio_base; |
| 432 | u32 tmp; |
| 433 | |
| 434 | /* plug IRQ */ |
| 435 | tmp = readl(mmio_base + SIL_SYSCFG); |
| 436 | tmp |= SIL_MASK_IDE0_INT << ap->port_no; |
| 437 | writel(tmp, mmio_base + SIL_SYSCFG); |
| 438 | readl(mmio_base + SIL_SYSCFG); /* flush */ |
| 439 | } |
| 440 | |
| 441 | static void sil_thaw(struct ata_port *ap) |
| 442 | { |
| 443 | void __iomem *mmio_base = ap->host_set->mmio_base; |
| 444 | u32 tmp; |
| 445 | |
| 446 | /* clear IRQ */ |
| 447 | ata_chk_status(ap); |
| 448 | ata_bmdma_irq_clear(ap); |
| 449 | |
| 450 | /* turn on IRQ */ |
| 451 | tmp = readl(mmio_base + SIL_SYSCFG); |
| 452 | tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); |
| 453 | writel(tmp, mmio_base + SIL_SYSCFG); |
| 454 | } |
| 455 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | /** |
| 457 | * sil_dev_config - Apply device/host-specific errata fixups |
| 458 | * @ap: Port containing device to be examined |
| 459 | * @dev: Device to be examined |
| 460 | * |
| 461 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a |
| 462 | * device is known to be present, this function is called. |
| 463 | * We apply two errata fixups which are specific to Silicon Image, |
| 464 | * a Seagate and a Maxtor fixup. |
| 465 | * |
| 466 | * For certain Seagate devices, we must limit the maximum sectors |
| 467 | * to under 8K. |
| 468 | * |
| 469 | * For certain Maxtor devices, we must not program the drive |
| 470 | * beyond udma5. |
| 471 | * |
| 472 | * Both fixups are unfairly pessimistic. As soon as I get more |
| 473 | * information on these errata, I will create a more exhaustive |
| 474 | * list, and apply the fixups to only the specific |
| 475 | * devices/hosts/firmwares that need it. |
| 476 | * |
| 477 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted |
| 478 | * The Maxtor quirk is in the blacklist, but I'm keeping the original |
| 479 | * pessimistic fix for the following reasons... |
| 480 | * - There seems to be less info on it, only one device gleaned off the |
| 481 | * Windows driver, maybe only one is affected. More info would be greatly |
| 482 | * appreciated. |
| 483 | * - But then again UDMA5 is hardly anything to complain about |
| 484 | */ |
| 485 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) |
| 486 | { |
| 487 | unsigned int n, quirks = 0; |
Tejun Heo | 2e02671 | 2006-02-12 22:47:04 +0900 | [diff] [blame] | 488 | unsigned char model_num[41]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | |
Tejun Heo | 6a62a04 | 2006-02-13 10:02:46 +0900 | [diff] [blame] | 490 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 492 | for (n = 0; sil_blacklist[n].product; n++) |
Tejun Heo | 2e02671 | 2006-02-12 22:47:04 +0900 | [diff] [blame] | 493 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | quirks = sil_blacklist[n].quirk; |
| 495 | break; |
| 496 | } |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 497 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | /* limit requests to 15 sectors */ |
Jeff Garzik | 51e9f2f | 2006-01-27 16:50:27 -0500 | [diff] [blame] | 499 | if (slow_down || |
| 500 | ((ap->flags & SIL_FLAG_MOD15WRITE) && |
| 501 | (quirks & SIL_QUIRK_MOD15WRITE))) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 502 | ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix " |
| 503 | "(mod15write workaround)\n"); |
Tejun Heo | b00eec1 | 2006-02-12 23:32:59 +0900 | [diff] [blame] | 504 | dev->max_sectors = 15; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | return; |
| 506 | } |
| 507 | |
| 508 | /* limit to udma5 */ |
| 509 | if (quirks & SIL_QUIRK_UDMA5MAX) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 510 | ata_dev_printk(dev, KERN_INFO, |
| 511 | "applying Maxtor errata fix %s\n", model_num); |
Tejun Heo | 5a52913 | 2006-03-24 14:07:50 +0900 | [diff] [blame] | 512 | dev->udma_mask &= ATA_UDMA5; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | return; |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 518 | { |
| 519 | static int printed_version; |
| 520 | struct ata_probe_ent *probe_ent = NULL; |
| 521 | unsigned long base; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 522 | void __iomem *mmio_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | int rc; |
| 524 | unsigned int i; |
| 525 | int pci_dev_busy = 0; |
Tejun Heo | f6aae27 | 2006-05-15 20:58:27 +0900 | [diff] [blame] | 526 | u32 tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | u8 cls; |
| 528 | |
| 529 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 530 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 532 | rc = pci_enable_device(pdev); |
| 533 | if (rc) |
| 534 | return rc; |
| 535 | |
| 536 | rc = pci_request_regions(pdev, DRV_NAME); |
| 537 | if (rc) { |
| 538 | pci_dev_busy = 1; |
| 539 | goto err_out; |
| 540 | } |
| 541 | |
| 542 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
| 543 | if (rc) |
| 544 | goto err_out_regions; |
| 545 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
| 546 | if (rc) |
| 547 | goto err_out_regions; |
| 548 | |
Tejun Heo | 9a53144 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 549 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | if (probe_ent == NULL) { |
| 551 | rc = -ENOMEM; |
| 552 | goto err_out_regions; |
| 553 | } |
| 554 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | INIT_LIST_HEAD(&probe_ent->node); |
| 556 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 557 | probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; |
| 558 | probe_ent->sht = sil_port_info[ent->driver_data].sht; |
| 559 | probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; |
| 560 | probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; |
| 561 | probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; |
| 562 | probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; |
| 563 | probe_ent->irq = pdev->irq; |
| 564 | probe_ent->irq_flags = SA_SHIRQ; |
| 565 | probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags; |
| 566 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 567 | mmio_base = pci_iomap(pdev, 5, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | if (mmio_base == NULL) { |
| 569 | rc = -ENOMEM; |
| 570 | goto err_out_free_ent; |
| 571 | } |
| 572 | |
| 573 | probe_ent->mmio_base = mmio_base; |
| 574 | |
| 575 | base = (unsigned long) mmio_base; |
| 576 | |
| 577 | for (i = 0; i < probe_ent->n_ports; i++) { |
| 578 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; |
| 579 | probe_ent->port[i].altstatus_addr = |
| 580 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; |
| 581 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; |
| 582 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; |
| 583 | ata_std_ports(&probe_ent->port[i]); |
| 584 | } |
| 585 | |
| 586 | /* Initialize FIFO PCI bus arbitration */ |
| 587 | cls = sil_get_device_cache_line(pdev); |
| 588 | if (cls) { |
| 589 | cls >>= 3; |
| 590 | cls++; /* cls = (line_size/8)+1 */ |
Tejun Heo | 48d4ef2 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 591 | for (i = 0; i < probe_ent->n_ports; i++) |
| 592 | writew(cls << 8 | cls, |
| 593 | mmio_base + sil_port[i].fifo_cfg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | } else |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 595 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 48d4ef2 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 596 | "cache line size not set. Driver may not function\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | |
Tejun Heo | e4e10e3 | 2006-02-25 13:52:30 +0900 | [diff] [blame] | 598 | /* Apply R_ERR on DMA activate FIS errata workaround */ |
| 599 | if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) { |
| 600 | int cnt; |
| 601 | |
| 602 | for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) { |
| 603 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); |
| 604 | if ((tmp & 0x3) != 0x01) |
| 605 | continue; |
| 606 | if (!cnt) |
| 607 | dev_printk(KERN_INFO, &pdev->dev, |
| 608 | "Applying R_ERR on DMA activate " |
| 609 | "FIS errata fix\n"); |
| 610 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); |
| 611 | cnt++; |
| 612 | } |
| 613 | } |
| 614 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | if (ent->driver_data == sil_3114) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 616 | /* flip the magic "make 4 ports work" bit */ |
Tejun Heo | 48d4ef2 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 617 | tmp = readl(mmio_base + sil_port[2].bmdma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | if ((tmp & SIL_INTR_STEERING) == 0) |
| 619 | writel(tmp | SIL_INTR_STEERING, |
Tejun Heo | 48d4ef2 | 2006-03-05 16:03:52 +0900 | [diff] [blame] | 620 | mmio_base + sil_port[2].bmdma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | /* mask all SATA phy-related interrupts */ |
| 624 | /* TODO: unmask bit 6 (SError N bit) for hotplug */ |
| 625 | for (i = 0; i < probe_ent->n_ports; i++) |
| 626 | writel(0, mmio_base + sil_port[i].sien); |
| 627 | |
| 628 | pci_set_master(pdev); |
| 629 | |
| 630 | /* FIXME: check ata_device_add return value */ |
| 631 | ata_device_add(probe_ent); |
| 632 | kfree(probe_ent); |
| 633 | |
| 634 | return 0; |
| 635 | |
| 636 | err_out_free_ent: |
| 637 | kfree(probe_ent); |
| 638 | err_out_regions: |
| 639 | pci_release_regions(pdev); |
| 640 | err_out: |
| 641 | if (!pci_dev_busy) |
| 642 | pci_disable_device(pdev); |
| 643 | return rc; |
| 644 | } |
| 645 | |
| 646 | static int __init sil_init(void) |
| 647 | { |
| 648 | return pci_module_init(&sil_pci_driver); |
| 649 | } |
| 650 | |
| 651 | static void __exit sil_exit(void) |
| 652 | { |
| 653 | pci_unregister_driver(&sil_pci_driver); |
| 654 | } |
| 655 | |
| 656 | |
| 657 | module_init(sil_init); |
| 658 | module_exit(sil_exit); |