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Alexander Duyckd4e0fe02009-04-07 14:37:34 +00001/*******************************************************************************
2
3 Intel(R) 82576 Virtual Function Linux driver
Mitch A Williams2a06ed92012-01-17 04:09:05 +00004 Copyright(c) 2009 - 2012 Intel Corporation.
Alexander Duyckd4e0fe02009-04-07 14:37:34 +00005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
Jeff Kirsher03405012015-01-21 09:57:50 +000016 this program; if not, see <http://www.gnu.org/licenses/>.
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000017
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27#ifndef _E1000_VF_H_
28#define _E1000_VF_H_
29
30#include <linux/pci.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/if_ether.h>
34
35#include "regs.h"
36#include "defines.h"
37
38struct e1000_hw;
39
Jeff Kirsher03405012015-01-21 09:57:50 +000040#define E1000_DEV_ID_82576_VF 0x10CA
41#define E1000_DEV_ID_I350_VF 0x1520
42#define E1000_REVISION_0 0
43#define E1000_REVISION_1 1
44#define E1000_REVISION_2 2
45#define E1000_REVISION_3 3
46#define E1000_REVISION_4 4
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000047
Jeff Kirsher03405012015-01-21 09:57:50 +000048#define E1000_FUNC_0 0
49#define E1000_FUNC_1 1
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000050
Jeff Kirsher03405012015-01-21 09:57:50 +000051/* Receive Address Register Count
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000052 * Number of high/low register pairs in the RAR. The RAR (Receive Address
53 * Registers) holds the directed and multicast addresses that we monitor.
54 * These entries are also used for MAC-based filtering.
55 */
Jeff Kirsher03405012015-01-21 09:57:50 +000056#define E1000_RAR_ENTRIES_VF 1
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000057
58/* Receive Descriptor - Advanced */
59union e1000_adv_rx_desc {
60 struct {
Jeff Kirsher03405012015-01-21 09:57:50 +000061 u64 pkt_addr; /* Packet buffer address */
62 u64 hdr_addr; /* Header buffer address */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000063 } read;
64 struct {
65 struct {
66 union {
67 u32 data;
68 struct {
69 u16 pkt_info; /* RSS/Packet type */
Jeff Kirsher03405012015-01-21 09:57:50 +000070 /* Split Header, hdr buffer length */
71 u16 hdr_info;
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000072 } hs_rss;
73 } lo_dword;
74 union {
Jeff Kirsher03405012015-01-21 09:57:50 +000075 u32 rss; /* RSS Hash */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000076 struct {
Jeff Kirsher03405012015-01-21 09:57:50 +000077 u16 ip_id; /* IP id */
78 u16 csum; /* Packet Checksum */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000079 } csum_ip;
80 } hi_dword;
81 } lower;
82 struct {
Jeff Kirsher03405012015-01-21 09:57:50 +000083 u32 status_error; /* ext status/error */
84 u16 length; /* Packet length */
85 u16 vlan; /* VLAN tag */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000086 } upper;
87 } wb; /* writeback */
88};
89
Jeff Kirsher03405012015-01-21 09:57:50 +000090#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
91#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000092
93/* Transmit Descriptor - Advanced */
94union e1000_adv_tx_desc {
95 struct {
Jeff Kirsher03405012015-01-21 09:57:50 +000096 u64 buffer_addr; /* Address of descriptor's data buf */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +000097 u32 cmd_type_len;
98 u32 olinfo_status;
99 } read;
100 struct {
Jeff Kirsher03405012015-01-21 09:57:50 +0000101 u64 rsvd; /* Reserved */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000102 u32 nxtseq_seed;
103 u32 status;
104 } wb;
105};
106
107/* Adv Transmit Descriptor Config Masks */
Jeff Kirsher03405012015-01-21 09:57:50 +0000108#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
109#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
110#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
111#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
112#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
113#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
114#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
115#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
116#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000117
118/* Context descriptors */
119struct e1000_adv_tx_context_desc {
120 u32 vlan_macip_lens;
121 u32 seqnum_seed;
122 u32 type_tucmd_mlhl;
123 u32 mss_l4len_idx;
124};
125
Jeff Kirsher03405012015-01-21 09:57:50 +0000126#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
127#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
128#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
Alexander Duyckea6ce602016-01-13 07:31:30 -0800129#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
Jeff Kirsher03405012015-01-21 09:57:50 +0000130#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
131#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000132
133enum e1000_mac_type {
134 e1000_undefined = 0,
135 e1000_vfadapt,
Williams, Mitch A031d7952010-12-09 03:23:56 +0000136 e1000_vfadapt_i350,
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000137 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
138};
139
140struct e1000_vf_stats {
141 u64 base_gprc;
142 u64 base_gptc;
143 u64 base_gorc;
144 u64 base_gotc;
145 u64 base_mprc;
146 u64 base_gotlbc;
147 u64 base_gptlbc;
148 u64 base_gorlbc;
149 u64 base_gprlbc;
150
151 u32 last_gprc;
152 u32 last_gptc;
153 u32 last_gorc;
154 u32 last_gotc;
155 u32 last_mprc;
156 u32 last_gotlbc;
157 u32 last_gptlbc;
158 u32 last_gorlbc;
159 u32 last_gprlbc;
160
161 u64 gprc;
162 u64 gptc;
163 u64 gorc;
164 u64 gotc;
165 u64 mprc;
166 u64 gotlbc;
167 u64 gptlbc;
168 u64 gorlbc;
169 u64 gprlbc;
170};
171
172#include "mbx.h"
173
174struct e1000_mac_operations {
175 /* Function pointers for the MAC. */
176 s32 (*init_params)(struct e1000_hw *);
177 s32 (*check_for_link)(struct e1000_hw *);
178 void (*clear_vfta)(struct e1000_hw *);
179 s32 (*get_bus_info)(struct e1000_hw *);
180 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
181 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
182 s32 (*reset_hw)(struct e1000_hw *);
183 s32 (*init_hw)(struct e1000_hw *);
184 s32 (*setup_link)(struct e1000_hw *);
185 void (*write_vfta)(struct e1000_hw *, u32, u32);
186 void (*mta_set)(struct e1000_hw *, u32);
187 void (*rar_set)(struct e1000_hw *, u8*, u32);
188 s32 (*read_mac_addr)(struct e1000_hw *);
189 s32 (*set_vfta)(struct e1000_hw *, u16, bool);
190};
191
192struct e1000_mac_info {
193 struct e1000_mac_operations ops;
194 u8 addr[6];
195 u8 perm_addr[6];
196
197 enum e1000_mac_type type;
198
199 u16 mta_reg_count;
200 u16 rar_entry_count;
201
202 bool get_link_status;
203};
204
205struct e1000_mbx_operations {
206 s32 (*init_params)(struct e1000_hw *hw);
207 s32 (*read)(struct e1000_hw *, u32 *, u16);
208 s32 (*write)(struct e1000_hw *, u32 *, u16);
209 s32 (*read_posted)(struct e1000_hw *, u32 *, u16);
210 s32 (*write_posted)(struct e1000_hw *, u32 *, u16);
211 s32 (*check_for_msg)(struct e1000_hw *);
212 s32 (*check_for_ack)(struct e1000_hw *);
213 s32 (*check_for_rst)(struct e1000_hw *);
214};
215
216struct e1000_mbx_stats {
217 u32 msgs_tx;
218 u32 msgs_rx;
219
220 u32 acks;
221 u32 reqs;
222 u32 rsts;
223};
224
225struct e1000_mbx_info {
226 struct e1000_mbx_operations ops;
227 struct e1000_mbx_stats stats;
228 u32 timeout;
229 u32 usec_delay;
230 u16 size;
231};
232
233struct e1000_dev_spec_vf {
234 u32 vf_number;
235 u32 v2p_mailbox;
236};
237
238struct e1000_hw {
239 void *back;
240
241 u8 __iomem *hw_addr;
242 u8 __iomem *flash_address;
243 unsigned long io_base;
244
245 struct e1000_mac_info mac;
246 struct e1000_mbx_info mbx;
247
248 union {
249 struct e1000_dev_spec_vf vf;
250 } dev_spec;
251
252 u16 device_id;
253 u16 subsystem_vendor_id;
254 u16 subsystem_device_id;
255 u16 vendor_id;
256
257 u8 revision_id;
258};
259
260/* These functions must be implemented by drivers */
261void e1000_rlpml_set_vf(struct e1000_hw *, u16);
262void e1000_init_function_pointers_vf(struct e1000_hw *hw);
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000263
Alexander Duyckd4e0fe02009-04-07 14:37:34 +0000264#endif /* _E1000_VF_H_ */