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gerrit-public.fairphone.software / kernel / msm-4.9 / cc21181217549e0a894dd6b57feacbcb979d831b / . / drivers / staging / vt6655 / mac.h
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Forest Bond5449c682009-04-25 10:30:44 -0400[diff] [blame]1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: mac.h
21 *
22 * Purpose: MAC routines
23 *
24 * Author: Tevin Chen
25 *
26 * Date: May 21, 1996
27 * Revision History:
28 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
29 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
30 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
31 *
32 */
33
34#ifndef __MAC_H__
35#define __MAC_H__
36
37
38
39#if !defined(__TTYPE_H__)
40#include "ttype.h"
41#endif
42#if !defined(__TMACRO_H__)
43#include "tmacro.h"
44#endif
45#if !defined(__UPC_H__)
46#include "upc.h"
47#endif
48
49/*--------------------- Export Definitions -------------------------*/
50//
51// Registers in the MAC
52//
53#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
54#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
55#define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
56
57// Registers not related to 802.11b
58#define MAC_REG_BCFG0 0x00
59#define MAC_REG_BCFG1 0x01
60#define MAC_REG_FCR0 0x02
61#define MAC_REG_FCR1 0x03
62#define MAC_REG_BISTCMD 0x04
63#define MAC_REG_BISTSR0 0x05
64#define MAC_REG_BISTSR1 0x06
65#define MAC_REG_BISTSR2 0x07
66#define MAC_REG_I2MCSR 0x08
67#define MAC_REG_I2MTGID 0x09
68#define MAC_REG_I2MTGAD 0x0A
69#define MAC_REG_I2MCFG 0x0B
70#define MAC_REG_I2MDIPT 0x0C
71#define MAC_REG_I2MDOPT 0x0E
72#define MAC_REG_PMC0 0x10
73#define MAC_REG_PMC1 0x11
74#define MAC_REG_STICKHW 0x12
75#define MAC_REG_LOCALID 0x14
76#define MAC_REG_TESTCFG 0x15
77#define MAC_REG_JUMPER0 0x16
78#define MAC_REG_JUMPER1 0x17
79#define MAC_REG_TMCTL0 0x18
80#define MAC_REG_TMCTL1 0x19
81#define MAC_REG_TMDATA0 0x1C
82// MAC Parameter related
83#define MAC_REG_LRT 0x20 //
84#define MAC_REG_SRT 0x21 //
85#define MAC_REG_SIFS 0x22 //
86#define MAC_REG_DIFS 0x23 //
87#define MAC_REG_EIFS 0x24 //
88#define MAC_REG_SLOT 0x25 //
89#define MAC_REG_BI 0x26 //
90#define MAC_REG_CWMAXMIN0 0x28 //
91#define MAC_REG_LINKOFFTOTM 0x2A
92#define MAC_REG_SWTMOT 0x2B
93#define MAC_REG_MIBCNTR 0x2C
94#define MAC_REG_RTSOKCNT 0x2C
95#define MAC_REG_RTSFAILCNT 0x2D
96#define MAC_REG_ACKFAILCNT 0x2E
97#define MAC_REG_FCSERRCNT 0x2F
98// TSF Related
99#define MAC_REG_TSFCNTR 0x30 //
100#define MAC_REG_NEXTTBTT 0x38 //
101#define MAC_REG_TSFOFST 0x40 //
102#define MAC_REG_TFTCTL 0x48 //
103// WMAC Control/Status Related
104#define MAC_REG_ENCFG 0x4C //
105#define MAC_REG_PAGE1SEL 0x4F //
106#define MAC_REG_CFG 0x50 //
107#define MAC_REG_TEST 0x52 //
108#define MAC_REG_HOSTCR 0x54 //
109#define MAC_REG_MACCR 0x55 //
110#define MAC_REG_RCR 0x56 //
111#define MAC_REG_TCR 0x57 //
112#define MAC_REG_IMR 0x58 //
113#define MAC_REG_ISR 0x5C
114// Power Saving Related
115#define MAC_REG_PSCFG 0x60 //
116#define MAC_REG_PSCTL 0x61 //
117#define MAC_REG_PSPWRSIG 0x62 //
118#define MAC_REG_BBCR13 0x63
119#define MAC_REG_AIDATIM 0x64
120#define MAC_REG_PWBT 0x66
121#define MAC_REG_WAKEOKTMR 0x68
122#define MAC_REG_CALTMR 0x69
123#define MAC_REG_SYNSPACCNT 0x6A
124#define MAC_REG_WAKSYNOPT 0x6B
125// Baseband/IF Control Group
126#define MAC_REG_BBREGCTL 0x6C //
127#define MAC_REG_CHANNEL 0x6D
128#define MAC_REG_BBREGADR 0x6E
129#define MAC_REG_BBREGDATA 0x6F
130#define MAC_REG_IFREGCTL 0x70 //
131#define MAC_REG_IFDATA 0x71 //
132#define MAC_REG_ITRTMSET 0x74 //
133#define MAC_REG_PAPEDELAY 0x77 //
134#define MAC_REG_SOFTPWRCTL 0x78 //
135#define MAC_REG_GPIOCTL0 0x7A //
136#define MAC_REG_GPIOCTL1 0x7B //
137
138// MAC DMA Related Group
139#define MAC_REG_TXDMACTL0 0x7C //
140#define MAC_REG_TXDMAPTR0 0x80 //
141#define MAC_REG_AC0DMACTL 0x84 //
142#define MAC_REG_AC0DMAPTR 0x88 //
143#define MAC_REG_BCNDMACTL 0x8C //
144#define MAC_REG_BCNDMAPTR 0x90 //
145#define MAC_REG_RXDMACTL0 0x94 //
146#define MAC_REG_RXDMAPTR0 0x98 //
147#define MAC_REG_RXDMACTL1 0x9C //
148#define MAC_REG_RXDMAPTR1 0xA0 //
149#define MAC_REG_SYNCDMACTL 0xA4 //
150#define MAC_REG_SYNCDMAPTR 0xA8
151#define MAC_REG_ATIMDMACTL 0xAC
152#define MAC_REG_ATIMDMAPTR 0xB0
153// MiscFF PIO related
154#define MAC_REG_MISCFFNDEX 0xB4
155#define MAC_REG_MISCFFCTL 0xB6
156#define MAC_REG_MISCFFDATA 0xB8
157// Extend SW Timer
158#define MAC_REG_TMDATA1 0xBC
159// WOW Related Group
160#define MAC_REG_WAKEUPEN0 0xC0
161#define MAC_REG_WAKEUPEN1 0xC1
162#define MAC_REG_WAKEUPSR0 0xC2
163#define MAC_REG_WAKEUPSR1 0xC3
164#define MAC_REG_WAKE128_0 0xC4
165#define MAC_REG_WAKE128_1 0xD4
166#define MAC_REG_WAKE128_2 0xE4
167#define MAC_REG_WAKE128_3 0xF4
168
169/////////////// Page 1 ///////////////////
170#define MAC_REG_CRC_128_0 0x04
171#define MAC_REG_CRC_128_1 0x06
172#define MAC_REG_CRC_128_2 0x08
173#define MAC_REG_CRC_128_3 0x0A
174// MAC Configuration Group
175#define MAC_REG_PAR0 0x0C
176#define MAC_REG_PAR4 0x10
177#define MAC_REG_BSSID0 0x14
178#define MAC_REG_BSSID4 0x18
179#define MAC_REG_MAR0 0x1C
180#define MAC_REG_MAR4 0x20
181// MAC RSPPKT INFO Group
182#define MAC_REG_RSPINF_B_1 0x24
183#define MAC_REG_RSPINF_B_2 0x28
184#define MAC_REG_RSPINF_B_5 0x2C
185#define MAC_REG_RSPINF_B_11 0x30
186#define MAC_REG_RSPINF_A_6 0x34
187#define MAC_REG_RSPINF_A_9 0x36
188#define MAC_REG_RSPINF_A_12 0x38
189#define MAC_REG_RSPINF_A_18 0x3A
190#define MAC_REG_RSPINF_A_24 0x3C
191#define MAC_REG_RSPINF_A_36 0x3E
192#define MAC_REG_RSPINF_A_48 0x40
193#define MAC_REG_RSPINF_A_54 0x42
194#define MAC_REG_RSPINF_A_72 0x44
195
196// 802.11h relative
197#define MAC_REG_QUIETINIT 0x60
198#define MAC_REG_QUIETGAP 0x62
199#define MAC_REG_QUIETDUR 0x64
200#define MAC_REG_MSRCTL 0x66
201#define MAC_REG_MSRBBSTS 0x67
202#define MAC_REG_MSRSTART 0x68
203#define MAC_REG_MSRDURATION 0x70
204#define MAC_REG_CCAFRACTION 0x72
205#define MAC_REG_PWRCCK 0x73
206#define MAC_REG_PWROFDM 0x7C
207
208
209//
210// Bits in the BCFG0 register
211//
212#define BCFG0_PERROFF 0x40
213#define BCFG0_MRDMDIS 0x20
214#define BCFG0_MRDLDIS 0x10
215#define BCFG0_MWMEN 0x08
216#define BCFG0_VSERREN 0x02
217#define BCFG0_LATMEN 0x01
218
219//
220// Bits in the BCFG1 register
221//
222#define BCFG1_CFUNOPT 0x80
223#define BCFG1_CREQOPT 0x40
224#define BCFG1_DMA8 0x10
225#define BCFG1_ARBITOPT 0x08
226#define BCFG1_PCIMEN 0x04
227#define BCFG1_MIOEN 0x02
228#define BCFG1_CISDLYEN 0x01
229
230// Bits in RAMBIST registers
231#define BISTCMD_TSTPAT5 0x00 //
232#define BISTCMD_TSTPATA 0x80 //
233#define BISTCMD_TSTERR 0x20 //
234#define BISTCMD_TSTPATF 0x18 //
235#define BISTCMD_TSTPAT0 0x10 //
236#define BISTCMD_TSTMODE 0x04 //
237#define BISTCMD_TSTITTX 0x03 //
238#define BISTCMD_TSTATRX 0x02 //
239#define BISTCMD_TSTATTX 0x01 //
240#define BISTCMD_TSTRX 0x00 //
241#define BISTSR0_BISTGO 0x01 //
242#define BISTSR1_TSTSR 0x01 //
243#define BISTSR2_CMDPRTEN 0x02 //
244#define BISTSR2_RAMTSTEN 0x01 //
245
246//
247// Bits in the I2MCFG EEPROM register
248//
249#define I2MCFG_BOUNDCTL 0x80
250#define I2MCFG_WAITCTL 0x20
251#define I2MCFG_SCLOECTL 0x10
252#define I2MCFG_WBUSYCTL 0x08
253#define I2MCFG_NORETRY 0x04
254#define I2MCFG_I2MLDSEQ 0x02
255#define I2MCFG_I2CMFAST 0x01
256
257//
258// Bits in the I2MCSR EEPROM register
259//
260#define I2MCSR_EEMW 0x80
261#define I2MCSR_EEMR 0x40
262#define I2MCSR_AUTOLD 0x08
263#define I2MCSR_NACK 0x02
264#define I2MCSR_DONE 0x01
265
266//
267// Bits in the PMC1 register
268//
269#define SPS_RST 0x80
270#define PCISTIKY 0x40
271#define PME_OVR 0x02
272
273//
274// Bits in the STICKYHW register
275//
276#define STICKHW_DS1_SHADOW 0x02
277#define STICKHW_DS0_SHADOW 0x01
278
279//
280// Bits in the TMCTL register
281//
282#define TMCTL_TSUSP 0x04
283#define TMCTL_TMD 0x02
284#define TMCTL_TE 0x01
285
286//
287// Bits in the TFTCTL register
288//
289#define TFTCTL_HWUTSF 0x80 //
290#define TFTCTL_TBTTSYNC 0x40
291#define TFTCTL_HWUTSFEN 0x20
292#define TFTCTL_TSFCNTRRD 0x10 //
293#define TFTCTL_TBTTSYNCEN 0x08 //
294#define TFTCTL_TSFSYNCEN 0x04 //
295#define TFTCTL_TSFCNTRST 0x02 //
296#define TFTCTL_TSFCNTREN 0x01 //
297
298//
299// Bits in the EnhanceCFG register
300//
301#define EnCFG_BarkerPream 0x00020000
302#define EnCFG_NXTBTTCFPSTR 0x00010000
303//#define EnCFG_TXLMT3UPDATE 0x00008000
304//#define EnCFG_TXLMT2UPDATE 0x00004000
305//#define EnCFG_TXLMT1UPDATE 0x00002000
306//#define EnCFG_TXLMT3EN 0x00001000
307//#define EnCFG_TXLMT2EN 0x00000800
308//#define EnCFG_TXLMT1EN 0x00000400
309#define EnCFG_BcnSusClr 0x00000200
310#define EnCFG_BcnSusInd 0x00000100
311//#define EnCFG_CWOFF1 0x00000080
312#define EnCFG_CFP_ProtectEn 0x00000040
313#define EnCFG_ProtectMd 0x00000020
314#define EnCFG_HwParCFP 0x00000010
315//#define EnCFG_QOS 0x00000008
316#define EnCFG_CFNULRSP 0x00000004
317#define EnCFG_BBType_MASK 0x00000003
318#define EnCFG_BBType_g 0x00000002
319#define EnCFG_BBType_b 0x00000001
320#define EnCFG_BBType_a 0x00000000
321
322//
323// Bits in the Page1Sel register
324//
325#define PAGE1_SEL 0x01
326
327//
328// Bits in the CFG register
329//
330#define CFG_TKIPOPT 0x80
331#define CFG_RXDMAOPT 0x40
332#define CFG_TMOT_SW 0x20
333#define CFG_TMOT_HWLONG 0x10
334#define CFG_TMOT_HW 0x00
335#define CFG_CFPENDOPT 0x08
336#define CFG_BCNSUSEN 0x04
337#define CFG_NOTXTIMEOUT 0x02
338#define CFG_NOBUFOPT 0x01
339
340//
341// Bits in the TEST register
342//
343#define TEST_LBEXT 0x80 //
344#define TEST_LBINT 0x40 //
345#define TEST_LBNONE 0x00 //
346#define TEST_SOFTINT 0x20 //
347#define TEST_CONTTX 0x10 //
348#define TEST_TXPE 0x08 //
349#define TEST_NAVDIS 0x04 //
350#define TEST_NOCTS 0x02 //
351#define TEST_NOACK 0x01 //
352
353//
354// Bits in the HOSTCR register
355//
356#define HOSTCR_TXONST 0x80 //
357#define HOSTCR_RXONST 0x40 //
358#define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
359#define HOSTCR_AP 0x10 // Port Type 1 = AP
360#define HOSTCR_TXON 0x08 //0000 1000
361#define HOSTCR_RXON 0x04 //0000 0100
362#define HOSTCR_MACEN 0x02 //0000 0010
363#define HOSTCR_SOFTRST 0x01 //0000 0001
364
365//
366// Bits in the MACCR register
367//
368#define MACCR_SYNCFLUSHOK 0x04 //
369#define MACCR_SYNCFLUSH 0x02 //
370#define MACCR_CLRNAV 0x01 //
371
372// Bits in the MAC_REG_GPIOCTL0 register
373//
374#define LED_ACTSET 0x01 //
375#define LED_RFOFF 0x02 //
376#define LED_NOCONNECT 0x04 //
377//
378// Bits in the RCR register
379//
380#define RCR_SSID 0x80
381#define RCR_RXALLTYPE 0x40 //
382#define RCR_UNICAST 0x20 //
383#define RCR_BROADCAST 0x10 //
384#define RCR_MULTICAST 0x08 //
385#define RCR_WPAERR 0x04 //
386#define RCR_ERRCRC 0x02 //
387#define RCR_BSSID 0x01 //
388
389//
390// Bits in the TCR register
391//
392#define TCR_SYNCDCFOPT 0x02 //
393#define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
394
395//
396// Bits in the IMR register
397//
398#define IMR_MEASURESTART 0x80000000 //
399#define IMR_QUIETSTART 0x20000000 //
400#define IMR_RADARDETECT 0x10000000 //
401#define IMR_MEASUREEND 0x08000000 //
402#define IMR_SOFTTIMER1 0x00200000 //
403//#define IMR_SYNCFLUSHOK 0x00100000 //
404//#define IMR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
405//#define IMR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
406//#define IMR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
407//#define IMR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
408//#define IMR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
409//#define IMR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
410//#define IMR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
411#define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
412#define IMR_RXNOBUF 0x00000800 //
413#define IMR_MIBNEARFULL 0x00000400 //
414#define IMR_SOFTINT 0x00000200 //
415#define IMR_FETALERR 0x00000100 //
416#define IMR_WATCHDOG 0x00000080 //
417#define IMR_SOFTTIMER 0x00000040 //
418#define IMR_GPIO 0x00000020 //
419#define IMR_TBTT 0x00000010 //
420#define IMR_RXDMA0 0x00000008 //
421#define IMR_BNTX 0x00000004 //
422#define IMR_AC0DMA 0x00000002 //
423#define IMR_TXDMA0 0x00000001 //
424
425
426//
427// Bits in the ISR register
428//
429
430#define ISR_MEASURESTART 0x80000000 //
431#define ISR_QUIETSTART 0x20000000 //
432#define ISR_RADARDETECT 0x10000000 //
433#define ISR_MEASUREEND 0x08000000 //
434#define ISR_SOFTTIMER1 0x00200000 //
435//#define ISR_SYNCFLUSHOK 0x00100000 //0001 0000 0000 0000 0000 0000
436//#define ISR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
437//#define ISR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
438//#define ISR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
439//#define ISR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
440//#define ISR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
441//#define ISR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
442//#define ISR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
443#define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
444#define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
445#define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
446#define ISR_SOFTINT 0x00000200 //
447#define ISR_FETALERR 0x00000100 //
448#define ISR_WATCHDOG 0x00000080 //
449#define ISR_SOFTTIMER 0x00000040 //
450#define ISR_GPIO 0x00000020 //
451#define ISR_TBTT 0x00000010 //
452#define ISR_RXDMA0 0x00000008 //
453#define ISR_BNTX 0x00000004 //
454#define ISR_AC0DMA 0x00000002 //
455#define ISR_TXDMA0 0x00000001 //
456
457
458//
459// Bits in the PSCFG register
460//
461#define PSCFG_PHILIPMD 0x40 //
462#define PSCFG_WAKECALEN 0x20 //
463#define PSCFG_WAKETMREN 0x10 //
464#define PSCFG_BBPSPROG 0x08 //
465#define PSCFG_WAKESYN 0x04 //
466#define PSCFG_SLEEPSYN 0x02 //
467#define PSCFG_AUTOSLEEP 0x01 //
468
469//
470// Bits in the PSCTL register
471//
472#define PSCTL_WAKEDONE 0x20 //
473#define PSCTL_PS 0x10 //
474#define PSCTL_GO2DOZE 0x08 //
475#define PSCTL_LNBCN 0x04 //
476#define PSCTL_ALBCN 0x02 //
477#define PSCTL_PSEN 0x01 //
478
479//
480// Bits in the PSPWSIG register
481//
482#define PSSIG_WPE3 0x80 //
483#define PSSIG_WPE2 0x40 //
484#define PSSIG_WPE1 0x20 //
485#define PSSIG_WRADIOPE 0x10 //
486#define PSSIG_SPE3 0x08 //
487#define PSSIG_SPE2 0x04 //
488#define PSSIG_SPE1 0x02 //
489#define PSSIG_SRADIOPE 0x01 //
490
491//
492// Bits in the BBREGCTL register
493//
494#define BBREGCTL_DONE 0x04 //
495#define BBREGCTL_REGR 0x02 //
496#define BBREGCTL_REGW 0x01 //
497
498//
499// Bits in the IFREGCTL register
500//
501#define IFREGCTL_DONE 0x04 //
502#define IFREGCTL_IFRF 0x02 //
503#define IFREGCTL_REGW 0x01 //
504
505//
506// Bits in the SOFTPWRCTL register
507//
508#define SOFTPWRCTL_RFLEOPT 0x0800 //
509#define SOFTPWRCTL_TXPEINV 0x0200 //
510#define SOFTPWRCTL_SWPECTI 0x0100 //
511#define SOFTPWRCTL_SWPAPE 0x0020 //
512#define SOFTPWRCTL_SWCALEN 0x0010 //
513#define SOFTPWRCTL_SWRADIO_PE 0x0008 //
514#define SOFTPWRCTL_SWPE2 0x0004 //
515#define SOFTPWRCTL_SWPE1 0x0002 //
516#define SOFTPWRCTL_SWPE3 0x0001 //
517
518//
519// Bits in the GPIOCTL1 register
520//
521#define GPIO1_DATA1 0x20 //
522#define GPIO1_MD1 0x10 //
523#define GPIO1_DATA0 0x02 //
524#define GPIO1_MD0 0x01 //
525
526//
527// Bits in the DMACTL register
528//
529#define DMACTL_CLRRUN 0x00080000 //
530#define DMACTL_RUN 0x00000008 //
531#define DMACTL_WAKE 0x00000004 //
532#define DMACTL_DEAD 0x00000002 //
533#define DMACTL_ACTIVE 0x00000001 //
534//
535// Bits in the RXDMACTL0 register
536//
537#define RX_PERPKT 0x00000100 //
538#define RX_PERPKTCLR 0x01000000 //
539//
540// Bits in the BCNDMACTL register
541//
542#define BEACON_READY 0x01 //
543//
544// Bits in the MISCFFCTL register
545//
546#define MISCFFCTL_WRITE 0x0001 //
547
548
549//
550// Bits in WAKEUPEN0
551//
552#define WAKEUPEN0_DIRPKT 0x10
553#define WAKEUPEN0_LINKOFF 0x08
554#define WAKEUPEN0_ATIMEN 0x04
555#define WAKEUPEN0_TIMEN 0x02
556#define WAKEUPEN0_MAGICEN 0x01
557
558//
559// Bits in WAKEUPEN1
560//
561#define WAKEUPEN1_128_3 0x08
562#define WAKEUPEN1_128_2 0x04
563#define WAKEUPEN1_128_1 0x02
564#define WAKEUPEN1_128_0 0x01
565
566//
567// Bits in WAKEUPSR0
568//
569#define WAKEUPSR0_DIRPKT 0x10
570#define WAKEUPSR0_LINKOFF 0x08
571#define WAKEUPSR0_ATIMEN 0x04
572#define WAKEUPSR0_TIMEN 0x02
573#define WAKEUPSR0_MAGICEN 0x01
574
575//
576// Bits in WAKEUPSR1
577//
578#define WAKEUPSR1_128_3 0x08
579#define WAKEUPSR1_128_2 0x04
580#define WAKEUPSR1_128_1 0x02
581#define WAKEUPSR1_128_0 0x01
582
583//
584// Bits in the MAC_REG_GPIOCTL register
585//
586#define GPIO0_MD 0x01 //
587#define GPIO0_DATA 0x02 //
588#define GPIO0_INTMD 0x04 //
589#define GPIO1_MD 0x10 //
590#define GPIO1_DATA 0x20 //
591
592
593//
594// Bits in the MSRCTL register
595//
596#define MSRCTL_FINISH 0x80
597#define MSRCTL_READY 0x40
598#define MSRCTL_RADARDETECT 0x20
599#define MSRCTL_EN 0x10
600#define MSRCTL_QUIETTXCHK 0x08
601#define MSRCTL_QUIETRPT 0x04
602#define MSRCTL_QUIETINT 0x02
603#define MSRCTL_QUIETEN 0x01
604//
605// Bits in the MSRCTL1 register
606//
607#define MSRCTL1_TXPWR 0x08
608#define MSRCTL1_CSAPAREN 0x04
609#define MSRCTL1_TXPAUSE 0x01
610
611
612// Loopback mode
613#define MAC_LB_EXT 0x02 //
614#define MAC_LB_INTERNAL 0x01 //
615#define MAC_LB_NONE 0x00 //
616
617// Ethernet address filter type
618#define PKT_TYPE_NONE 0x00 // turn off receiver
619#define PKT_TYPE_ALL_MULTICAST 0x80
620#define PKT_TYPE_PROMISCUOUS 0x40
621#define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
622#define PKT_TYPE_BROADCAST 0x10
623#define PKT_TYPE_MULTICAST 0x08
624#define PKT_TYPE_ERROR_WPA 0x04
625#define PKT_TYPE_ERROR_CRC 0x02
626#define PKT_TYPE_BSSID 0x01
627
628#define Default_BI 0x200
629
630
631// MiscFIFO Offset
632#define MISCFIFO_KEYETRY0 32
633#define MISCFIFO_KEYENTRYSIZE 22
634#define MISCFIFO_SYNINFO_IDX 10
635#define MISCFIFO_SYNDATA_IDX 11
636#define MISCFIFO_SYNDATASIZE 21
637
638// enabled mask value of irq
639#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
640 IMR_RXDMA1 | \
641 IMR_RXNOBUF | \
642 IMR_MIBNEARFULL | \
643 IMR_SOFTINT | \
644 IMR_FETALERR | \
645 IMR_WATCHDOG | \
646 IMR_SOFTTIMER | \
647 IMR_GPIO | \
648 IMR_TBTT | \
649 IMR_RXDMA0 | \
650 IMR_BNTX | \
651 IMR_AC0DMA | \
652 IMR_TXDMA0)
653
654// max time out delay time
655#define W_MAX_TIMEOUT 0xFFF0U //
656
657// wait time within loop
658#define CB_DELAY_LOOP_WAIT 10 // 10ms
659
660//
661// revision id
662//
663#define REV_ID_VT3253_A0 0x00
664#define REV_ID_VT3253_A1 0x01
665#define REV_ID_VT3253_B0 0x08
666#define REV_ID_VT3253_B1 0x09
667
668/*--------------------- Export Types ------------------------------*/
669
670/*--------------------- Export Macros ------------------------------*/
671
672#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
673{ \
674 BYTE byData; \
675 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
676 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
677}
678
679#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
680{ \
681 WORD wData; \
682 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
683 VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
684}
685
686#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
687{ \
688 DWORD dwData; \
689 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
690 VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
691}
692
693#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
694{ \
695 BYTE byData; \
696 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
697 byData &= byMask; \
698 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
699}
700
701#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
702{ \
703 BYTE byData; \
704 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
705 VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
706}
707
708#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
709{ \
710 WORD wData; \
711 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
712 VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
713}
714
715#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
716{ \
717 DWORD dwData; \
718 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
719 VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
720}
721
722#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
723{ \
724 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
725 (PDWORD)pdwCurrDescAddr); \
726}
727
728#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
729{ \
730 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
731 (PDWORD)pdwCurrDescAddr); \
732}
733
734#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
735{ \
736 VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
737 (PDWORD)pdwCurrDescAddr); \
738}
739
740#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
741{ \
742 VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
743 (PDWORD)pdwCurrDescAddr); \
744}
745
746#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
747{ \
748 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
749 (PDWORD)pdwCurrDescAddr); \
750}
751
752#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
753{ \
754 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
755 (PDWORD)pdwCurrDescAddr); \
756} \
757
758// set the chip with current BCN tx descriptor address
759#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
760{ \
761 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
762 dwCurrDescAddr); \
763}
764
765// set the chip with current BCN length
766#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
767{ \
768 VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
769 wCurrBCNLength); \
770}
771
772#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
773{ \
774 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
775 VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
776 (PBYTE)pbyEtherAddr); \
777 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
778 pbyEtherAddr + 1); \
779 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
780 pbyEtherAddr + 2); \
781 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
782 pbyEtherAddr + 3); \
783 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
784 pbyEtherAddr + 4); \
785 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
786 pbyEtherAddr + 5); \
787 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
788}
789
790#define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
791{ \
792 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
793 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
794 *(pbyEtherAddr)); \
795 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
796 *(pbyEtherAddr + 1)); \
797 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
798 *(pbyEtherAddr + 2)); \
799 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
800 *(pbyEtherAddr + 3)); \
801 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
802 *(pbyEtherAddr + 4)); \
803 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
804 *(pbyEtherAddr + 5)); \
805 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
806}
807
808#define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
809{ \
810 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
811 VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
812 (PBYTE)pbyEtherAddr); \
813 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
814 pbyEtherAddr + 1); \
815 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
816 pbyEtherAddr + 2); \
817 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
818 pbyEtherAddr + 3); \
819 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
820 pbyEtherAddr + 4); \
821 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
822 pbyEtherAddr + 5); \
823 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
824}
825
826
827#define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
828{ \
829 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
830 VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
831 *pbyEtherAddr); \
832 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
833 *(pbyEtherAddr + 1)); \
834 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
835 *(pbyEtherAddr + 2)); \
836 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
837 *(pbyEtherAddr + 3)); \
838 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
839 *(pbyEtherAddr + 4)); \
840 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
841 *(pbyEtherAddr + 5)); \
842 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
843}
844
845
846#define MACvClearISR(dwIoBase) \
847{ \
848 VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE); \
849}
850
851#define MACvStart(dwIoBase) \
852{ \
853 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
854 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \
855}
856
857#define MACvRx0PerPktMode(dwIoBase) \
858{ \
859 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT); \
860}
861
862#define MACvRx0BufferFillMode(dwIoBase) \
863{ \
864 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR); \
865}
866
867#define MACvRx1PerPktMode(dwIoBase) \
868{ \
869 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT); \
870}
871
872#define MACvRx1BufferFillMode(dwIoBase) \
873{ \
874 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR); \
875}
876
877#define MACvRxOn(dwIoBase) \
878{ \
879 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); \
880}
881
882#define MACvReceive0(dwIoBase) \
883{ \
884 DWORD dwData; \
885 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
886 if (dwData & DMACTL_RUN) { \
887 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE);\
888 } \
889 else { \
890 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
891 } \
892}
893
894#define MACvReceive1(dwIoBase) \
895{ \
896 DWORD dwData; \
897 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
898 if (dwData & DMACTL_RUN) { \
899 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE);\
900 } \
901 else { \
902 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
903 } \
904}
905
906#define MACvTxOn(dwIoBase) \
907{ \
908 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); \
909}
910
911#define MACvTransmit0(dwIoBase) \
912{ \
913 DWORD dwData; \
914 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
915 if (dwData & DMACTL_RUN) { \
916 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE);\
917 } \
918 else { \
919 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
920 } \
921}
922
923#define MACvTransmitAC0(dwIoBase) \
924{ \
925 DWORD dwData; \
926 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
927 if (dwData & DMACTL_RUN) { \
928 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE);\
929 } \
930 else { \
931 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
932 } \
933}
934
935#define MACvTransmitSYNC(dwIoBase) \
936{ \
937 DWORD dwData; \
938 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
939 if (dwData & DMACTL_RUN) { \
940 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE);\
941 } \
942 else { \
943 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
944 } \
945}
946
947#define MACvTransmitATIM(dwIoBase) \
948{ \
949 DWORD dwData; \
950 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
951 if (dwData & DMACTL_RUN) { \
952 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE);\
953 } \
954 else { \
955 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
956 } \
957}
958
959#define MACvTransmitBCN(dwIoBase) \
960{ \
961 VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY); \
962}
963
964#define MACvClearStckDS(dwIoBase) \
965{ \
966 BYTE byOrgValue; \
967 VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
968 byOrgValue = byOrgValue & 0xFC; \
969 VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
970}
971
972#define MACvReadISR(dwIoBase, pdwValue) \
973{ \
974 VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue); \
975}
976
977#define MACvWriteISR(dwIoBase, dwValue) \
978{ \
979 VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue); \
980}
981
982#define MACvIntEnable(dwIoBase, dwMask) \
983{ \
984 VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask); \
985}
986
987#define MACvIntDisable(dwIoBase) \
988{ \
989 VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0); \
990}
991
992#define MACvSelectPage0(dwIoBase) \
993{ \
994 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
995}
996#define MACvSelectPage1(dwIoBase) \
997{ \
998 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
999}
1000
1001#define MACvReadMIBCounter(dwIoBase, pdwCounter) \
1002{ \
1003 VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter); \
1004}
1005
1006#define MACvPwrEvntDisable(dwIoBase) \
1007{ \
1008 VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \
1009}
1010
1011#define MACvEnableProtectMD(dwIoBase) \
1012{ \
1013 DWORD dwOrgValue; \
1014 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1015 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
1016 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1017}
1018
1019#define MACvDisableProtectMD(dwIoBase) \
1020{ \
1021 DWORD dwOrgValue; \
1022 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1023 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
1024 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1025}
1026
1027#define MACvEnableBarkerPreambleMd(dwIoBase) \
1028{ \
1029 DWORD dwOrgValue; \
1030 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1031 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
1032 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1033}
1034
1035#define MACvDisableBarkerPreambleMd(dwIoBase) \
1036{ \
1037 DWORD dwOrgValue; \
1038 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1039 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
1040 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1041}
1042
1043#define MACvSetBBType(dwIoBase, byTyp) \
1044{ \
1045 DWORD dwOrgValue; \
1046 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1047 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
1048 dwOrgValue = dwOrgValue | (DWORD) byTyp; \
1049 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1050}
1051
1052#define MACvReadATIMW(dwIoBase, pwCounter) \
1053{ \
1054 VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter); \
1055}
1056
1057#define MACvWriteATIMW(dwIoBase, wCounter) \
1058{ \
1059 VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter); \
1060}
1061
1062#define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
1063{ \
1064 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
1065 VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
1066 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
1067}
1068
1069#define MACvGPIOIn(dwIoBase, pbyValue) \
1070{ \
1071 VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue); \
1072}
1073
1074#define MACvSetRFLE_LatchBase(dwIoBase) \
1075{ \
1076 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \
1077}
1078
1079/*--------------------- Export Classes ----------------------------*/
1080
1081/*--------------------- Export Variables --------------------------*/
1082
1083/*--------------------- Export Functions --------------------------*/
1084#ifdef __cplusplus
1085extern "C" { /* Assume C declarations for C++ */
1086#endif /* __cplusplus */
1087
1088extern WORD TxRate_iwconfig;//2008-5-8 <add> by chester
1089VOID MACvReadAllRegs(DWORD_PTR dwIoBase, PBYTE pbyMacRegs);
1090
1091BOOL MACbIsRegBitsOn(DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits);
1092BOOL MACbIsRegBitsOff(DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits);
1093
1094BOOL MACbIsIntDisable(DWORD_PTR dwIoBase);
1095
1096BYTE MACbyReadMultiAddr(DWORD_PTR dwIoBase, UINT uByteIdx);
1097VOID MACvWriteMultiAddr(DWORD_PTR dwIoBase, UINT uByteIdx, BYTE byData);
1098VOID MACvSetMultiAddrByHash(DWORD_PTR dwIoBase, BYTE byHashIdx);
1099VOID MACvResetMultiAddrByHash(DWORD_PTR dwIoBase, BYTE byHashIdx);
1100
1101VOID MACvSetRxThreshold(DWORD_PTR dwIoBase, BYTE byThreshold);
1102VOID MACvGetRxThreshold(DWORD_PTR dwIoBase, PBYTE pbyThreshold);
1103
1104VOID MACvSetTxThreshold(DWORD_PTR dwIoBase, BYTE byThreshold);
1105VOID MACvGetTxThreshold(DWORD_PTR dwIoBase, PBYTE pbyThreshold);
1106
1107VOID MACvSetDmaLength(DWORD_PTR dwIoBase, BYTE byDmaLength);
1108VOID MACvGetDmaLength(DWORD_PTR dwIoBase, PBYTE pbyDmaLength);
1109
1110VOID MACvSetShortRetryLimit(DWORD_PTR dwIoBase, BYTE byRetryLimit);
1111VOID MACvGetShortRetryLimit(DWORD_PTR dwIoBase, PBYTE pbyRetryLimit);
1112
1113VOID MACvSetLongRetryLimit(DWORD_PTR dwIoBase, BYTE byRetryLimit);
1114VOID MACvGetLongRetryLimit(DWORD_PTR dwIoBase, PBYTE pbyRetryLimit);
1115
1116VOID MACvSetLoopbackMode(DWORD_PTR dwIoBase, BYTE byLoopbackMode);
1117BOOL MACbIsInLoopbackMode(DWORD_PTR dwIoBase);
1118
1119VOID MACvSetPacketFilter(DWORD_PTR dwIoBase, WORD wFilterType);
1120
1121VOID MACvSaveContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1122VOID MACvRestoreContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1123BOOL MACbCompareContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1124
1125BOOL MACbSoftwareReset(DWORD_PTR dwIoBase);
1126BOOL MACbSafeSoftwareReset(DWORD_PTR dwIoBase);
1127BOOL MACbSafeRxOff(DWORD_PTR dwIoBase);
1128BOOL MACbSafeTxOff(DWORD_PTR dwIoBase);
1129BOOL MACbSafeStop(DWORD_PTR dwIoBase);
1130BOOL MACbShutdown(DWORD_PTR dwIoBase);
1131VOID MACvInitialize(DWORD_PTR dwIoBase);
1132VOID MACvSetCurrRx0DescAddr(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1133VOID MACvSetCurrRx1DescAddr(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1134VOID MACvSetCurrTXDescAddr(int iTxType, DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1135VOID MACvSetCurrTx0DescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1136VOID MACvSetCurrAC0DescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1137VOID MACvSetCurrSyncDescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1138VOID MACvSetCurrATIMDescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1139void MACvTimer0MicroSDelay(DWORD_PTR dwIoBase, UINT uDelay);
1140void MACvOneShotTimer0MicroSec(DWORD_PTR dwIoBase, UINT uDelayTime);
1141void MACvOneShotTimer1MicroSec(DWORD_PTR dwIoBase, UINT uDelayTime);
1142
1143void MACvSetMISCFifo(DWORD_PTR dwIoBase, WORD wOffset, DWORD dwData);
1144
1145BOOL MACbTxDMAOff (DWORD_PTR dwIoBase, UINT idx);
1146
1147void MACvClearBusSusInd(DWORD_PTR dwIoBase);
1148void MACvEnableBusSusEn(DWORD_PTR dwIoBase);
1149
1150BOOL MACbFlushSYNCFifo(DWORD_PTR dwIoBase);
1151BOOL MACbPSWakeup(DWORD_PTR dwIoBase);
1152
1153void MACvSetKeyEntry(DWORD_PTR dwIoBase, WORD wKeyCtl, UINT uEntryIdx, UINT uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey, BYTE byLocalID);
1154void MACvDisableKeyEntry(DWORD_PTR dwIoBase, UINT uEntryIdx);
1155void MACvSetDefaultKeyEntry(DWORD_PTR dwIoBase, UINT uKeyLen, UINT uKeyIdx, PDWORD pdwKey, BYTE byLocalID);
1156//void MACvEnableDefaultKey(DWORD_PTR dwIoBase, BYTE byLocalID);
1157void MACvDisableDefaultKey(DWORD_PTR dwIoBase);
1158void MACvSetDefaultTKIPKeyEntry(DWORD_PTR dwIoBase, UINT uKeyLen, UINT uKeyIdx, PDWORD pdwKey, BYTE byLocalID);
1159void MACvSetDefaultKeyCtl(DWORD_PTR dwIoBase, WORD wKeyCtl, UINT uEntryIdx, BYTE byLocalID);
1160
1161#ifdef __cplusplus
1162} /* End of extern "C" { */
1163#endif /* __cplusplus */
1164
1165#endif // __MAC_H__
1166