blob: 3d9d746b221ae0669fc01b1020ce0716c4f73a97 [file] [log] [blame]
Paul Walmsley734f69a2010-01-26 20:13:06 -07001/*
2 * OMAP2xxx DVFS virtual clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * XXX Some of this code should be replaceable by the upcoming OPP layer
19 * code. However, some notion of "rate set" is probably still necessary
20 * for OMAP2xxx at least. Rate sets should be generalized so they can be
21 * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
22 * has in the past expressed a preference to use rate sets for OPP changes,
23 * rather than dynamically recalculating the clock tree, so if someone wants
24 * this badly enough to write the code to handle it, we should support it
25 * as an option.
26 */
27#undef DEBUG
28
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/cpufreq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Paul Walmsley734f69a2010-01-26 20:13:06 -070035
Tony Lindgren2c799ce2012-02-24 10:34:35 -080036#include <plat/cpu.h>
Paul Walmsley734f69a2010-01-26 20:13:06 -070037#include <plat/clock.h>
38#include <plat/sram.h>
39#include <plat/sdrc.h>
40
41#include "clock.h"
42#include "clock2xxx.h"
43#include "opp2xxx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070044#include "cm2xxx_3xxx.h"
Paul Walmsley734f69a2010-01-26 20:13:06 -070045#include "cm-regbits-24xx.h"
46
47const struct prcm_config *curr_prcm_set;
48const struct prcm_config *rate_table;
49
50/**
51 * omap2_table_mpu_recalc - just return the MPU speed
52 * @clk: virt_prcm_set struct clk
53 *
54 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
55 */
56unsigned long omap2_table_mpu_recalc(struct clk *clk)
57{
58 return curr_prcm_set->mpu_speed;
59}
60
61/*
62 * Look for a rate equal or less than the target rate given a configuration set.
63 *
64 * What's not entirely clear is "which" field represents the key field.
65 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
66 * just uses the ARM rates.
67 */
68long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
69{
70 const struct prcm_config *ptr;
71 long highest_rate;
Paul Walmsley734f69a2010-01-26 20:13:06 -070072
73 highest_rate = -EINVAL;
74
75 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
76 if (!(ptr->flags & cpu_mask))
77 continue;
Paul Walmsley59dd7222010-05-18 20:24:06 -060078 if (ptr->xtal_speed != sclk->rate)
Paul Walmsley734f69a2010-01-26 20:13:06 -070079 continue;
80
81 highest_rate = ptr->mpu_speed;
82
83 /* Can check only after xtal frequency check */
84 if (ptr->mpu_speed <= rate)
85 break;
86 }
87 return highest_rate;
88}
89
90/* Sets basic clocks based on the specified rate */
91int omap2_select_table_rate(struct clk *clk, unsigned long rate)
92{
93 u32 cur_rate, done_rate, bypass = 0, tmp;
94 const struct prcm_config *prcm;
95 unsigned long found_speed = 0;
96 unsigned long flags;
Paul Walmsley734f69a2010-01-26 20:13:06 -070097
98 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
99 if (!(prcm->flags & cpu_mask))
100 continue;
101
Paul Walmsley59dd7222010-05-18 20:24:06 -0600102 if (prcm->xtal_speed != sclk->rate)
Paul Walmsley734f69a2010-01-26 20:13:06 -0700103 continue;
104
105 if (prcm->mpu_speed <= rate) {
106 found_speed = prcm->mpu_speed;
107 break;
108 }
109 }
110
111 if (!found_speed) {
112 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
113 rate / 1000000);
114 return -EINVAL;
115 }
116
117 curr_prcm_set = prcm;
118 cur_rate = omap2xxx_clk_get_core_rate(dclk);
119
120 if (prcm->dpll_speed == cur_rate / 2) {
121 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
122 } else if (prcm->dpll_speed == cur_rate * 2) {
123 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
124 } else if (prcm->dpll_speed != cur_rate) {
125 local_irq_save(flags);
126
127 if (prcm->dpll_speed == prcm->xtal_speed)
128 bypass = 1;
129
130 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
131 CORE_CLK_SRC_DPLL_X2)
132 done_rate = CORE_CLK_SRC_DPLL_X2;
133 else
134 done_rate = CORE_CLK_SRC_DPLL;
135
136 /* MPU divider */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700137 omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
Paul Walmsley734f69a2010-01-26 20:13:06 -0700138
139 /* dsp + iva1 div(2420), iva2.1(2430) */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700140 omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
Paul Walmsley734f69a2010-01-26 20:13:06 -0700141 OMAP24XX_DSP_MOD, CM_CLKSEL);
142
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700143 omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
Paul Walmsley734f69a2010-01-26 20:13:06 -0700144
145 /* Major subsystem dividers */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700146 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
147 omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
Paul Walmsley734f69a2010-01-26 20:13:06 -0700148 CM_CLKSEL1);
149
150 if (cpu_is_omap2430())
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700151 omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
Paul Walmsley734f69a2010-01-26 20:13:06 -0700152 OMAP2430_MDM_MOD, CM_CLKSEL);
153
154 /* x2 to enter omap2xxx_sdrc_init_params() */
155 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
156
157 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
158 bypass);
159
160 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
161 omap2xxx_sdrc_reprogram(done_rate, 0);
162
163 local_irq_restore(flags);
164 }
165
166 return 0;
167}