Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/irq.c |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * Interrupt handler for OMAP2 boards. |
| 5 | * |
| 6 | * Copyright (C) 2005 Nokia Corporation |
| 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
| 13 | #include <linux/kernel.h> |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 14 | #include <linux/module.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 15 | #include <linux/init.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 16 | #include <linux/interrupt.h> |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 17 | #include <linux/io.h> |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 18 | |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 19 | #include <asm/exception.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 20 | #include <asm/mach/irq.h> |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 21 | #include <linux/irqdomain.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_address.h> |
R Sricharan | c4082d4 | 2012-06-05 16:31:06 +0530 | [diff] [blame] | 24 | #include <linux/of_irq.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 25 | |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 26 | #include <mach/hardware.h> |
| 27 | |
| 28 | #include "iomap.h" |
Paul Walmsley | e2ed89f | 2012-04-13 06:34:26 -0600 | [diff] [blame] | 29 | #include "common.h" |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 30 | |
| 31 | /* selected INTC register offsets */ |
| 32 | |
| 33 | #define INTC_REVISION 0x0000 |
| 34 | #define INTC_SYSCONFIG 0x0010 |
| 35 | #define INTC_SYSSTATUS 0x0014 |
Tony Lindgren | 6ccc4c0 | 2008-12-10 17:36:52 -0800 | [diff] [blame] | 36 | #define INTC_SIR 0x0040 |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 37 | #define INTC_CONTROL 0x0048 |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 38 | #define INTC_PROTECTION 0x004C |
| 39 | #define INTC_IDLE 0x0050 |
| 40 | #define INTC_THRESHOLD 0x0068 |
| 41 | #define INTC_MIR0 0x0084 |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 42 | #define INTC_MIR_CLEAR0 0x0088 |
| 43 | #define INTC_MIR_SET0 0x008c |
| 44 | #define INTC_PENDING_IRQ0 0x0098 |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 45 | /* Number of IRQ state bits in each MIR register */ |
| 46 | #define IRQ_BITS_PER_REG 32 |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 47 | |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 48 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) |
| 49 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) |
| 50 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ |
| 51 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
Tony Lindgren | 3003ce3 | 2012-09-04 17:43:29 -0700 | [diff] [blame] | 52 | #define INTCPS_NR_MIR_REGS 3 |
| 53 | #define INTCPS_NR_IRQS 96 |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 54 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 55 | /* |
| 56 | * OMAP2 has a number of different interrupt controllers, each interrupt |
| 57 | * controller is identified as its own "bank". Register definitions are |
| 58 | * fairly consistent for each bank, but not all registers are implemented |
| 59 | * for each bank.. when in doubt, consult the TRM. |
| 60 | */ |
| 61 | static struct omap_irq_bank { |
Russell King | e8a91c9 | 2008-09-01 22:07:37 +0100 | [diff] [blame] | 62 | void __iomem *base_reg; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 63 | unsigned int nr_irqs; |
| 64 | } __attribute__ ((aligned(4))) irq_banks[] = { |
| 65 | { |
| 66 | /* MPU INTC */ |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 67 | .nr_irqs = 96, |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 68 | }, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 69 | }; |
| 70 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 71 | static struct irq_domain *domain; |
| 72 | |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 73 | /* Structure to save interrupt controller context */ |
| 74 | struct omap3_intc_regs { |
| 75 | u32 sysconfig; |
| 76 | u32 protection; |
| 77 | u32 idle; |
| 78 | u32 threshold; |
| 79 | u32 ilr[INTCPS_NR_IRQS]; |
| 80 | u32 mir[INTCPS_NR_MIR_REGS]; |
| 81 | }; |
| 82 | |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 83 | /* INTC bank register get/set */ |
| 84 | |
| 85 | static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) |
| 86 | { |
| 87 | __raw_writel(val, bank->base_reg + reg); |
| 88 | } |
| 89 | |
| 90 | static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) |
| 91 | { |
| 92 | return __raw_readl(bank->base_reg + reg); |
| 93 | } |
| 94 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 95 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 96 | static void omap_ack_irq(struct irq_data *d) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 97 | { |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 98 | intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 101 | static void omap_mask_ack_irq(struct irq_data *d) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 102 | { |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 103 | irq_gc_mask_disable_reg(d); |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 104 | omap_ack_irq(d); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 105 | } |
| 106 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 107 | static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) |
| 108 | { |
| 109 | unsigned long tmp; |
| 110 | |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 111 | tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; |
Russell King | e8a91c9 | 2008-09-01 22:07:37 +0100 | [diff] [blame] | 112 | printk(KERN_INFO "IRQ: Found an INTC at 0x%p " |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 113 | "(revision %ld.%ld) with %d interrupts\n", |
| 114 | bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); |
| 115 | |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 116 | tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 117 | tmp |= 1 << 1; /* soft reset */ |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 118 | intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 119 | |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 120 | while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 121 | /* Wait for reset to complete */; |
Juha Yrjola | 375e12a | 2006-12-06 17:13:50 -0800 | [diff] [blame] | 122 | |
| 123 | /* Enable autoidle */ |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 124 | intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 125 | } |
| 126 | |
Jouni Hogander | 9443453 | 2009-02-03 15:49:04 -0800 | [diff] [blame] | 127 | int omap_irq_pending(void) |
| 128 | { |
| 129 | int i; |
| 130 | |
| 131 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { |
| 132 | struct omap_irq_bank *bank = irq_banks + i; |
| 133 | int irq; |
| 134 | |
| 135 | for (irq = 0; irq < bank->nr_irqs; irq += 32) |
| 136 | if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 + |
| 137 | ((irq >> 5) << 5))) |
| 138 | return 1; |
| 139 | } |
| 140 | return 0; |
| 141 | } |
| 142 | |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 143 | static __init void |
| 144 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) |
| 145 | { |
| 146 | struct irq_chip_generic *gc; |
| 147 | struct irq_chip_type *ct; |
| 148 | |
| 149 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, |
| 150 | handle_level_irq); |
| 151 | ct = gc->chip_types; |
| 152 | ct->chip.irq_ack = omap_mask_ack_irq; |
| 153 | ct->chip.irq_mask = irq_gc_mask_disable_reg; |
| 154 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
NeilBrown | e3c83c2 | 2012-04-25 13:05:24 +1000 | [diff] [blame] | 155 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 156 | |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 157 | ct->regs.enable = INTC_MIR_CLEAR0; |
| 158 | ct->regs.disable = INTC_MIR_SET0; |
| 159 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
| 160 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
| 161 | } |
| 162 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 163 | static void __init omap_init_irq(u32 base, int nr_irqs, |
| 164 | struct device_node *node) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 165 | { |
Marc Zyngier | ab65be2 | 2011-11-15 17:22:45 +0000 | [diff] [blame] | 166 | void __iomem *omap_irq_base; |
Thomas Gleixner | 4b1135a | 2008-10-16 15:33:18 +0200 | [diff] [blame] | 167 | unsigned long nr_of_irqs = 0; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 168 | unsigned int nr_banks = 0; |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 169 | int i, j, irq_base; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 170 | |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 171 | omap_irq_base = ioremap(base, SZ_4K); |
| 172 | if (WARN_ON(!omap_irq_base)) |
| 173 | return; |
| 174 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 175 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
| 176 | if (irq_base < 0) { |
| 177 | pr_warn("Couldn't allocate IRQ numbers\n"); |
| 178 | irq_base = 0; |
| 179 | } |
| 180 | |
| 181 | domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, |
| 182 | &irq_domain_simple_ops, NULL); |
| 183 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 184 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { |
| 185 | struct omap_irq_bank *bank = irq_banks + i; |
| 186 | |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 187 | bank->nr_irqs = nr_irqs; |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 188 | |
Tony Lindgren | 1b26fe8 | 2009-10-19 15:25:13 -0700 | [diff] [blame] | 189 | /* Static mapping, never released */ |
| 190 | bank->base_reg = ioremap(base, SZ_4K); |
| 191 | if (!bank->base_reg) { |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 192 | pr_err("Could not ioremap irq bank%i\n", i); |
Tony Lindgren | 1b26fe8 | 2009-10-19 15:25:13 -0700 | [diff] [blame] | 193 | continue; |
| 194 | } |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 195 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 196 | omap_irq_bank_init_one(bank); |
| 197 | |
Tapani Utriainen | 5c30cdf | 2011-09-30 11:05:56 -0700 | [diff] [blame] | 198 | for (j = 0; j < bank->nr_irqs; j += 32) |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 199 | omap_alloc_gc(bank->base_reg + j, j + irq_base, 32); |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 200 | |
Thomas Gleixner | 4b1135a | 2008-10-16 15:33:18 +0200 | [diff] [blame] | 201 | nr_of_irqs += bank->nr_irqs; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 202 | nr_banks++; |
| 203 | } |
| 204 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 205 | pr_info("Total of %ld interrupts on %d active controller%s\n", |
| 206 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 207 | } |
| 208 | |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 209 | void __init omap2_init_irq(void) |
| 210 | { |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 211 | omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | void __init omap3_init_irq(void) |
| 215 | { |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 216 | omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 217 | } |
| 218 | |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 219 | void __init ti81xx_init_irq(void) |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 220 | { |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 221 | omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 222 | } |
| 223 | |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 224 | static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) |
| 225 | { |
| 226 | u32 irqnr; |
| 227 | |
| 228 | do { |
| 229 | irqnr = readl_relaxed(base_addr + 0x98); |
| 230 | if (irqnr) |
| 231 | goto out; |
| 232 | |
| 233 | irqnr = readl_relaxed(base_addr + 0xb8); |
| 234 | if (irqnr) |
| 235 | goto out; |
| 236 | |
| 237 | irqnr = readl_relaxed(base_addr + 0xd8); |
Kevin Hilman | 3395955 | 2012-05-10 11:10:07 -0700 | [diff] [blame] | 238 | #ifdef CONFIG_SOC_TI81XX |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 239 | if (irqnr) |
| 240 | goto out; |
| 241 | irqnr = readl_relaxed(base_addr + 0xf8); |
| 242 | #endif |
| 243 | |
| 244 | out: |
| 245 | if (!irqnr) |
| 246 | break; |
| 247 | |
| 248 | irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); |
| 249 | irqnr &= ACTIVEIRQ_MASK; |
| 250 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 251 | if (irqnr) { |
| 252 | irqnr = irq_find_mapping(domain, irqnr); |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 253 | handle_IRQ(irqnr, regs); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 254 | } |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 255 | } while (irqnr); |
| 256 | } |
| 257 | |
| 258 | asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) |
| 259 | { |
| 260 | void __iomem *base_addr = OMAP2_IRQ_BASE; |
| 261 | omap_intc_handle_irq(base_addr, regs); |
| 262 | } |
| 263 | |
R Sricharan | c4082d4 | 2012-06-05 16:31:06 +0530 | [diff] [blame] | 264 | int __init intc_of_init(struct device_node *node, |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 265 | struct device_node *parent) |
| 266 | { |
| 267 | struct resource res; |
Venkatraman S | b56f2cb | 2012-06-25 15:56:39 +0530 | [diff] [blame] | 268 | u32 nr_irq = 96; |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 269 | |
| 270 | if (WARN_ON(!node)) |
| 271 | return -ENODEV; |
| 272 | |
| 273 | if (of_address_to_resource(node, 0, &res)) { |
| 274 | WARN(1, "unable to get intc registers\n"); |
| 275 | return -EINVAL; |
| 276 | } |
| 277 | |
Venkatraman S | b56f2cb | 2012-06-25 15:56:39 +0530 | [diff] [blame] | 278 | if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) |
| 279 | pr_warn("unable to get intc-size, default to %d\n", nr_irq); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 280 | |
Venkatraman S | b56f2cb | 2012-06-25 15:56:39 +0530 | [diff] [blame] | 281 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
R Sricharan | c4082d4 | 2012-06-05 16:31:06 +0530 | [diff] [blame] | 286 | static struct of_device_id irq_match[] __initdata = { |
| 287 | { .compatible = "ti,omap2-intc", .data = intc_of_init, }, |
| 288 | { } |
| 289 | }; |
| 290 | |
| 291 | void __init omap_intc_of_init(void) |
| 292 | { |
| 293 | of_irq_init(irq_match); |
| 294 | } |
| 295 | |
Afzal Mohammed | 08f3098 | 2012-05-11 00:38:49 +0530 | [diff] [blame] | 296 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
Felipe Balbi | ee23b93 | 2011-01-27 16:39:43 -0800 | [diff] [blame] | 297 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; |
| 298 | |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 299 | void omap_intc_save_context(void) |
| 300 | { |
| 301 | int ind = 0, i = 0; |
| 302 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { |
| 303 | struct omap_irq_bank *bank = irq_banks + ind; |
| 304 | intc_context[ind].sysconfig = |
| 305 | intc_bank_read_reg(bank, INTC_SYSCONFIG); |
| 306 | intc_context[ind].protection = |
| 307 | intc_bank_read_reg(bank, INTC_PROTECTION); |
| 308 | intc_context[ind].idle = |
| 309 | intc_bank_read_reg(bank, INTC_IDLE); |
| 310 | intc_context[ind].threshold = |
| 311 | intc_bank_read_reg(bank, INTC_THRESHOLD); |
| 312 | for (i = 0; i < INTCPS_NR_IRQS; i++) |
| 313 | intc_context[ind].ilr[i] = |
Aaro Koskinen | 2329e7c | 2009-03-12 18:12:29 +0200 | [diff] [blame] | 314 | intc_bank_read_reg(bank, (0x100 + 0x4*i)); |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 315 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
| 316 | intc_context[ind].mir[i] = |
| 317 | intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + |
| 318 | (0x20 * i)); |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | void omap_intc_restore_context(void) |
| 323 | { |
| 324 | int ind = 0, i = 0; |
| 325 | |
| 326 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { |
| 327 | struct omap_irq_bank *bank = irq_banks + ind; |
| 328 | intc_bank_write_reg(intc_context[ind].sysconfig, |
| 329 | bank, INTC_SYSCONFIG); |
| 330 | intc_bank_write_reg(intc_context[ind].sysconfig, |
| 331 | bank, INTC_SYSCONFIG); |
| 332 | intc_bank_write_reg(intc_context[ind].protection, |
| 333 | bank, INTC_PROTECTION); |
| 334 | intc_bank_write_reg(intc_context[ind].idle, |
| 335 | bank, INTC_IDLE); |
| 336 | intc_bank_write_reg(intc_context[ind].threshold, |
| 337 | bank, INTC_THRESHOLD); |
| 338 | for (i = 0; i < INTCPS_NR_IRQS; i++) |
| 339 | intc_bank_write_reg(intc_context[ind].ilr[i], |
Aaro Koskinen | 2329e7c | 2009-03-12 18:12:29 +0200 | [diff] [blame] | 340 | bank, (0x100 + 0x4*i)); |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 341 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
| 342 | intc_bank_write_reg(intc_context[ind].mir[i], |
| 343 | &irq_banks[0], INTC_MIR0 + (0x20 * i)); |
| 344 | } |
| 345 | /* MIRs are saved and restore with other PRCM registers */ |
| 346 | } |
Tero Kristo | 2bbe3af | 2009-10-23 19:03:48 +0300 | [diff] [blame] | 347 | |
| 348 | void omap3_intc_suspend(void) |
| 349 | { |
| 350 | /* A pending interrupt would prevent OMAP from entering suspend */ |
Paul Walmsley | a7022d6 | 2012-04-13 06:34:28 -0600 | [diff] [blame] | 351 | omap_ack_irq(NULL); |
Tero Kristo | 2bbe3af | 2009-10-23 19:03:48 +0300 | [diff] [blame] | 352 | } |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 353 | |
| 354 | void omap3_intc_prepare_idle(void) |
| 355 | { |
Jean Pihet | 447b8da | 2010-11-17 17:52:11 +0000 | [diff] [blame] | 356 | /* |
| 357 | * Disable autoidle as it can stall interrupt controller, |
| 358 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) |
| 359 | */ |
Tero Kristo | f18cc2f | 2009-10-23 19:03:50 +0300 | [diff] [blame] | 360 | intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); |
| 361 | } |
| 362 | |
| 363 | void omap3_intc_resume_idle(void) |
| 364 | { |
| 365 | /* Re-enable autoidle */ |
| 366 | intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG); |
| 367 | } |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 368 | |
| 369 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) |
| 370 | { |
| 371 | void __iomem *base_addr = OMAP3_IRQ_BASE; |
| 372 | omap_intc_handle_irq(base_addr, regs); |
| 373 | } |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 374 | #endif /* CONFIG_ARCH_OMAP3 */ |