blob: 257e2d427cabfdeb0e02857dda0c24f62a0e86de [file] [log] [blame]
Ido Schimmelf00817d2016-04-06 17:10:09 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum_dcb.c
3 * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2016 Ido Schimmel <idosch@mellanox.com>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/netdevice.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020036#include <linux/string.h>
Ido Schimmelf00817d2016-04-06 17:10:09 +020037#include <net/dcbnl.h>
38
39#include "spectrum.h"
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020040#include "reg.h"
Ido Schimmelf00817d2016-04-06 17:10:09 +020041
42static u8 mlxsw_sp_dcbnl_getdcbx(struct net_device __always_unused *dev)
43{
44 return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
45}
46
47static u8 mlxsw_sp_dcbnl_setdcbx(struct net_device __always_unused *dev,
48 u8 mode)
49{
50 return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
51}
52
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020053static int mlxsw_sp_dcbnl_ieee_getets(struct net_device *dev,
54 struct ieee_ets *ets)
55{
56 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
57
58 memcpy(ets, mlxsw_sp_port->dcb.ets, sizeof(*ets));
59
60 return 0;
61}
62
63static int mlxsw_sp_port_ets_validate(struct mlxsw_sp_port *mlxsw_sp_port,
64 struct ieee_ets *ets)
65{
66 struct net_device *dev = mlxsw_sp_port->dev;
67 bool has_ets_tc = false;
68 int i, tx_bw_sum = 0;
69
70 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
71 switch (ets->tc_tsa[i]) {
72 case IEEE_8021QAZ_TSA_STRICT:
73 break;
74 case IEEE_8021QAZ_TSA_ETS:
75 has_ets_tc = true;
76 tx_bw_sum += ets->tc_tx_bw[i];
77 break;
78 default:
79 netdev_err(dev, "Only strict priority and ETS are supported\n");
80 return -EINVAL;
81 }
82
83 if (ets->prio_tc[i] >= IEEE_8021QAZ_MAX_TCS) {
84 netdev_err(dev, "Invalid TC\n");
85 return -EINVAL;
86 }
87 }
88
89 if (has_ets_tc && tx_bw_sum != 100) {
90 netdev_err(dev, "Total ETS bandwidth should equal 100\n");
91 return -EINVAL;
92 }
93
94 return 0;
95}
96
97static int mlxsw_sp_port_pg_prio_map(struct mlxsw_sp_port *mlxsw_sp_port,
98 u8 *prio_tc)
99{
100 char pptb_pl[MLXSW_REG_PPTB_LEN];
101 int i;
102
103 mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
104 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
105 mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, prio_tc[i]);
106 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
107 pptb_pl);
108}
109
110static bool mlxsw_sp_ets_has_pg(u8 *prio_tc, u8 pg)
111{
112 int i;
113
114 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
115 if (prio_tc[i] == pg)
116 return true;
117 return false;
118}
119
120static int mlxsw_sp_port_pg_destroy(struct mlxsw_sp_port *mlxsw_sp_port,
121 u8 *old_prio_tc, u8 *new_prio_tc)
122{
123 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
124 char pbmc_pl[MLXSW_REG_PBMC_LEN];
125 int err, i;
126
127 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
128 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
129 if (err)
130 return err;
131
132 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
133 u8 pg = old_prio_tc[i];
134
135 if (!mlxsw_sp_ets_has_pg(new_prio_tc, pg))
136 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg, 0);
137 }
138
139 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
140}
141
142static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
143 struct ieee_ets *ets)
144{
145 struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
146 struct net_device *dev = mlxsw_sp_port->dev;
147 int err;
148
149 /* Create the required PGs, but don't destroy existing ones, as
150 * traffic is still directed to them.
151 */
152 err = __mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu,
153 ets->prio_tc);
154 if (err) {
155 netdev_err(dev, "Failed to configure port's headroom\n");
156 return err;
157 }
158
159 err = mlxsw_sp_port_pg_prio_map(mlxsw_sp_port, ets->prio_tc);
160 if (err) {
161 netdev_err(dev, "Failed to set PG-priority mapping\n");
162 goto err_port_prio_pg_map;
163 }
164
165 err = mlxsw_sp_port_pg_destroy(mlxsw_sp_port, my_ets->prio_tc,
166 ets->prio_tc);
167 if (err)
168 netdev_warn(dev, "Failed to remove ununsed PGs\n");
169
170 return 0;
171
172err_port_prio_pg_map:
173 mlxsw_sp_port_pg_destroy(mlxsw_sp_port, ets->prio_tc, my_ets->prio_tc);
174 return err;
175}
176
177static int __mlxsw_sp_dcbnl_ieee_setets(struct mlxsw_sp_port *mlxsw_sp_port,
178 struct ieee_ets *ets)
179{
180 struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
181 struct net_device *dev = mlxsw_sp_port->dev;
182 int i, err;
183
184 /* Egress configuration. */
185 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
186 bool dwrr = ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
187 u8 weight = ets->tc_tx_bw[i];
188
189 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
190 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
191 0, dwrr, weight);
192 if (err) {
193 netdev_err(dev, "Failed to link subgroup ETS element %d to group\n",
194 i);
195 goto err_port_ets_set;
196 }
197 }
198
199 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
200 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i,
201 ets->prio_tc[i]);
202 if (err) {
203 netdev_err(dev, "Failed to map prio %d to TC %d\n", i,
204 ets->prio_tc[i]);
205 goto err_port_prio_tc_set;
206 }
207 }
208
209 /* Ingress configuration. */
210 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, ets);
211 if (err)
212 goto err_port_headroom_set;
213
214 return 0;
215
216err_port_headroom_set:
217 i = IEEE_8021QAZ_MAX_TCS;
218err_port_prio_tc_set:
219 for (i--; i >= 0; i--)
220 mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, my_ets->prio_tc[i]);
221 i = IEEE_8021QAZ_MAX_TCS;
222err_port_ets_set:
223 for (i--; i >= 0; i--) {
224 bool dwrr = my_ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
225 u8 weight = my_ets->tc_tx_bw[i];
226
227 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
228 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
229 0, dwrr, weight);
230 }
231 return err;
232}
233
234static int mlxsw_sp_dcbnl_ieee_setets(struct net_device *dev,
235 struct ieee_ets *ets)
236{
237 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
238 int err;
239
240 err = mlxsw_sp_port_ets_validate(mlxsw_sp_port, ets);
241 if (err)
242 return err;
243
244 err = __mlxsw_sp_dcbnl_ieee_setets(mlxsw_sp_port, ets);
245 if (err)
246 return err;
247
248 memcpy(mlxsw_sp_port->dcb.ets, ets, sizeof(*ets));
249
250 return 0;
251}
252
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200253static int mlxsw_sp_dcbnl_ieee_getmaxrate(struct net_device *dev,
254 struct ieee_maxrate *maxrate)
255{
256 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
257
258 memcpy(maxrate, mlxsw_sp_port->dcb.maxrate, sizeof(*maxrate));
259
260 return 0;
261}
262
263static int mlxsw_sp_dcbnl_ieee_setmaxrate(struct net_device *dev,
264 struct ieee_maxrate *maxrate)
265{
266 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
267 struct ieee_maxrate *my_maxrate = mlxsw_sp_port->dcb.maxrate;
268 int err, i;
269
270 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
271 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
272 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
273 i, 0,
274 maxrate->tc_maxrate[i]);
275 if (err) {
276 netdev_err(dev, "Failed to set maxrate for TC %d\n", i);
277 goto err_port_ets_maxrate_set;
278 }
279 }
280
281 memcpy(mlxsw_sp_port->dcb.maxrate, maxrate, sizeof(*maxrate));
282
283 return 0;
284
285err_port_ets_maxrate_set:
286 for (i--; i >= 0; i--)
287 mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
288 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
289 i, 0, my_maxrate->tc_maxrate[i]);
290 return err;
291}
292
Ido Schimmelf00817d2016-04-06 17:10:09 +0200293static const struct dcbnl_rtnl_ops mlxsw_sp_dcbnl_ops = {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200294 .ieee_getets = mlxsw_sp_dcbnl_ieee_getets,
295 .ieee_setets = mlxsw_sp_dcbnl_ieee_setets,
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200296 .ieee_getmaxrate = mlxsw_sp_dcbnl_ieee_getmaxrate,
297 .ieee_setmaxrate = mlxsw_sp_dcbnl_ieee_setmaxrate,
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200298
Ido Schimmelf00817d2016-04-06 17:10:09 +0200299 .getdcbx = mlxsw_sp_dcbnl_getdcbx,
300 .setdcbx = mlxsw_sp_dcbnl_setdcbx,
301};
302
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200303static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
304{
305 mlxsw_sp_port->dcb.ets = kzalloc(sizeof(*mlxsw_sp_port->dcb.ets),
306 GFP_KERNEL);
307 if (!mlxsw_sp_port->dcb.ets)
308 return -ENOMEM;
309
310 mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
311
312 return 0;
313}
314
315static void mlxsw_sp_port_ets_fini(struct mlxsw_sp_port *mlxsw_sp_port)
316{
317 kfree(mlxsw_sp_port->dcb.ets);
318}
319
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200320static int mlxsw_sp_port_maxrate_init(struct mlxsw_sp_port *mlxsw_sp_port)
321{
322 int i;
323
324 mlxsw_sp_port->dcb.maxrate = kmalloc(sizeof(*mlxsw_sp_port->dcb.maxrate),
325 GFP_KERNEL);
326 if (!mlxsw_sp_port->dcb.maxrate)
327 return -ENOMEM;
328
329 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
330 mlxsw_sp_port->dcb.maxrate->tc_maxrate[i] = MLXSW_REG_QEEC_MAS_DIS;
331
332 return 0;
333}
334
335static void mlxsw_sp_port_maxrate_fini(struct mlxsw_sp_port *mlxsw_sp_port)
336{
337 kfree(mlxsw_sp_port->dcb.maxrate);
338}
339
Ido Schimmelf00817d2016-04-06 17:10:09 +0200340int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
341{
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200342 int err;
343
344 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
345 if (err)
346 return err;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200347 err = mlxsw_sp_port_maxrate_init(mlxsw_sp_port);
348 if (err)
349 goto err_port_maxrate_init;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200350
Ido Schimmelf00817d2016-04-06 17:10:09 +0200351 mlxsw_sp_port->dev->dcbnl_ops = &mlxsw_sp_dcbnl_ops;
352
353 return 0;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200354
355err_port_maxrate_init:
356 mlxsw_sp_port_ets_fini(mlxsw_sp_port);
357 return err;
Ido Schimmelf00817d2016-04-06 17:10:09 +0200358}
359
360void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
361{
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200362 mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200363 mlxsw_sp_port_ets_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +0200364}