Donguk Ryu | ccbc876 | 2011-01-13 13:40:29 +0900 | [diff] [blame^] | 1 | /* linux/arch/arm/mach-s5pv310/dev-sysmmu.c |
| 2 | * |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/dma-mapping.h> |
| 13 | |
| 14 | #include <mach/map.h> |
| 15 | #include <mach/irqs.h> |
| 16 | |
| 17 | static struct resource s5pv310_sysmmu_resource[] = { |
| 18 | [0] = { |
| 19 | .start = S5PV310_PA_SYSMMU_MDMA, |
| 20 | .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, |
| 21 | .flags = IORESOURCE_MEM, |
| 22 | }, |
| 23 | [1] = { |
| 24 | .start = IRQ_SYSMMU_MDMA0_0, |
| 25 | .end = IRQ_SYSMMU_MDMA0_0, |
| 26 | .flags = IORESOURCE_IRQ, |
| 27 | }, |
| 28 | [2] = { |
| 29 | .start = S5PV310_PA_SYSMMU_SSS, |
| 30 | .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, |
| 31 | .flags = IORESOURCE_MEM, |
| 32 | }, |
| 33 | [3] = { |
| 34 | .start = IRQ_SYSMMU_SSS_0, |
| 35 | .end = IRQ_SYSMMU_SSS_0, |
| 36 | .flags = IORESOURCE_IRQ, |
| 37 | }, |
| 38 | [4] = { |
| 39 | .start = S5PV310_PA_SYSMMU_FIMC0, |
| 40 | .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, |
| 41 | .flags = IORESOURCE_MEM, |
| 42 | }, |
| 43 | [5] = { |
| 44 | .start = IRQ_SYSMMU_FIMC0_0, |
| 45 | .end = IRQ_SYSMMU_FIMC0_0, |
| 46 | .flags = IORESOURCE_IRQ, |
| 47 | }, |
| 48 | [6] = { |
| 49 | .start = S5PV310_PA_SYSMMU_FIMC1, |
| 50 | .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, |
| 51 | .flags = IORESOURCE_MEM, |
| 52 | }, |
| 53 | [7] = { |
| 54 | .start = IRQ_SYSMMU_FIMC1_0, |
| 55 | .end = IRQ_SYSMMU_FIMC1_0, |
| 56 | .flags = IORESOURCE_IRQ, |
| 57 | }, |
| 58 | [8] = { |
| 59 | .start = S5PV310_PA_SYSMMU_FIMC2, |
| 60 | .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, |
| 61 | .flags = IORESOURCE_MEM, |
| 62 | }, |
| 63 | [9] = { |
| 64 | .start = IRQ_SYSMMU_FIMC2_0, |
| 65 | .end = IRQ_SYSMMU_FIMC2_0, |
| 66 | .flags = IORESOURCE_IRQ, |
| 67 | }, |
| 68 | [10] = { |
| 69 | .start = S5PV310_PA_SYSMMU_FIMC3, |
| 70 | .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, |
| 71 | .flags = IORESOURCE_MEM, |
| 72 | }, |
| 73 | [11] = { |
| 74 | .start = IRQ_SYSMMU_FIMC3_0, |
| 75 | .end = IRQ_SYSMMU_FIMC3_0, |
| 76 | .flags = IORESOURCE_IRQ, |
| 77 | }, |
| 78 | [12] = { |
| 79 | .start = S5PV310_PA_SYSMMU_JPEG, |
| 80 | .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, |
| 81 | .flags = IORESOURCE_MEM, |
| 82 | }, |
| 83 | [13] = { |
| 84 | .start = IRQ_SYSMMU_JPEG_0, |
| 85 | .end = IRQ_SYSMMU_JPEG_0, |
| 86 | .flags = IORESOURCE_IRQ, |
| 87 | }, |
| 88 | [14] = { |
| 89 | .start = S5PV310_PA_SYSMMU_FIMD0, |
| 90 | .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, |
| 91 | .flags = IORESOURCE_MEM, |
| 92 | }, |
| 93 | [15] = { |
| 94 | .start = IRQ_SYSMMU_LCD0_M0_0, |
| 95 | .end = IRQ_SYSMMU_LCD0_M0_0, |
| 96 | .flags = IORESOURCE_IRQ, |
| 97 | }, |
| 98 | [16] = { |
| 99 | .start = S5PV310_PA_SYSMMU_FIMD1, |
| 100 | .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, |
| 101 | .flags = IORESOURCE_MEM, |
| 102 | }, |
| 103 | [17] = { |
| 104 | .start = IRQ_SYSMMU_LCD1_M1_0, |
| 105 | .end = IRQ_SYSMMU_LCD1_M1_0, |
| 106 | .flags = IORESOURCE_IRQ, |
| 107 | }, |
| 108 | [18] = { |
| 109 | .start = S5PV310_PA_SYSMMU_PCIe, |
| 110 | .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, |
| 111 | .flags = IORESOURCE_MEM, |
| 112 | }, |
| 113 | [19] = { |
| 114 | .start = IRQ_SYSMMU_PCIE_0, |
| 115 | .end = IRQ_SYSMMU_PCIE_0, |
| 116 | .flags = IORESOURCE_IRQ, |
| 117 | }, |
| 118 | [20] = { |
| 119 | .start = S5PV310_PA_SYSMMU_G2D, |
| 120 | .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, |
| 121 | .flags = IORESOURCE_MEM, |
| 122 | }, |
| 123 | [21] = { |
| 124 | .start = IRQ_SYSMMU_2D_0, |
| 125 | .end = IRQ_SYSMMU_2D_0, |
| 126 | .flags = IORESOURCE_IRQ, |
| 127 | }, |
| 128 | [22] = { |
| 129 | .start = S5PV310_PA_SYSMMU_ROTATOR, |
| 130 | .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, |
| 131 | .flags = IORESOURCE_MEM, |
| 132 | }, |
| 133 | [23] = { |
| 134 | .start = IRQ_SYSMMU_ROTATOR_0, |
| 135 | .end = IRQ_SYSMMU_ROTATOR_0, |
| 136 | .flags = IORESOURCE_IRQ, |
| 137 | }, |
| 138 | [24] = { |
| 139 | .start = S5PV310_PA_SYSMMU_MDMA2, |
| 140 | .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, |
| 141 | .flags = IORESOURCE_MEM, |
| 142 | }, |
| 143 | [25] = { |
| 144 | .start = IRQ_SYSMMU_MDMA1_0, |
| 145 | .end = IRQ_SYSMMU_MDMA1_0, |
| 146 | .flags = IORESOURCE_IRQ, |
| 147 | }, |
| 148 | [26] = { |
| 149 | .start = S5PV310_PA_SYSMMU_TV, |
| 150 | .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, |
| 151 | .flags = IORESOURCE_MEM, |
| 152 | }, |
| 153 | [27] = { |
| 154 | .start = IRQ_SYSMMU_TV_M0_0, |
| 155 | .end = IRQ_SYSMMU_TV_M0_0, |
| 156 | .flags = IORESOURCE_IRQ, |
| 157 | }, |
| 158 | [28] = { |
| 159 | .start = S5PV310_PA_SYSMMU_MFC_L, |
| 160 | .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, |
| 161 | .flags = IORESOURCE_MEM, |
| 162 | }, |
| 163 | [29] = { |
| 164 | .start = IRQ_SYSMMU_MFC_M0_0, |
| 165 | .end = IRQ_SYSMMU_MFC_M0_0, |
| 166 | .flags = IORESOURCE_IRQ, |
| 167 | }, |
| 168 | [30] = { |
| 169 | .start = S5PV310_PA_SYSMMU_MFC_R, |
| 170 | .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, |
| 171 | .flags = IORESOURCE_MEM, |
| 172 | }, |
| 173 | [31] = { |
| 174 | .start = IRQ_SYSMMU_MFC_M1_0, |
| 175 | .end = IRQ_SYSMMU_MFC_M1_0, |
| 176 | .flags = IORESOURCE_IRQ, |
| 177 | }, |
| 178 | }; |
| 179 | |
| 180 | struct platform_device s5pv310_device_sysmmu = { |
| 181 | .name = "s5p-sysmmu", |
| 182 | .id = 32, |
| 183 | .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), |
| 184 | .resource = s5pv310_sysmmu_resource, |
| 185 | }; |
| 186 | |
| 187 | EXPORT_SYMBOL(s5pv310_device_sysmmu); |