Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can distribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License (Version 2) as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 11 | * for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along |
| 14 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 15 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 16 | * |
| 17 | */ |
| 18 | /* |
| 19 | * Simulator Platform-specific hooks for SMP operation |
| 20 | */ |
| 21 | #include <linux/config.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/sched.h> |
| 24 | #include <linux/cpumask.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <asm/atomic.h> |
| 27 | #include <asm/cpu.h> |
| 28 | #include <asm/processor.h> |
| 29 | #include <asm/system.h> |
| 30 | #include <asm/hardirq.h> |
| 31 | #include <asm/mmu_context.h> |
| 32 | #include <asm/smp.h> |
| 33 | #ifdef CONFIG_MIPS_MT_SMTC |
| 34 | #include <asm/smtc_ipi.h> |
| 35 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 36 | |
| 37 | /* VPE/SMP Prototype implements platform interfaces directly */ |
| 38 | #if !defined(CONFIG_MIPS_MT_SMP) |
| 39 | |
| 40 | /* |
| 41 | * Cause the specified action to be performed on a targeted "CPU" |
| 42 | */ |
| 43 | |
| 44 | void core_send_ipi(int cpu, unsigned int action) |
| 45 | { |
| 46 | #ifdef CONFIG_MIPS_MT_SMTC |
| 47 | void smtc_send_ipi(int, int, unsigned int); |
| 48 | |
| 49 | smtc_send_ipi(cpu, LINUX_SMP_IPI, action); |
| 50 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 51 | /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ |
| 52 | |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map |
| 57 | */ |
| 58 | |
| 59 | void __init prom_build_cpu_map(void) |
| 60 | { |
| 61 | #ifdef CONFIG_MIPS_MT_SMTC |
| 62 | extern int mipsmt_build_cpu_map(int startslot); |
| 63 | int nextslot; |
| 64 | |
| 65 | cpus_clear(phys_cpu_present_map); |
| 66 | |
| 67 | /* Register the boot CPU */ |
| 68 | |
| 69 | smp_prepare_boot_cpu(); |
| 70 | |
| 71 | /* |
| 72 | * As of November, 2004, MIPSsim only simulates one core |
| 73 | * at a time. However, that core may be a MIPS MT core |
| 74 | * with multiple virtual processors and thread contexts. |
| 75 | */ |
| 76 | |
| 77 | if (read_c0_config3() & (1<<2)) { |
| 78 | nextslot = mipsmt_build_cpu_map(1); |
| 79 | } |
| 80 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * Platform "CPU" startup hook |
| 85 | */ |
| 86 | |
| 87 | void prom_boot_secondary(int cpu, struct task_struct *idle) |
| 88 | { |
| 89 | #ifdef CONFIG_MIPS_MT_SMTC |
| 90 | extern void smtc_boot_secondary(int cpu, struct task_struct *t); |
| 91 | |
| 92 | smtc_boot_secondary(cpu, idle); |
| 93 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * Post-config but pre-boot cleanup entry point |
| 98 | */ |
| 99 | |
| 100 | void prom_init_secondary(void) |
| 101 | { |
| 102 | #ifdef CONFIG_MIPS_MT_SMTC |
| 103 | void smtc_init_secondary(void); |
| 104 | |
| 105 | smtc_init_secondary(); |
| 106 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * Platform SMP pre-initialization |
| 111 | */ |
| 112 | |
| 113 | void prom_prepare_cpus(unsigned int max_cpus) |
| 114 | { |
| 115 | #ifdef CONFIG_MIPS_MT_SMTC |
| 116 | void mipsmt_prepare_cpus(int c); |
| 117 | /* |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 118 | * As noted above, we can assume a single CPU for now |
Ralf Baechle | c78cbf4 | 2005-09-30 13:59:37 +0100 | [diff] [blame] | 119 | * but it may be multithreaded. |
| 120 | */ |
| 121 | |
| 122 | if (read_c0_config3() & (1<<2)) { |
| 123 | mipsmt_prepare_cpus(max_cpus); |
| 124 | } |
| 125 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * SMP initialization finalization entry point |
| 130 | */ |
| 131 | |
| 132 | void prom_smp_finish(void) |
| 133 | { |
| 134 | #ifdef CONFIG_MIPS_MT_SMTC |
| 135 | void smtc_smp_finish(void); |
| 136 | |
| 137 | smtc_smp_finish(); |
| 138 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Hook for after all CPUs are online |
| 143 | */ |
| 144 | |
| 145 | void prom_cpus_done(void) |
| 146 | { |
| 147 | #ifdef CONFIG_MIPS_MT_SMTC |
| 148 | |
| 149 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 150 | } |
| 151 | #endif /* CONFIG_MIPS32R2_MT_SMP */ |