| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2002 Momentum Computer Inc. |
| 3 | * Author: Matthew Dharm <mdharm@momenco.com> |
| 4 | * |
| 5 | * Copyright 2001 MontaVista Software Inc. |
| 6 | * Author: jsun@mvista.com or jsun@junsun.net |
| 7 | * |
| 8 | * Copyright 2004 PMC-Sierra |
| 9 | * Author: Manish Lachwani (lachwani@pmc-sierra.com) |
| 10 | * |
| 11 | * Copyright (C) 2004 MontaVista Software Inc. |
| 12 | * Author: Manish Lachwani, mlachwani@mvista.com |
| 13 | * |
| 14 | * First-level interrupt dispatcher for Ocelot-3 board. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify it |
| 17 | * under the terms of the GNU General Public License as published by the |
| 18 | * Free Software Foundation; either version 2 of the License, or (at your |
| 19 | * option) any later version. |
| 20 | */ |
| 21 | #include <asm/asm.h> |
| 22 | #include <asm/mipsregs.h> |
| 23 | #include <asm/addrspace.h> |
| 24 | #include <asm/regdef.h> |
| 25 | #include <asm/stackframe.h> |
| 26 | |
| 27 | /* |
| 28 | * First level interrupt dispatcher for Ocelot-3 board |
| 29 | */ |
| 30 | .align 5 |
| 31 | NESTED(ocelot3_handle_int, PT_SIZE, sp) |
| 32 | SAVE_ALL |
| 33 | CLI |
| 34 | .set at |
| 35 | |
| 36 | mfc0 t0, CP0_CAUSE |
| 37 | mfc0 t2, CP0_STATUS |
| 38 | |
| 39 | and t0, t2 |
| 40 | |
| 41 | andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ |
| 42 | bnez t1, ll_sw0_irq |
| 43 | |
| 44 | andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ |
| 45 | bnez t1, ll_sw1_irq |
| 46 | |
| 47 | andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ |
| 48 | bnez t1, ll_pci0slot1_irq |
| 49 | |
| 50 | andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ |
| 51 | bnez t1, ll_pci0slot2_irq |
| 52 | |
| 53 | andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ |
| 54 | bnez t1, ll_pci1slot1_irq |
| 55 | |
| 56 | andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ |
| 57 | bnez t1, ll_pci1slot2_irq |
| 58 | |
| 59 | andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ |
| 60 | bnez t1, ll_uart_irq |
| 61 | |
| 62 | andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ |
| 63 | bnez t1, ll_cputimer_irq |
| 64 | |
| 65 | /* now look at extended interrupts */ |
| 66 | mfc0 t0, CP0_CAUSE |
| 67 | cfc0 t1, CP0_S1_INTCONTROL |
| 68 | |
| 69 | /* shift the mask 8 bits left to line up the bits */ |
| 70 | sll t2, t1, 8 |
| 71 | |
| 72 | and t0, t2 |
| 73 | srl t0, t0, 16 |
| 74 | |
| 75 | andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ |
| 76 | bnez t1, ll_mv64340_decode_irq |
| 77 | |
| 78 | .set reorder |
| 79 | |
| 80 | /* wrong alarm or masked ... */ |
| 81 | j spurious_interrupt |
| 82 | nop |
| 83 | END(ocelot3_handle_int) |
| 84 | |
| 85 | .align 5 |
| 86 | ll_sw0_irq: |
| 87 | li a0, 0 /* IRQ 1 */ |
| 88 | move a1, sp |
| 89 | jal do_IRQ |
| 90 | j ret_from_irq |
| 91 | ll_sw1_irq: |
| 92 | li a0, 1 /* IRQ 2 */ |
| 93 | move a1, sp |
| 94 | jal do_IRQ |
| 95 | j ret_from_irq |
| 96 | |
| 97 | ll_pci0slot1_irq: |
| 98 | li a0, 2 /* IRQ 3 */ |
| 99 | move a1, sp |
| 100 | jal do_IRQ |
| 101 | j ret_from_irq |
| 102 | |
| 103 | ll_pci0slot2_irq: |
| 104 | li a0, 3 /* IRQ 4 */ |
| 105 | move a1, sp |
| 106 | jal do_IRQ |
| 107 | j ret_from_irq |
| 108 | |
| 109 | ll_pci1slot1_irq: |
| 110 | li a0, 4 /* IRQ 5 */ |
| 111 | move a1, sp |
| 112 | jal do_IRQ |
| 113 | j ret_from_irq |
| 114 | |
| 115 | ll_pci1slot2_irq: |
| 116 | li a0, 5 /* IRQ 6 */ |
| 117 | move a1, sp |
| 118 | jal do_IRQ |
| 119 | j ret_from_irq |
| 120 | |
| 121 | ll_uart_irq: |
| 122 | li a0, 6 /* IRQ 7 */ |
| 123 | move a1, sp |
| 124 | jal do_IRQ |
| 125 | j ret_from_irq |
| 126 | |
| 127 | ll_cputimer_irq: |
| 128 | li a0, 7 /* IRQ 8 */ |
| 129 | move a1, sp |
| 130 | jal do_IRQ |
| 131 | j ret_from_irq |
| 132 | |
| 133 | ll_mv64340_decode_irq: |
| 134 | move a0, sp |
| 135 | jal ll_mv64340_irq |
| 136 | j ret_from_irq |
| 137 | |