Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 1 | /* |
| 2 | * CHRP pci routines. |
| 3 | */ |
| 4 | |
| 5 | #include <linux/config.h> |
| 6 | #include <linux/kernel.h> |
| 7 | #include <linux/pci.h> |
| 8 | #include <linux/delay.h> |
| 9 | #include <linux/string.h> |
| 10 | #include <linux/init.h> |
| 11 | #include <linux/ide.h> |
| 12 | |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/pgtable.h> |
| 15 | #include <asm/irq.h> |
| 16 | #include <asm/hydra.h> |
| 17 | #include <asm/prom.h> |
| 18 | #include <asm/gg2.h> |
| 19 | #include <asm/machdep.h> |
| 20 | #include <asm/sections.h> |
| 21 | #include <asm/pci-bridge.h> |
| 22 | #include <asm/open_pic.h> |
| 23 | #include <asm/grackle.h> |
| 24 | #include <asm/rtas.h> |
| 25 | |
| 26 | /* LongTrail */ |
| 27 | void __iomem *gg2_pci_config_base; |
| 28 | |
| 29 | /* |
| 30 | * The VLSI Golden Gate II has only 512K of PCI configuration space, so we |
| 31 | * limit the bus number to 3 bits |
| 32 | */ |
| 33 | |
| 34 | int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, |
| 35 | int len, u32 *val) |
| 36 | { |
| 37 | volatile void __iomem *cfg_data; |
| 38 | struct pci_controller *hose = bus->sysdata; |
| 39 | |
| 40 | if (bus->number > 7) |
| 41 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 42 | /* |
| 43 | * Note: the caller has already checked that off is |
| 44 | * suitably aligned and that len is 1, 2 or 4. |
| 45 | */ |
| 46 | cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); |
| 47 | switch (len) { |
| 48 | case 1: |
| 49 | *val = in_8(cfg_data); |
| 50 | break; |
| 51 | case 2: |
| 52 | *val = in_le16(cfg_data); |
| 53 | break; |
| 54 | default: |
| 55 | *val = in_le32(cfg_data); |
| 56 | break; |
| 57 | } |
| 58 | return PCIBIOS_SUCCESSFUL; |
| 59 | } |
| 60 | |
| 61 | int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, |
| 62 | int len, u32 val) |
| 63 | { |
| 64 | volatile void __iomem *cfg_data; |
| 65 | struct pci_controller *hose = bus->sysdata; |
| 66 | |
| 67 | if (bus->number > 7) |
| 68 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 69 | /* |
| 70 | * Note: the caller has already checked that off is |
| 71 | * suitably aligned and that len is 1, 2 or 4. |
| 72 | */ |
| 73 | cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); |
| 74 | switch (len) { |
| 75 | case 1: |
| 76 | out_8(cfg_data, val); |
| 77 | break; |
| 78 | case 2: |
| 79 | out_le16(cfg_data, val); |
| 80 | break; |
| 81 | default: |
| 82 | out_le32(cfg_data, val); |
| 83 | break; |
| 84 | } |
| 85 | return PCIBIOS_SUCCESSFUL; |
| 86 | } |
| 87 | |
| 88 | static struct pci_ops gg2_pci_ops = |
| 89 | { |
| 90 | gg2_read_config, |
| 91 | gg2_write_config |
| 92 | }; |
| 93 | |
| 94 | /* |
| 95 | * Access functions for PCI config space using RTAS calls. |
| 96 | */ |
| 97 | int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 98 | int len, u32 *val) |
| 99 | { |
| 100 | struct pci_controller *hose = bus->sysdata; |
| 101 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 102 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 103 | | (hose->index << 24); |
| 104 | int ret = -1; |
| 105 | int rval; |
| 106 | |
| 107 | rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len); |
| 108 | *val = ret; |
| 109 | return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; |
| 110 | } |
| 111 | |
| 112 | int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 113 | int len, u32 val) |
| 114 | { |
| 115 | struct pci_controller *hose = bus->sysdata; |
| 116 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 117 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 118 | | (hose->index << 24); |
| 119 | int rval; |
| 120 | |
| 121 | rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, |
| 122 | addr, len, val); |
| 123 | return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; |
| 124 | } |
| 125 | |
| 126 | static struct pci_ops rtas_pci_ops = |
| 127 | { |
| 128 | rtas_read_config, |
| 129 | rtas_write_config |
| 130 | }; |
| 131 | |
| 132 | volatile struct Hydra __iomem *Hydra = NULL; |
| 133 | |
| 134 | int __init |
| 135 | hydra_init(void) |
| 136 | { |
| 137 | struct device_node *np; |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 138 | struct resource r; |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 139 | |
| 140 | np = find_devices("mac-io"); |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 141 | if (np == NULL || of_address_to_resource(np, 0, &r)) |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 142 | return 0; |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 143 | Hydra = ioremap(r.start, r.end-r.start); |
| 144 | printk("Hydra Mac I/O at %lx\n", r.start); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 145 | printk("Hydra Feature_Control was %x", |
| 146 | in_le32(&Hydra->Feature_Control)); |
| 147 | out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | |
| 148 | HYDRA_FC_SCSI_CELL_EN | |
| 149 | HYDRA_FC_SCCA_ENABLE | |
| 150 | HYDRA_FC_SCCB_ENABLE | |
| 151 | HYDRA_FC_ARB_BYPASS | |
| 152 | HYDRA_FC_MPIC_ENABLE | |
| 153 | HYDRA_FC_SLOW_SCC_PCLK | |
| 154 | HYDRA_FC_MPIC_IS_MASTER)); |
| 155 | printk(", now %x\n", in_le32(&Hydra->Feature_Control)); |
| 156 | return 1; |
| 157 | } |
| 158 | |
| 159 | void __init |
| 160 | chrp_pcibios_fixup(void) |
| 161 | { |
| 162 | struct pci_dev *dev = NULL; |
| 163 | struct device_node *np; |
| 164 | |
| 165 | /* PCI interrupts are controlled by the OpenPIC */ |
| 166 | for_each_pci_dev(dev) { |
| 167 | np = pci_device_to_OF_node(dev); |
| 168 | if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0)) |
| 169 | dev->irq = np->intrs[0].line; |
| 170 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | #define PRG_CL_RESET_VALID 0x00010000 |
| 175 | |
| 176 | static void __init |
| 177 | setup_python(struct pci_controller *hose, struct device_node *dev) |
| 178 | { |
| 179 | u32 __iomem *reg; |
| 180 | u32 val; |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 181 | struct resource r; |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 182 | |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 183 | if (of_address_to_resource(dev, 0, &r)) { |
| 184 | printk(KERN_ERR "No address for Python PCI controller\n"); |
| 185 | return; |
| 186 | } |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 187 | |
| 188 | /* Clear the magic go-slow bit */ |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 189 | reg = ioremap(r.start + 0xf6000, 0x40); |
| 190 | BUG_ON(!reg); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 191 | val = in_be32(®[12]); |
| 192 | if (val & PRG_CL_RESET_VALID) { |
| 193 | out_be32(®[12], val & ~PRG_CL_RESET_VALID); |
| 194 | in_be32(®[12]); |
| 195 | } |
| 196 | iounmap(reg); |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 197 | |
| 198 | setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | /* Marvell Discovery II based Pegasos 2 */ |
| 202 | static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) |
| 203 | { |
| 204 | struct device_node *root = find_path_device("/"); |
| 205 | struct device_node *rtas; |
| 206 | |
Olaf Hering | d60dcd9 | 2006-02-04 12:55:41 +0100 | [diff] [blame] | 207 | of_node_get(root); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 208 | rtas = of_find_node_by_name (root, "rtas"); |
| 209 | if (rtas) { |
| 210 | hose->ops = &rtas_pci_ops; |
Olaf Hering | d60dcd9 | 2006-02-04 12:55:41 +0100 | [diff] [blame] | 211 | of_node_put(rtas); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 212 | } else { |
| 213 | printk ("RTAS supporting Pegasos OF not found, please upgrade" |
| 214 | " your firmware\n"); |
| 215 | } |
| 216 | pci_assign_all_buses = 1; |
| 217 | } |
| 218 | |
| 219 | void __init |
| 220 | chrp_find_bridges(void) |
| 221 | { |
| 222 | struct device_node *dev; |
| 223 | int *bus_range; |
| 224 | int len, index = -1; |
| 225 | struct pci_controller *hose; |
| 226 | unsigned int *dma; |
| 227 | char *model, *machine; |
| 228 | int is_longtrail = 0, is_mot = 0, is_pegasos = 0; |
| 229 | struct device_node *root = find_path_device("/"); |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 230 | struct resource r; |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 231 | /* |
| 232 | * The PCI host bridge nodes on some machines don't have |
| 233 | * properties to adequately identify them, so we have to |
| 234 | * look at what sort of machine this is as well. |
| 235 | */ |
| 236 | machine = get_property(root, "model", NULL); |
| 237 | if (machine != NULL) { |
| 238 | is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; |
| 239 | is_mot = strncmp(machine, "MOT", 3) == 0; |
| 240 | if (strncmp(machine, "Pegasos2", 8) == 0) |
| 241 | is_pegasos = 2; |
| 242 | else if (strncmp(machine, "Pegasos", 7) == 0) |
| 243 | is_pegasos = 1; |
| 244 | } |
| 245 | for (dev = root->child; dev != NULL; dev = dev->sibling) { |
| 246 | if (dev->type == NULL || strcmp(dev->type, "pci") != 0) |
| 247 | continue; |
| 248 | ++index; |
| 249 | /* The GG2 bridge on the LongTrail doesn't have an address */ |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 250 | if (of_address_to_resource(dev, 0, &r) && !is_longtrail) { |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 251 | printk(KERN_WARNING "Can't use %s: no address\n", |
| 252 | dev->full_name); |
| 253 | continue; |
| 254 | } |
| 255 | bus_range = (int *) get_property(dev, "bus-range", &len); |
| 256 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 257 | printk(KERN_WARNING "Can't get bus-range for %s\n", |
| 258 | dev->full_name); |
| 259 | continue; |
| 260 | } |
| 261 | if (bus_range[1] == bus_range[0]) |
| 262 | printk(KERN_INFO "PCI bus %d", bus_range[0]); |
| 263 | else |
| 264 | printk(KERN_INFO "PCI buses %d..%d", |
| 265 | bus_range[0], bus_range[1]); |
| 266 | printk(" controlled by %s", dev->type); |
David Woodhouse | 575e321 | 2006-01-14 00:13:49 +0000 | [diff] [blame] | 267 | if (!is_longtrail) |
| 268 | printk(" at %lx", r.start); |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 269 | printk("\n"); |
| 270 | |
| 271 | hose = pcibios_alloc_controller(); |
| 272 | if (!hose) { |
| 273 | printk("Can't allocate PCI controller structure for %s\n", |
| 274 | dev->full_name); |
| 275 | continue; |
| 276 | } |
| 277 | hose->arch_data = dev; |
| 278 | hose->first_busno = bus_range[0]; |
| 279 | hose->last_busno = bus_range[1]; |
| 280 | |
| 281 | model = get_property(dev, "model", NULL); |
| 282 | if (model == NULL) |
| 283 | model = "<none>"; |
| 284 | if (device_is_compatible(dev, "IBM,python")) { |
| 285 | setup_python(hose, dev); |
| 286 | } else if (is_mot |
| 287 | || strncmp(model, "Motorola, Grackle", 17) == 0) { |
| 288 | setup_grackle(hose); |
| 289 | } else if (is_longtrail) { |
| 290 | void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); |
| 291 | hose->ops = &gg2_pci_ops; |
| 292 | hose->cfg_data = p; |
| 293 | gg2_pci_config_base = p; |
| 294 | } else if (is_pegasos == 1) { |
| 295 | setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); |
| 296 | } else if (is_pegasos == 2) { |
| 297 | setup_peg2(hose, dev); |
| 298 | } else { |
| 299 | printk("No methods for %s (model %s), using RTAS\n", |
| 300 | dev->full_name, model); |
| 301 | hose->ops = &rtas_pci_ops; |
| 302 | } |
| 303 | |
| 304 | pci_process_bridge_OF_ranges(hose, dev, index == 0); |
| 305 | |
| 306 | /* check the first bridge for a property that we can |
| 307 | use to set pci_dram_offset */ |
| 308 | dma = (unsigned int *) |
| 309 | get_property(dev, "ibm,dma-ranges", &len); |
| 310 | if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { |
| 311 | pci_dram_offset = dma[2] - dma[3]; |
| 312 | printk("pci_dram_offset = %lx\n", pci_dram_offset); |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | /* Do not fixup interrupts from OF tree on pegasos */ |
| 317 | if (is_pegasos == 0) |
| 318 | ppc_md.pcibios_fixup = chrp_pcibios_fixup; |
| 319 | } |