Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 3 | * Copyright (c) 2005 Cisco Systems. All rights reserved. |
Roland Dreier | 2a1d9b7 | 2005-08-10 23:03:10 -0700 | [diff] [blame] | 4 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 5 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This software is available to you under a choice of one of two |
| 8 | * licenses. You may choose to be licensed under the terms of the GNU |
| 9 | * General Public License (GPL) Version 2, available from the file |
| 10 | * COPYING in the main directory of this source tree, or the |
| 11 | * OpenIB.org BSD license below: |
| 12 | * |
| 13 | * Redistribution and use in source and binary forms, with or |
| 14 | * without modification, are permitted provided that the following |
| 15 | * conditions are met: |
| 16 | * |
| 17 | * - Redistributions of source code must retain the above |
| 18 | * copyright notice, this list of conditions and the following |
| 19 | * disclaimer. |
| 20 | * |
| 21 | * - Redistributions in binary form must reproduce the above |
| 22 | * copyright notice, this list of conditions and the following |
| 23 | * disclaimer in the documentation and/or other materials |
| 24 | * provided with the distribution. |
| 25 | * |
| 26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 33 | * SOFTWARE. |
| 34 | * |
| 35 | * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $ |
| 36 | */ |
| 37 | |
| 38 | #include <linux/init.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 39 | #include <linux/string.h> |
| 40 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Roland Dreier | a4d61e8 | 2005-08-25 13:40:04 -0700 | [diff] [blame] | 42 | #include <rdma/ib_verbs.h> |
| 43 | #include <rdma/ib_cache.h> |
| 44 | #include <rdma/ib_pack.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | #include "mthca_dev.h" |
| 47 | #include "mthca_cmd.h" |
| 48 | #include "mthca_memfree.h" |
Roland Dreier | c04bc3d | 2005-08-19 10:33:35 -0700 | [diff] [blame] | 49 | #include "mthca_wqe.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | enum { |
| 52 | MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, |
| 53 | MTHCA_ACK_REQ_FREQ = 10, |
| 54 | MTHCA_FLIGHT_LIMIT = 9, |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 55 | MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */ |
| 56 | MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */ |
| 57 | MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | }; |
| 59 | |
| 60 | enum { |
| 61 | MTHCA_QP_STATE_RST = 0, |
| 62 | MTHCA_QP_STATE_INIT = 1, |
| 63 | MTHCA_QP_STATE_RTR = 2, |
| 64 | MTHCA_QP_STATE_RTS = 3, |
| 65 | MTHCA_QP_STATE_SQE = 4, |
| 66 | MTHCA_QP_STATE_SQD = 5, |
| 67 | MTHCA_QP_STATE_ERR = 6, |
| 68 | MTHCA_QP_STATE_DRAINING = 7 |
| 69 | }; |
| 70 | |
| 71 | enum { |
| 72 | MTHCA_QP_ST_RC = 0x0, |
| 73 | MTHCA_QP_ST_UC = 0x1, |
| 74 | MTHCA_QP_ST_RD = 0x2, |
| 75 | MTHCA_QP_ST_UD = 0x3, |
| 76 | MTHCA_QP_ST_MLX = 0x7 |
| 77 | }; |
| 78 | |
| 79 | enum { |
| 80 | MTHCA_QP_PM_MIGRATED = 0x3, |
| 81 | MTHCA_QP_PM_ARMED = 0x0, |
| 82 | MTHCA_QP_PM_REARM = 0x1 |
| 83 | }; |
| 84 | |
| 85 | enum { |
| 86 | /* qp_context flags */ |
| 87 | MTHCA_QP_BIT_DE = 1 << 8, |
| 88 | /* params1 */ |
| 89 | MTHCA_QP_BIT_SRE = 1 << 15, |
| 90 | MTHCA_QP_BIT_SWE = 1 << 14, |
| 91 | MTHCA_QP_BIT_SAE = 1 << 13, |
| 92 | MTHCA_QP_BIT_SIC = 1 << 4, |
| 93 | MTHCA_QP_BIT_SSC = 1 << 3, |
| 94 | /* params2 */ |
| 95 | MTHCA_QP_BIT_RRE = 1 << 15, |
| 96 | MTHCA_QP_BIT_RWE = 1 << 14, |
| 97 | MTHCA_QP_BIT_RAE = 1 << 13, |
| 98 | MTHCA_QP_BIT_RIC = 1 << 4, |
| 99 | MTHCA_QP_BIT_RSC = 1 << 3 |
| 100 | }; |
| 101 | |
| 102 | struct mthca_qp_path { |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 103 | __be32 port_pkey; |
| 104 | u8 rnr_retry; |
| 105 | u8 g_mylmc; |
| 106 | __be16 rlid; |
| 107 | u8 ackto; |
| 108 | u8 mgid_index; |
| 109 | u8 static_rate; |
| 110 | u8 hop_limit; |
| 111 | __be32 sl_tclass_flowlabel; |
| 112 | u8 rgid[16]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | } __attribute__((packed)); |
| 114 | |
| 115 | struct mthca_qp_context { |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 116 | __be32 flags; |
| 117 | __be32 tavor_sched_queue; /* Reserved on Arbel */ |
| 118 | u8 mtu_msgmax; |
| 119 | u8 rq_size_stride; /* Reserved on Tavor */ |
| 120 | u8 sq_size_stride; /* Reserved on Tavor */ |
| 121 | u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */ |
| 122 | __be32 usr_page; |
| 123 | __be32 local_qpn; |
| 124 | __be32 remote_qpn; |
| 125 | u32 reserved1[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | struct mthca_qp_path pri_path; |
| 127 | struct mthca_qp_path alt_path; |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 128 | __be32 rdd; |
| 129 | __be32 pd; |
| 130 | __be32 wqe_base; |
| 131 | __be32 wqe_lkey; |
| 132 | __be32 params1; |
| 133 | __be32 reserved2; |
| 134 | __be32 next_send_psn; |
| 135 | __be32 cqn_snd; |
| 136 | __be32 snd_wqe_base_l; /* Next send WQE on Tavor */ |
| 137 | __be32 snd_db_index; /* (debugging only entries) */ |
| 138 | __be32 last_acked_psn; |
| 139 | __be32 ssn; |
| 140 | __be32 params2; |
| 141 | __be32 rnr_nextrecvpsn; |
| 142 | __be32 ra_buff_indx; |
| 143 | __be32 cqn_rcv; |
| 144 | __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */ |
| 145 | __be32 rcv_db_index; /* (debugging only entries) */ |
| 146 | __be32 qkey; |
| 147 | __be32 srqn; |
| 148 | __be32 rmsn; |
| 149 | __be16 rq_wqe_counter; /* reserved on Tavor */ |
| 150 | __be16 sq_wqe_counter; /* reserved on Tavor */ |
| 151 | u32 reserved3[18]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | } __attribute__((packed)); |
| 153 | |
| 154 | struct mthca_qp_param { |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 155 | __be32 opt_param_mask; |
| 156 | u32 reserved1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | struct mthca_qp_context context; |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 158 | u32 reserved2[62]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | } __attribute__((packed)); |
| 160 | |
| 161 | enum { |
| 162 | MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, |
| 163 | MTHCA_QP_OPTPAR_RRE = 1 << 1, |
| 164 | MTHCA_QP_OPTPAR_RAE = 1 << 2, |
| 165 | MTHCA_QP_OPTPAR_RWE = 1 << 3, |
| 166 | MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4, |
| 167 | MTHCA_QP_OPTPAR_Q_KEY = 1 << 5, |
| 168 | MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, |
| 169 | MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, |
| 170 | MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8, |
| 171 | MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9, |
| 172 | MTHCA_QP_OPTPAR_PM_STATE = 1 << 10, |
| 173 | MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11, |
| 174 | MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12, |
| 175 | MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13, |
| 176 | MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, |
| 177 | MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15, |
| 178 | MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 |
| 179 | }; |
| 180 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | static const u8 mthca_opcode[] = { |
| 182 | [IB_WR_SEND] = MTHCA_OPCODE_SEND, |
| 183 | [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, |
| 184 | [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE, |
| 185 | [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM, |
| 186 | [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ, |
| 187 | [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS, |
| 188 | [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA, |
| 189 | }; |
| 190 | |
| 191 | static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp) |
| 192 | { |
| 193 | return qp->qpn >= dev->qp_table.sqp_start && |
| 194 | qp->qpn <= dev->qp_table.sqp_start + 3; |
| 195 | } |
| 196 | |
| 197 | static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp) |
| 198 | { |
| 199 | return qp->qpn >= dev->qp_table.sqp_start && |
| 200 | qp->qpn <= dev->qp_table.sqp_start + 1; |
| 201 | } |
| 202 | |
| 203 | static void *get_recv_wqe(struct mthca_qp *qp, int n) |
| 204 | { |
| 205 | if (qp->is_direct) |
| 206 | return qp->queue.direct.buf + (n << qp->rq.wqe_shift); |
| 207 | else |
| 208 | return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf + |
| 209 | ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1)); |
| 210 | } |
| 211 | |
| 212 | static void *get_send_wqe(struct mthca_qp *qp, int n) |
| 213 | { |
| 214 | if (qp->is_direct) |
| 215 | return qp->queue.direct.buf + qp->send_wqe_offset + |
| 216 | (n << qp->sq.wqe_shift); |
| 217 | else |
| 218 | return qp->queue.page_list[(qp->send_wqe_offset + |
| 219 | (n << qp->sq.wqe_shift)) >> |
| 220 | PAGE_SHIFT].buf + |
| 221 | ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) & |
| 222 | (PAGE_SIZE - 1)); |
| 223 | } |
| 224 | |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 225 | static void mthca_wq_init(struct mthca_wq *wq) |
| 226 | { |
| 227 | spin_lock_init(&wq->lock); |
| 228 | wq->next_ind = 0; |
| 229 | wq->last_comp = wq->max - 1; |
| 230 | wq->head = 0; |
| 231 | wq->tail = 0; |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 232 | } |
| 233 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | void mthca_qp_event(struct mthca_dev *dev, u32 qpn, |
| 235 | enum ib_event_type event_type) |
| 236 | { |
| 237 | struct mthca_qp *qp; |
| 238 | struct ib_event event; |
| 239 | |
| 240 | spin_lock(&dev->qp_table.lock); |
| 241 | qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1)); |
| 242 | if (qp) |
| 243 | atomic_inc(&qp->refcount); |
| 244 | spin_unlock(&dev->qp_table.lock); |
| 245 | |
| 246 | if (!qp) { |
| 247 | mthca_warn(dev, "Async event for bogus QP %08x\n", qpn); |
| 248 | return; |
| 249 | } |
| 250 | |
| 251 | event.device = &dev->ib_dev; |
| 252 | event.event = event_type; |
| 253 | event.element.qp = &qp->ibqp; |
| 254 | if (qp->ibqp.event_handler) |
| 255 | qp->ibqp.event_handler(&event, qp->ibqp.qp_context); |
| 256 | |
| 257 | if (atomic_dec_and_test(&qp->refcount)) |
| 258 | wake_up(&qp->wait); |
| 259 | } |
| 260 | |
| 261 | static int to_mthca_state(enum ib_qp_state ib_state) |
| 262 | { |
| 263 | switch (ib_state) { |
| 264 | case IB_QPS_RESET: return MTHCA_QP_STATE_RST; |
| 265 | case IB_QPS_INIT: return MTHCA_QP_STATE_INIT; |
| 266 | case IB_QPS_RTR: return MTHCA_QP_STATE_RTR; |
| 267 | case IB_QPS_RTS: return MTHCA_QP_STATE_RTS; |
| 268 | case IB_QPS_SQD: return MTHCA_QP_STATE_SQD; |
| 269 | case IB_QPS_SQE: return MTHCA_QP_STATE_SQE; |
| 270 | case IB_QPS_ERR: return MTHCA_QP_STATE_ERR; |
| 271 | default: return -1; |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; |
| 276 | |
| 277 | static int to_mthca_st(int transport) |
| 278 | { |
| 279 | switch (transport) { |
| 280 | case RC: return MTHCA_QP_ST_RC; |
| 281 | case UC: return MTHCA_QP_ST_UC; |
| 282 | case UD: return MTHCA_QP_ST_UD; |
| 283 | case RD: return MTHCA_QP_ST_RD; |
| 284 | case MLX: return MTHCA_QP_ST_MLX; |
| 285 | default: return -1; |
| 286 | } |
| 287 | } |
| 288 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr, |
| 290 | int attr_mask) |
| 291 | { |
| 292 | if (attr_mask & IB_QP_PKEY_INDEX) |
| 293 | sqp->pkey_index = attr->pkey_index; |
| 294 | if (attr_mask & IB_QP_QKEY) |
| 295 | sqp->qkey = attr->qkey; |
| 296 | if (attr_mask & IB_QP_SQ_PSN) |
| 297 | sqp->send_psn = attr->sq_psn; |
| 298 | } |
| 299 | |
| 300 | static void init_port(struct mthca_dev *dev, int port) |
| 301 | { |
| 302 | int err; |
| 303 | u8 status; |
| 304 | struct mthca_init_ib_param param; |
| 305 | |
| 306 | memset(¶m, 0, sizeof param); |
| 307 | |
Roland Dreier | da6561c | 2005-08-17 07:39:10 -0700 | [diff] [blame] | 308 | param.port_width = dev->limits.port_width_cap; |
| 309 | param.vl_cap = dev->limits.vl_cap; |
| 310 | param.mtu_cap = dev->limits.mtu_cap; |
| 311 | param.gid_cap = dev->limits.gid_table_len; |
| 312 | param.pkey_cap = dev->limits.pkey_table_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | |
| 314 | err = mthca_INIT_IB(dev, ¶m, port, &status); |
| 315 | if (err) |
| 316 | mthca_warn(dev, "INIT_IB failed, return code %d.\n", err); |
| 317 | if (status) |
| 318 | mthca_warn(dev, "INIT_IB returned status %02x.\n", status); |
| 319 | } |
| 320 | |
Jack Morgenstein | d1646f8 | 2005-12-15 14:36:24 -0800 | [diff] [blame] | 321 | static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr, |
| 322 | int attr_mask) |
| 323 | { |
| 324 | u8 dest_rd_atomic; |
| 325 | u32 access_flags; |
| 326 | u32 hw_access_flags = 0; |
| 327 | |
| 328 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
| 329 | dest_rd_atomic = attr->max_dest_rd_atomic; |
| 330 | else |
| 331 | dest_rd_atomic = qp->resp_depth; |
| 332 | |
| 333 | if (attr_mask & IB_QP_ACCESS_FLAGS) |
| 334 | access_flags = attr->qp_access_flags; |
| 335 | else |
| 336 | access_flags = qp->atomic_rd_en; |
| 337 | |
| 338 | if (!dest_rd_atomic) |
| 339 | access_flags &= IB_ACCESS_REMOTE_WRITE; |
| 340 | |
| 341 | if (access_flags & IB_ACCESS_REMOTE_READ) |
| 342 | hw_access_flags |= MTHCA_QP_BIT_RRE; |
| 343 | if (access_flags & IB_ACCESS_REMOTE_ATOMIC) |
| 344 | hw_access_flags |= MTHCA_QP_BIT_RAE; |
| 345 | if (access_flags & IB_ACCESS_REMOTE_WRITE) |
| 346 | hw_access_flags |= MTHCA_QP_BIT_RWE; |
| 347 | |
| 348 | return cpu_to_be32(hw_access_flags); |
| 349 | } |
| 350 | |
Eli Cohen | 8ebe507 | 2006-02-13 16:40:21 -0800 | [diff] [blame] | 351 | static inline enum ib_qp_state to_ib_qp_state(int mthca_state) |
| 352 | { |
| 353 | switch (mthca_state) { |
| 354 | case MTHCA_QP_STATE_RST: return IB_QPS_RESET; |
| 355 | case MTHCA_QP_STATE_INIT: return IB_QPS_INIT; |
| 356 | case MTHCA_QP_STATE_RTR: return IB_QPS_RTR; |
| 357 | case MTHCA_QP_STATE_RTS: return IB_QPS_RTS; |
| 358 | case MTHCA_QP_STATE_DRAINING: |
| 359 | case MTHCA_QP_STATE_SQD: return IB_QPS_SQD; |
| 360 | case MTHCA_QP_STATE_SQE: return IB_QPS_SQE; |
| 361 | case MTHCA_QP_STATE_ERR: return IB_QPS_ERR; |
| 362 | default: return -1; |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state) |
| 367 | { |
| 368 | switch (mthca_mig_state) { |
| 369 | case 0: return IB_MIG_ARMED; |
| 370 | case 1: return IB_MIG_REARM; |
| 371 | case 3: return IB_MIG_MIGRATED; |
| 372 | default: return -1; |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | static int to_ib_qp_access_flags(int mthca_flags) |
| 377 | { |
| 378 | int ib_flags = 0; |
| 379 | |
| 380 | if (mthca_flags & MTHCA_QP_BIT_RRE) |
| 381 | ib_flags |= IB_ACCESS_REMOTE_READ; |
| 382 | if (mthca_flags & MTHCA_QP_BIT_RWE) |
| 383 | ib_flags |= IB_ACCESS_REMOTE_WRITE; |
| 384 | if (mthca_flags & MTHCA_QP_BIT_RAE) |
| 385 | ib_flags |= IB_ACCESS_REMOTE_ATOMIC; |
| 386 | |
| 387 | return ib_flags; |
| 388 | } |
| 389 | |
| 390 | static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr, |
| 391 | struct mthca_qp_path *path) |
| 392 | { |
| 393 | memset(ib_ah_attr, 0, sizeof *path); |
| 394 | ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3; |
| 395 | ib_ah_attr->dlid = be16_to_cpu(path->rlid); |
| 396 | ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28; |
| 397 | ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f; |
| 398 | ib_ah_attr->static_rate = path->static_rate & 0x7; |
| 399 | ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0; |
| 400 | if (ib_ah_attr->ah_flags) { |
| 401 | ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1); |
| 402 | ib_ah_attr->grh.hop_limit = path->hop_limit; |
| 403 | ib_ah_attr->grh.traffic_class = |
| 404 | (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff; |
| 405 | ib_ah_attr->grh.flow_label = |
| 406 | be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff; |
| 407 | memcpy(ib_ah_attr->grh.dgid.raw, |
| 408 | path->rgid, sizeof ib_ah_attr->grh.dgid.raw); |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, |
| 413 | struct ib_qp_init_attr *qp_init_attr) |
| 414 | { |
| 415 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 416 | struct mthca_qp *qp = to_mqp(ibqp); |
| 417 | int err; |
| 418 | struct mthca_mailbox *mailbox; |
| 419 | struct mthca_qp_param *qp_param; |
| 420 | struct mthca_qp_context *context; |
| 421 | int mthca_state; |
| 422 | u8 status; |
| 423 | |
| 424 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
| 425 | if (IS_ERR(mailbox)) |
| 426 | return PTR_ERR(mailbox); |
| 427 | |
| 428 | err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status); |
| 429 | if (err) |
| 430 | goto out; |
| 431 | if (status) { |
| 432 | mthca_warn(dev, "QUERY_QP returned status %02x\n", status); |
| 433 | err = -EINVAL; |
| 434 | goto out; |
| 435 | } |
| 436 | |
| 437 | qp_param = mailbox->buf; |
| 438 | context = &qp_param->context; |
| 439 | mthca_state = be32_to_cpu(context->flags) >> 28; |
| 440 | |
| 441 | qp_attr->qp_state = to_ib_qp_state(mthca_state); |
| 442 | qp_attr->cur_qp_state = qp_attr->qp_state; |
| 443 | qp_attr->path_mtu = context->mtu_msgmax >> 5; |
| 444 | qp_attr->path_mig_state = |
| 445 | to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); |
| 446 | qp_attr->qkey = be32_to_cpu(context->qkey); |
| 447 | qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; |
| 448 | qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; |
| 449 | qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff; |
| 450 | qp_attr->qp_access_flags = |
| 451 | to_ib_qp_access_flags(be32_to_cpu(context->params2)); |
| 452 | qp_attr->cap.max_send_wr = qp->sq.max; |
| 453 | qp_attr->cap.max_recv_wr = qp->rq.max; |
| 454 | qp_attr->cap.max_send_sge = qp->sq.max_gs; |
| 455 | qp_attr->cap.max_recv_sge = qp->rq.max_gs; |
| 456 | qp_attr->cap.max_inline_data = qp->max_inline_data; |
| 457 | |
| 458 | to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); |
| 459 | to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); |
| 460 | |
| 461 | qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f; |
| 462 | qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f; |
| 463 | |
| 464 | /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ |
| 465 | qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING; |
| 466 | |
| 467 | qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); |
| 468 | |
| 469 | qp_attr->max_dest_rd_atomic = |
| 470 | 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); |
| 471 | qp_attr->min_rnr_timer = |
| 472 | (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; |
| 473 | qp_attr->port_num = qp_attr->ah_attr.port_num; |
| 474 | qp_attr->timeout = context->pri_path.ackto >> 3; |
| 475 | qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; |
| 476 | qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5; |
| 477 | qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; |
| 478 | qp_attr->alt_timeout = context->alt_path.ackto >> 3; |
| 479 | qp_init_attr->cap = qp_attr->cap; |
| 480 | |
| 481 | out: |
| 482 | mthca_free_mailbox(dev, mailbox); |
| 483 | return err; |
| 484 | } |
| 485 | |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 486 | static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah, |
| 487 | struct mthca_qp_path *path) |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 488 | { |
| 489 | path->g_mylmc = ah->src_path_bits & 0x7f; |
| 490 | path->rlid = cpu_to_be16(ah->dlid); |
| 491 | path->static_rate = !!ah->static_rate; |
| 492 | |
| 493 | if (ah->ah_flags & IB_AH_GRH) { |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 494 | if (ah->grh.sgid_index >= dev->limits.gid_table_len) { |
| 495 | mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n", |
| 496 | ah->grh.sgid_index, dev->limits.gid_table_len-1); |
| 497 | return -1; |
| 498 | } |
| 499 | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 500 | path->g_mylmc |= 1 << 7; |
| 501 | path->mgid_index = ah->grh.sgid_index; |
| 502 | path->hop_limit = ah->grh.hop_limit; |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 503 | path->sl_tclass_flowlabel = |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 504 | cpu_to_be32((ah->sl << 28) | |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 505 | (ah->grh.traffic_class << 20) | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 506 | (ah->grh.flow_label)); |
| 507 | memcpy(path->rgid, ah->grh.dgid.raw, 16); |
| 508 | } else |
| 509 | path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28); |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 510 | |
| 511 | return 0; |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 512 | } |
| 513 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) |
| 515 | { |
| 516 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 517 | struct mthca_qp *qp = to_mqp(ibqp); |
| 518 | enum ib_qp_state cur_state, new_state; |
Roland Dreier | ed87845 | 2005-06-27 14:36:45 -0700 | [diff] [blame] | 519 | struct mthca_mailbox *mailbox; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | struct mthca_qp_param *qp_param; |
| 521 | struct mthca_qp_context *qp_context; |
Roland Dreier | 3fa1fa3 | 2006-02-03 14:53:28 -0800 | [diff] [blame] | 522 | u32 sqd_event = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | u8 status; |
| 524 | int err; |
| 525 | |
| 526 | if (attr_mask & IB_QP_CUR_STATE) { |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 527 | cur_state = attr->cur_qp_state; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | } else { |
| 529 | spin_lock_irq(&qp->sq.lock); |
| 530 | spin_lock(&qp->rq.lock); |
| 531 | cur_state = qp->state; |
| 532 | spin_unlock(&qp->rq.lock); |
| 533 | spin_unlock_irq(&qp->sq.lock); |
| 534 | } |
| 535 | |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 536 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 538 | if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) { |
| 539 | mthca_dbg(dev, "Bad QP transition (transport %d) " |
| 540 | "%d->%d with attr 0x%08x\n", |
| 541 | qp->transport, cur_state, new_state, |
| 542 | attr_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | return -EINVAL; |
| 544 | } |
| 545 | |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 546 | if ((attr_mask & IB_QP_PKEY_INDEX) && |
Jack Morgenstein | d09e327 | 2005-11-03 14:58:33 -0800 | [diff] [blame] | 547 | attr->pkey_index >= dev->limits.pkey_table_len) { |
Dotan Barak | 67e7377 | 2006-03-01 14:28:12 -0800 | [diff] [blame] | 548 | mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n", |
| 549 | attr->pkey_index, dev->limits.pkey_table_len-1); |
Jack Morgenstein | d09e327 | 2005-11-03 14:58:33 -0800 | [diff] [blame] | 550 | return -EINVAL; |
| 551 | } |
| 552 | |
Jack Morgenstein | 38d1e79 | 2006-01-05 16:13:46 -0800 | [diff] [blame] | 553 | if ((attr_mask & IB_QP_PORT) && |
| 554 | (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) { |
| 555 | mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num); |
| 556 | return -EINVAL; |
| 557 | } |
| 558 | |
Jack Morgenstein | 94361cf | 2005-12-09 16:32:21 -0800 | [diff] [blame] | 559 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && |
| 560 | attr->max_rd_atomic > dev->limits.max_qp_init_rdma) { |
| 561 | mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n", |
| 562 | attr->max_rd_atomic, dev->limits.max_qp_init_rdma); |
| 563 | return -EINVAL; |
| 564 | } |
| 565 | |
| 566 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && |
| 567 | attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) { |
| 568 | mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n", |
| 569 | attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift); |
| 570 | return -EINVAL; |
| 571 | } |
| 572 | |
Roland Dreier | ed87845 | 2005-06-27 14:36:45 -0700 | [diff] [blame] | 573 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
| 574 | if (IS_ERR(mailbox)) |
| 575 | return PTR_ERR(mailbox); |
| 576 | qp_param = mailbox->buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | qp_context = &qp_param->context; |
| 578 | memset(qp_param, 0, sizeof *qp_param); |
| 579 | |
| 580 | qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) | |
| 581 | (to_mthca_st(qp->transport) << 16)); |
| 582 | qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE); |
| 583 | if (!(attr_mask & IB_QP_PATH_MIG_STATE)) |
| 584 | qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); |
| 585 | else { |
| 586 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE); |
| 587 | switch (attr->path_mig_state) { |
| 588 | case IB_MIG_MIGRATED: |
| 589 | qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); |
| 590 | break; |
| 591 | case IB_MIG_REARM: |
| 592 | qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11); |
| 593 | break; |
| 594 | case IB_MIG_ARMED: |
| 595 | qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11); |
| 596 | break; |
| 597 | } |
| 598 | } |
| 599 | |
| 600 | /* leave tavor_sched_queue as 0 */ |
| 601 | |
| 602 | if (qp->transport == MLX || qp->transport == UD) |
| 603 | qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11; |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 604 | else if (attr_mask & IB_QP_PATH_MTU) { |
| 605 | if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) { |
| 606 | mthca_dbg(dev, "path MTU (%u) is invalid\n", |
| 607 | attr->path_mtu); |
| 608 | return -EINVAL; |
| 609 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31; |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 611 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 613 | if (mthca_is_memfree(dev)) { |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 614 | if (qp->rq.max) |
| 615 | qp_context->rq_size_stride = long_log2(qp->rq.max) << 3; |
| 616 | qp_context->rq_size_stride |= qp->rq.wqe_shift - 4; |
| 617 | |
| 618 | if (qp->sq.max) |
| 619 | qp_context->sq_size_stride = long_log2(qp->sq.max) << 3; |
| 620 | qp_context->sq_size_stride |= qp->sq.wqe_shift - 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | /* leave arbel_sched_queue as 0 */ |
| 624 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 625 | if (qp->ibqp.uobject) |
| 626 | qp_context->usr_page = |
| 627 | cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index); |
| 628 | else |
| 629 | qp_context->usr_page = cpu_to_be32(dev->driver_uar.index); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | qp_context->local_qpn = cpu_to_be32(qp->qpn); |
| 631 | if (attr_mask & IB_QP_DEST_QPN) { |
| 632 | qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num); |
| 633 | } |
| 634 | |
| 635 | if (qp->transport == MLX) |
| 636 | qp_context->pri_path.port_pkey |= |
| 637 | cpu_to_be32(to_msqp(qp)->port << 24); |
| 638 | else { |
| 639 | if (attr_mask & IB_QP_PORT) { |
| 640 | qp_context->pri_path.port_pkey |= |
| 641 | cpu_to_be32(attr->port_num << 24); |
| 642 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM); |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | if (attr_mask & IB_QP_PKEY_INDEX) { |
| 647 | qp_context->pri_path.port_pkey |= |
| 648 | cpu_to_be32(attr->pkey_index); |
| 649 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX); |
| 650 | } |
| 651 | |
| 652 | if (attr_mask & IB_QP_RNR_RETRY) { |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 653 | qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry = |
| 654 | attr->rnr_retry << 5; |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 655 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 656 | MTHCA_QP_OPTPAR_ALT_RNR_RETRY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | } |
| 658 | |
| 659 | if (attr_mask & IB_QP_AV) { |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 660 | if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path)) |
| 661 | return -EINVAL; |
| 662 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH); |
| 664 | } |
| 665 | |
| 666 | if (attr_mask & IB_QP_TIMEOUT) { |
Roland Dreier | bb4a7f0 | 2005-09-12 14:08:51 -0700 | [diff] [blame] | 667 | qp_context->pri_path.ackto = attr->timeout << 3; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT); |
| 669 | } |
| 670 | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 671 | if (attr_mask & IB_QP_ALT_PATH) { |
Dotan Barak | 67e7377 | 2006-03-01 14:28:12 -0800 | [diff] [blame] | 672 | if (attr->alt_pkey_index >= dev->limits.pkey_table_len) { |
| 673 | mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n", |
| 674 | attr->alt_pkey_index, dev->limits.pkey_table_len-1); |
| 675 | return -EINVAL; |
| 676 | } |
| 677 | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 678 | if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) { |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 679 | mthca_dbg(dev, "Alternate port number (%u) is invalid\n", |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 680 | attr->alt_port_num); |
| 681 | return -EINVAL; |
| 682 | } |
| 683 | |
Dotan Barak | 0ef61db | 2006-03-19 17:20:36 +0200 | [diff] [blame] | 684 | if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path)) |
| 685 | return -EINVAL; |
| 686 | |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 687 | qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index | |
Dotan Barak | 4de144b | 2006-01-06 13:23:58 -0800 | [diff] [blame] | 688 | attr->alt_port_num << 24); |
| 689 | qp_context->alt_path.ackto = attr->alt_timeout << 3; |
| 690 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH); |
| 691 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 692 | |
| 693 | /* leave rdd as 0 */ |
| 694 | qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num); |
| 695 | /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */ |
| 696 | qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey); |
| 697 | qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) | |
| 698 | (MTHCA_FLIGHT_LIMIT << 24) | |
Jack Morgenstein | c4342d8 | 2005-12-15 19:59:01 -0800 | [diff] [blame] | 699 | MTHCA_QP_BIT_SWE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | if (qp->sq_policy == IB_SIGNAL_ALL_WR) |
| 701 | qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC); |
| 702 | if (attr_mask & IB_QP_RETRY_CNT) { |
| 703 | qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16); |
| 704 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT); |
| 705 | } |
| 706 | |
Roland Dreier | 34a4a75 | 2005-06-27 14:36:41 -0700 | [diff] [blame] | 707 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { |
Jack Morgenstein | c4342d8 | 2005-12-15 19:59:01 -0800 | [diff] [blame] | 708 | if (attr->max_rd_atomic) { |
| 709 | qp_context->params1 |= |
| 710 | cpu_to_be32(MTHCA_QP_BIT_SRE | |
| 711 | MTHCA_QP_BIT_SAE); |
Jack Morgenstein | 6aa2e4e | 2005-12-09 16:38:04 -0800 | [diff] [blame] | 712 | qp_context->params1 |= |
| 713 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); |
Jack Morgenstein | c4342d8 | 2005-12-15 19:59:01 -0800 | [diff] [blame] | 714 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX); |
| 716 | } |
| 717 | |
| 718 | if (attr_mask & IB_QP_SQ_PSN) |
| 719 | qp_context->next_send_psn = cpu_to_be32(attr->sq_psn); |
| 720 | qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn); |
| 721 | |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 722 | if (mthca_is_memfree(dev)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset); |
| 724 | qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index); |
| 725 | } |
| 726 | |
Roland Dreier | 34a4a75 | 2005-06-27 14:36:41 -0700 | [diff] [blame] | 727 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { |
Jack Morgenstein | 6aa2e4e | 2005-12-09 16:38:04 -0800 | [diff] [blame] | 728 | if (attr->max_dest_rd_atomic) |
| 729 | qp_context->params2 |= |
| 730 | cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 731 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | } |
| 734 | |
Jack Morgenstein | d1646f8 | 2005-12-15 14:36:24 -0800 | [diff] [blame] | 735 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { |
| 736 | qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask); |
| 737 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE | |
| 738 | MTHCA_QP_OPTPAR_RRE | |
| 739 | MTHCA_QP_OPTPAR_RAE); |
| 740 | } |
| 741 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); |
| 743 | |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 744 | if (ibqp->srq) |
| 745 | qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC); |
| 746 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { |
| 748 | qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); |
| 749 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT); |
| 750 | } |
| 751 | if (attr_mask & IB_QP_RQ_PSN) |
| 752 | qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); |
| 753 | |
| 754 | qp_context->ra_buff_indx = |
| 755 | cpu_to_be32(dev->qp_table.rdb_base + |
| 756 | ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE << |
| 757 | dev->qp_table.rdb_shift)); |
| 758 | |
| 759 | qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn); |
| 760 | |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 761 | if (mthca_is_memfree(dev)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 762 | qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index); |
| 763 | |
| 764 | if (attr_mask & IB_QP_QKEY) { |
| 765 | qp_context->qkey = cpu_to_be32(attr->qkey); |
| 766 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY); |
| 767 | } |
| 768 | |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 769 | if (ibqp->srq) |
| 770 | qp_context->srqn = cpu_to_be32(1 << 24 | |
| 771 | to_msrq(ibqp->srq)->srqn); |
| 772 | |
Roland Dreier | 3fa1fa3 | 2006-02-03 14:53:28 -0800 | [diff] [blame] | 773 | if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && |
| 774 | attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && |
| 775 | attr->en_sqd_async_notify) |
| 776 | sqd_event = 1 << 31; |
| 777 | |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 778 | err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0, |
| 779 | mailbox, sqd_event, &status); |
Roland Dreier | 192daa1 | 2006-03-24 15:47:30 -0800 | [diff] [blame] | 780 | if (err) |
| 781 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | if (status) { |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 783 | mthca_warn(dev, "modify QP %d->%d returned status %02x.\n", |
| 784 | cur_state, new_state, status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 785 | err = -EINVAL; |
Roland Dreier | 192daa1 | 2006-03-24 15:47:30 -0800 | [diff] [blame] | 786 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | } |
| 788 | |
Roland Dreier | 192daa1 | 2006-03-24 15:47:30 -0800 | [diff] [blame] | 789 | qp->state = new_state; |
| 790 | if (attr_mask & IB_QP_ACCESS_FLAGS) |
| 791 | qp->atomic_rd_en = attr->qp_access_flags; |
| 792 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
| 793 | qp->resp_depth = attr->max_dest_rd_atomic; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | |
| 795 | if (is_sqp(dev, qp)) |
| 796 | store_attrs(to_msqp(qp), attr, attr_mask); |
| 797 | |
| 798 | /* |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 799 | * If we moved QP0 to RTR, bring the IB link up; if we moved |
| 800 | * QP0 to RESET or ERROR, bring the link back down. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | */ |
| 802 | if (is_qp0(dev, qp)) { |
| 803 | if (cur_state != IB_QPS_RTR && |
| 804 | new_state == IB_QPS_RTR) |
| 805 | init_port(dev, to_msqp(qp)->port); |
| 806 | |
| 807 | if (cur_state != IB_QPS_RESET && |
| 808 | cur_state != IB_QPS_ERR && |
| 809 | (new_state == IB_QPS_RESET || |
| 810 | new_state == IB_QPS_ERR)) |
| 811 | mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status); |
| 812 | } |
| 813 | |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 814 | /* |
| 815 | * If we moved a kernel QP to RESET, clean up all old CQ |
| 816 | * entries and reinitialize the QP. |
| 817 | */ |
Roland Dreier | 192daa1 | 2006-03-24 15:47:30 -0800 | [diff] [blame] | 818 | if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) { |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 819 | mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn, |
| 820 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
| 821 | if (qp->ibqp.send_cq != qp->ibqp.recv_cq) |
| 822 | mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn, |
| 823 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
| 824 | |
| 825 | mthca_wq_init(&qp->sq); |
Michael S. Tsirkin | 187a258 | 2005-11-28 11:19:43 -0800 | [diff] [blame] | 826 | qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); |
| 827 | |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 828 | mthca_wq_init(&qp->rq); |
Michael S. Tsirkin | 187a258 | 2005-11-28 11:19:43 -0800 | [diff] [blame] | 829 | qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); |
Roland Dreier | c9fe2b3 | 2005-09-07 09:43:23 -0700 | [diff] [blame] | 830 | |
| 831 | if (mthca_is_memfree(dev)) { |
| 832 | *qp->sq.db = 0; |
| 833 | *qp->rq.db = 0; |
| 834 | } |
| 835 | } |
| 836 | |
Roland Dreier | 192daa1 | 2006-03-24 15:47:30 -0800 | [diff] [blame] | 837 | out: |
| 838 | mthca_free_mailbox(dev, mailbox); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | return err; |
| 840 | } |
| 841 | |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 842 | static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz) |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 843 | { |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 844 | /* |
| 845 | * Calculate the maximum size of WQE s/g segments, excluding |
| 846 | * the next segment and other non-data segments. |
| 847 | */ |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 848 | int max_data_size = desc_sz - sizeof (struct mthca_next_seg); |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 849 | |
| 850 | switch (qp->transport) { |
| 851 | case MLX: |
| 852 | max_data_size -= 2 * sizeof (struct mthca_data_seg); |
| 853 | break; |
| 854 | |
| 855 | case UD: |
| 856 | if (mthca_is_memfree(dev)) |
| 857 | max_data_size -= sizeof (struct mthca_arbel_ud_seg); |
| 858 | else |
| 859 | max_data_size -= sizeof (struct mthca_tavor_ud_seg); |
| 860 | break; |
| 861 | |
| 862 | default: |
| 863 | max_data_size -= sizeof (struct mthca_raddr_seg); |
| 864 | break; |
| 865 | } |
| 866 | |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 867 | return max_data_size; |
| 868 | } |
| 869 | |
| 870 | static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size) |
| 871 | { |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 872 | /* We don't support inline data for kernel QPs (yet). */ |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 873 | return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0; |
| 874 | } |
| 875 | |
| 876 | static void mthca_adjust_qp_caps(struct mthca_dev *dev, |
| 877 | struct mthca_pd *pd, |
| 878 | struct mthca_qp *qp) |
| 879 | { |
| 880 | int max_data_size = mthca_max_data_size(dev, qp, |
| 881 | min(dev->limits.max_desc_sz, |
| 882 | 1 << qp->sq.wqe_shift)); |
| 883 | |
| 884 | qp->max_inline_data = mthca_max_inline_data(pd, max_data_size); |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 885 | |
Michael S. Tsirkin | 48fd0d1 | 2005-11-18 14:11:17 -0800 | [diff] [blame] | 886 | qp->sq.max_gs = min_t(int, dev->limits.max_sg, |
| 887 | max_data_size / sizeof (struct mthca_data_seg)); |
| 888 | qp->rq.max_gs = min_t(int, dev->limits.max_sg, |
| 889 | (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) - |
| 890 | sizeof (struct mthca_next_seg)) / |
| 891 | sizeof (struct mthca_data_seg)); |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 892 | } |
| 893 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | /* |
| 895 | * Allocate and register buffer for WQEs. qp->rq.max, sq.max, |
| 896 | * rq.max_gs and sq.max_gs must all be assigned. |
| 897 | * mthca_alloc_wqe_buf will calculate rq.wqe_shift and |
| 898 | * sq.wqe_shift (as well as send_wqe_offset, is_direct, and |
| 899 | * queue) |
| 900 | */ |
| 901 | static int mthca_alloc_wqe_buf(struct mthca_dev *dev, |
| 902 | struct mthca_pd *pd, |
| 903 | struct mthca_qp *qp) |
| 904 | { |
| 905 | int size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | int err = -ENOMEM; |
| 907 | |
| 908 | size = sizeof (struct mthca_next_seg) + |
| 909 | qp->rq.max_gs * sizeof (struct mthca_data_seg); |
| 910 | |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 911 | if (size > dev->limits.max_desc_sz) |
| 912 | return -EINVAL; |
| 913 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size; |
| 915 | qp->rq.wqe_shift++) |
| 916 | ; /* nothing */ |
| 917 | |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 918 | size = qp->sq.max_gs * sizeof (struct mthca_data_seg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | switch (qp->transport) { |
| 920 | case MLX: |
| 921 | size += 2 * sizeof (struct mthca_data_seg); |
| 922 | break; |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 923 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | case UD: |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 925 | size += mthca_is_memfree(dev) ? |
| 926 | sizeof (struct mthca_arbel_ud_seg) : |
| 927 | sizeof (struct mthca_tavor_ud_seg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 928 | break; |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 929 | |
| 930 | case UC: |
| 931 | size += sizeof (struct mthca_raddr_seg); |
| 932 | break; |
| 933 | |
| 934 | case RC: |
| 935 | size += sizeof (struct mthca_raddr_seg); |
| 936 | /* |
| 937 | * An atomic op will require an atomic segment, a |
| 938 | * remote address segment and one scatter entry. |
| 939 | */ |
| 940 | size = max_t(int, size, |
| 941 | sizeof (struct mthca_atomic_seg) + |
| 942 | sizeof (struct mthca_raddr_seg) + |
| 943 | sizeof (struct mthca_data_seg)); |
| 944 | break; |
| 945 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 946 | default: |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 947 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | } |
| 949 | |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 950 | /* Make sure that we have enough space for a bind request */ |
| 951 | size = max_t(int, size, sizeof (struct mthca_bind_seg)); |
| 952 | |
| 953 | size += sizeof (struct mthca_next_seg); |
| 954 | |
| 955 | if (size > dev->limits.max_desc_sz) |
| 956 | return -EINVAL; |
| 957 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size; |
| 959 | qp->sq.wqe_shift++) |
| 960 | ; /* nothing */ |
| 961 | |
| 962 | qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift, |
| 963 | 1 << qp->sq.wqe_shift); |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 964 | |
| 965 | /* |
| 966 | * If this is a userspace QP, we don't actually have to |
| 967 | * allocate anything. All we need is to calculate the WQE |
| 968 | * sizes and the send_wqe_offset, so we're done now. |
| 969 | */ |
| 970 | if (pd->ibpd.uobject) |
| 971 | return 0; |
| 972 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 973 | size = PAGE_ALIGN(qp->send_wqe_offset + |
| 974 | (qp->sq.max << qp->sq.wqe_shift)); |
| 975 | |
| 976 | qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64), |
| 977 | GFP_KERNEL); |
| 978 | if (!qp->wrid) |
| 979 | goto err_out; |
| 980 | |
Roland Dreier | 87b8167 | 2005-08-18 13:39:31 -0700 | [diff] [blame] | 981 | err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE, |
| 982 | &qp->queue, &qp->is_direct, pd, 0, &qp->mr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | if (err) |
Roland Dreier | 87b8167 | 2005-08-18 13:39:31 -0700 | [diff] [blame] | 984 | goto err_out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | return 0; |
| 987 | |
Roland Dreier | 87b8167 | 2005-08-18 13:39:31 -0700 | [diff] [blame] | 988 | err_out: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | kfree(qp->wrid); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | return err; |
| 991 | } |
| 992 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 993 | static void mthca_free_wqe_buf(struct mthca_dev *dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | struct mthca_qp *qp) |
| 995 | { |
Roland Dreier | 87b8167 | 2005-08-18 13:39:31 -0700 | [diff] [blame] | 996 | mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset + |
| 997 | (qp->sq.max << qp->sq.wqe_shift)), |
| 998 | &qp->queue, qp->is_direct, &qp->mr); |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 999 | kfree(qp->wrid); |
| 1000 | } |
| 1001 | |
| 1002 | static int mthca_map_memfree(struct mthca_dev *dev, |
| 1003 | struct mthca_qp *qp) |
| 1004 | { |
| 1005 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1006 | |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 1007 | if (mthca_is_memfree(dev)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn); |
| 1009 | if (ret) |
| 1010 | return ret; |
| 1011 | |
| 1012 | ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn); |
| 1013 | if (ret) |
| 1014 | goto err_qpc; |
| 1015 | |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 1016 | ret = mthca_table_get(dev, dev->qp_table.rdb_table, |
| 1017 | qp->qpn << dev->qp_table.rdb_shift); |
| 1018 | if (ret) |
| 1019 | goto err_eqpc; |
Roland Dreier | 08aeb14 | 2005-04-16 15:26:34 -0700 | [diff] [blame] | 1020 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1021 | } |
| 1022 | |
| 1023 | return 0; |
| 1024 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1025 | err_eqpc: |
| 1026 | mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); |
| 1027 | |
| 1028 | err_qpc: |
| 1029 | mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); |
| 1030 | |
| 1031 | return ret; |
| 1032 | } |
| 1033 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1034 | static void mthca_unmap_memfree(struct mthca_dev *dev, |
| 1035 | struct mthca_qp *qp) |
| 1036 | { |
| 1037 | mthca_table_put(dev, dev->qp_table.rdb_table, |
| 1038 | qp->qpn << dev->qp_table.rdb_shift); |
| 1039 | mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); |
| 1040 | mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); |
| 1041 | } |
| 1042 | |
| 1043 | static int mthca_alloc_memfree(struct mthca_dev *dev, |
| 1044 | struct mthca_qp *qp) |
| 1045 | { |
| 1046 | int ret = 0; |
| 1047 | |
| 1048 | if (mthca_is_memfree(dev)) { |
| 1049 | qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ, |
| 1050 | qp->qpn, &qp->rq.db); |
| 1051 | if (qp->rq.db_index < 0) |
| 1052 | return ret; |
| 1053 | |
| 1054 | qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ, |
| 1055 | qp->qpn, &qp->sq.db); |
| 1056 | if (qp->sq.db_index < 0) |
| 1057 | mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); |
| 1058 | } |
| 1059 | |
| 1060 | return ret; |
| 1061 | } |
| 1062 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1063 | static void mthca_free_memfree(struct mthca_dev *dev, |
| 1064 | struct mthca_qp *qp) |
| 1065 | { |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 1066 | if (mthca_is_memfree(dev)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index); |
| 1068 | mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1069 | } |
| 1070 | } |
| 1071 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1072 | static int mthca_alloc_qp_common(struct mthca_dev *dev, |
| 1073 | struct mthca_pd *pd, |
| 1074 | struct mthca_cq *send_cq, |
| 1075 | struct mthca_cq *recv_cq, |
| 1076 | enum ib_sig_type send_policy, |
| 1077 | struct mthca_qp *qp) |
| 1078 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1079 | int ret; |
| 1080 | int i; |
| 1081 | |
| 1082 | atomic_set(&qp->refcount, 1); |
Michael S. Tsirkin | 30a7e8e | 2005-09-07 09:45:00 -0700 | [diff] [blame] | 1083 | init_waitqueue_head(&qp->wait); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1084 | qp->state = IB_QPS_RESET; |
| 1085 | qp->atomic_rd_en = 0; |
| 1086 | qp->resp_depth = 0; |
| 1087 | qp->sq_policy = send_policy; |
| 1088 | mthca_wq_init(&qp->sq); |
| 1089 | mthca_wq_init(&qp->rq); |
| 1090 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1091 | ret = mthca_map_memfree(dev, qp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1092 | if (ret) |
| 1093 | return ret; |
| 1094 | |
| 1095 | ret = mthca_alloc_wqe_buf(dev, pd, qp); |
| 1096 | if (ret) { |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1097 | mthca_unmap_memfree(dev, qp); |
| 1098 | return ret; |
| 1099 | } |
| 1100 | |
Jack Morgenstein | 77369ed | 2005-11-09 11:26:07 -0800 | [diff] [blame] | 1101 | mthca_adjust_qp_caps(dev, pd, qp); |
| 1102 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1103 | /* |
| 1104 | * If this is a userspace QP, we're done now. The doorbells |
| 1105 | * will be allocated and buffers will be initialized in |
| 1106 | * userspace. |
| 1107 | */ |
| 1108 | if (pd->ibpd.uobject) |
| 1109 | return 0; |
| 1110 | |
| 1111 | ret = mthca_alloc_memfree(dev, qp); |
| 1112 | if (ret) { |
| 1113 | mthca_free_wqe_buf(dev, qp); |
| 1114 | mthca_unmap_memfree(dev, qp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | return ret; |
| 1116 | } |
| 1117 | |
Roland Dreier | d10ddbf | 2005-04-16 15:26:32 -0700 | [diff] [blame] | 1118 | if (mthca_is_memfree(dev)) { |
Roland Dreier | ddf841f | 2005-04-16 15:26:33 -0700 | [diff] [blame] | 1119 | struct mthca_next_seg *next; |
| 1120 | struct mthca_data_seg *scatter; |
| 1121 | int size = (sizeof (struct mthca_next_seg) + |
| 1122 | qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16; |
| 1123 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1124 | for (i = 0; i < qp->rq.max; ++i) { |
Roland Dreier | ddf841f | 2005-04-16 15:26:33 -0700 | [diff] [blame] | 1125 | next = get_recv_wqe(qp, i); |
| 1126 | next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) << |
| 1127 | qp->rq.wqe_shift); |
| 1128 | next->ee_nds = cpu_to_be32(size); |
| 1129 | |
| 1130 | for (scatter = (void *) (next + 1); |
| 1131 | (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift); |
| 1132 | ++scatter) |
| 1133 | scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | for (i = 0; i < qp->sq.max; ++i) { |
Roland Dreier | ddf841f | 2005-04-16 15:26:33 -0700 | [diff] [blame] | 1137 | next = get_send_wqe(qp, i); |
| 1138 | next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) << |
| 1139 | qp->sq.wqe_shift) + |
| 1140 | qp->send_wqe_offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | } |
| 1142 | } |
| 1143 | |
Roland Dreier | d6cff02 | 2005-09-13 10:41:03 -0700 | [diff] [blame] | 1144 | qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); |
| 1145 | qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); |
| 1146 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | return 0; |
| 1148 | } |
| 1149 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1150 | static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap, |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 1151 | struct mthca_pd *pd, struct mthca_qp *qp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1152 | { |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 1153 | int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz); |
| 1154 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1155 | /* Sanity check QP size before proceeding */ |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 1156 | if (cap->max_send_wr > dev->limits.max_wqes || |
| 1157 | cap->max_recv_wr > dev->limits.max_wqes || |
| 1158 | cap->max_send_sge > dev->limits.max_sg || |
| 1159 | cap->max_recv_sge > dev->limits.max_sg || |
| 1160 | cap->max_inline_data > mthca_max_inline_data(pd, max_data_size)) |
| 1161 | return -EINVAL; |
| 1162 | |
| 1163 | /* |
| 1164 | * For MLX transport we need 2 extra S/G entries: |
| 1165 | * one for the header and one for the checksum at the end |
| 1166 | */ |
| 1167 | if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg) |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1168 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1170 | if (mthca_is_memfree(dev)) { |
| 1171 | qp->rq.max = cap->max_recv_wr ? |
| 1172 | roundup_pow_of_two(cap->max_recv_wr) : 0; |
| 1173 | qp->sq.max = cap->max_send_wr ? |
| 1174 | roundup_pow_of_two(cap->max_send_wr) : 0; |
| 1175 | } else { |
| 1176 | qp->rq.max = cap->max_recv_wr; |
| 1177 | qp->sq.max = cap->max_send_wr; |
| 1178 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1180 | qp->rq.max_gs = cap->max_recv_sge; |
| 1181 | qp->sq.max_gs = max_t(int, cap->max_send_sge, |
| 1182 | ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE, |
| 1183 | MTHCA_INLINE_CHUNK_SIZE) / |
| 1184 | sizeof (struct mthca_data_seg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1186 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | int mthca_alloc_qp(struct mthca_dev *dev, |
| 1190 | struct mthca_pd *pd, |
| 1191 | struct mthca_cq *send_cq, |
| 1192 | struct mthca_cq *recv_cq, |
| 1193 | enum ib_qp_type type, |
| 1194 | enum ib_sig_type send_policy, |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1195 | struct ib_qp_cap *cap, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1196 | struct mthca_qp *qp) |
| 1197 | { |
| 1198 | int err; |
| 1199 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | switch (type) { |
| 1201 | case IB_QPT_RC: qp->transport = RC; break; |
| 1202 | case IB_QPT_UC: qp->transport = UC; break; |
| 1203 | case IB_QPT_UD: qp->transport = UD; break; |
| 1204 | default: return -EINVAL; |
| 1205 | } |
| 1206 | |
Jack Morgenstein | b3f6496 | 2006-03-22 09:52:31 +0200 | [diff] [blame] | 1207 | err = mthca_set_qp_size(dev, cap, pd, qp); |
| 1208 | if (err) |
| 1209 | return err; |
| 1210 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | qp->qpn = mthca_alloc(&dev->qp_table.alloc); |
| 1212 | if (qp->qpn == -1) |
| 1213 | return -ENOMEM; |
| 1214 | |
| 1215 | err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, |
| 1216 | send_policy, qp); |
| 1217 | if (err) { |
| 1218 | mthca_free(&dev->qp_table.alloc, qp->qpn); |
| 1219 | return err; |
| 1220 | } |
| 1221 | |
| 1222 | spin_lock_irq(&dev->qp_table.lock); |
| 1223 | mthca_array_set(&dev->qp_table.qp, |
| 1224 | qp->qpn & (dev->limits.num_qps - 1), qp); |
| 1225 | spin_unlock_irq(&dev->qp_table.lock); |
| 1226 | |
| 1227 | return 0; |
| 1228 | } |
| 1229 | |
| 1230 | int mthca_alloc_sqp(struct mthca_dev *dev, |
| 1231 | struct mthca_pd *pd, |
| 1232 | struct mthca_cq *send_cq, |
| 1233 | struct mthca_cq *recv_cq, |
| 1234 | enum ib_sig_type send_policy, |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1235 | struct ib_qp_cap *cap, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1236 | int qpn, |
| 1237 | int port, |
| 1238 | struct mthca_sqp *sqp) |
| 1239 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1; |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1241 | int err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1242 | |
Jack Morgenstein | b3f6496 | 2006-03-22 09:52:31 +0200 | [diff] [blame] | 1243 | sqp->qp.transport = MLX; |
Jack Morgenstein | 5b3bc7a | 2006-01-06 12:57:30 -0800 | [diff] [blame] | 1244 | err = mthca_set_qp_size(dev, cap, pd, &sqp->qp); |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1245 | if (err) |
| 1246 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1247 | |
| 1248 | sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE; |
| 1249 | sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size, |
| 1250 | &sqp->header_dma, GFP_KERNEL); |
| 1251 | if (!sqp->header_buf) |
| 1252 | return -ENOMEM; |
| 1253 | |
| 1254 | spin_lock_irq(&dev->qp_table.lock); |
| 1255 | if (mthca_array_get(&dev->qp_table.qp, mqpn)) |
| 1256 | err = -EBUSY; |
| 1257 | else |
| 1258 | mthca_array_set(&dev->qp_table.qp, mqpn, sqp); |
| 1259 | spin_unlock_irq(&dev->qp_table.lock); |
| 1260 | |
| 1261 | if (err) |
| 1262 | goto err_out; |
| 1263 | |
| 1264 | sqp->port = port; |
| 1265 | sqp->qp.qpn = mqpn; |
| 1266 | sqp->qp.transport = MLX; |
| 1267 | |
| 1268 | err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, |
| 1269 | send_policy, &sqp->qp); |
| 1270 | if (err) |
| 1271 | goto err_out_free; |
| 1272 | |
| 1273 | atomic_inc(&pd->sqp_count); |
| 1274 | |
| 1275 | return 0; |
| 1276 | |
| 1277 | err_out_free: |
| 1278 | /* |
| 1279 | * Lock CQs here, so that CQ polling code can do QP lookup |
| 1280 | * without taking a lock. |
| 1281 | */ |
| 1282 | spin_lock_irq(&send_cq->lock); |
| 1283 | if (send_cq != recv_cq) |
| 1284 | spin_lock(&recv_cq->lock); |
| 1285 | |
| 1286 | spin_lock(&dev->qp_table.lock); |
| 1287 | mthca_array_clear(&dev->qp_table.qp, mqpn); |
| 1288 | spin_unlock(&dev->qp_table.lock); |
| 1289 | |
| 1290 | if (send_cq != recv_cq) |
| 1291 | spin_unlock(&recv_cq->lock); |
| 1292 | spin_unlock_irq(&send_cq->lock); |
| 1293 | |
| 1294 | err_out: |
| 1295 | dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size, |
| 1296 | sqp->header_buf, sqp->header_dma); |
| 1297 | |
| 1298 | return err; |
| 1299 | } |
| 1300 | |
| 1301 | void mthca_free_qp(struct mthca_dev *dev, |
| 1302 | struct mthca_qp *qp) |
| 1303 | { |
| 1304 | u8 status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1305 | struct mthca_cq *send_cq; |
| 1306 | struct mthca_cq *recv_cq; |
| 1307 | |
| 1308 | send_cq = to_mcq(qp->ibqp.send_cq); |
| 1309 | recv_cq = to_mcq(qp->ibqp.recv_cq); |
| 1310 | |
| 1311 | /* |
| 1312 | * Lock CQs here, so that CQ polling code can do QP lookup |
| 1313 | * without taking a lock. |
| 1314 | */ |
| 1315 | spin_lock_irq(&send_cq->lock); |
| 1316 | if (send_cq != recv_cq) |
| 1317 | spin_lock(&recv_cq->lock); |
| 1318 | |
| 1319 | spin_lock(&dev->qp_table.lock); |
| 1320 | mthca_array_clear(&dev->qp_table.qp, |
| 1321 | qp->qpn & (dev->limits.num_qps - 1)); |
| 1322 | spin_unlock(&dev->qp_table.lock); |
| 1323 | |
| 1324 | if (send_cq != recv_cq) |
| 1325 | spin_unlock(&recv_cq->lock); |
| 1326 | spin_unlock_irq(&send_cq->lock); |
| 1327 | |
| 1328 | atomic_dec(&qp->refcount); |
| 1329 | wait_event(qp->wait, !atomic_read(&qp->refcount)); |
| 1330 | |
| 1331 | if (qp->state != IB_QPS_RESET) |
Roland Dreier | d844183 | 2006-02-13 16:30:18 -0800 | [diff] [blame] | 1332 | mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0, |
| 1333 | NULL, 0, &status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1334 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1335 | /* |
| 1336 | * If this is a userspace QP, the buffers, MR, CQs and so on |
| 1337 | * will be cleaned up in userspace, so all we have to do is |
| 1338 | * unref the mem-free tables and free the QPN in our table. |
| 1339 | */ |
| 1340 | if (!qp->ibqp.uobject) { |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 1341 | mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn, |
| 1342 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1343 | if (qp->ibqp.send_cq != qp->ibqp.recv_cq) |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 1344 | mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn, |
| 1345 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1347 | mthca_free_memfree(dev, qp); |
| 1348 | mthca_free_wqe_buf(dev, qp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1349 | } |
| 1350 | |
Roland Dreier | 80c8ec2 | 2005-07-07 17:57:20 -0700 | [diff] [blame] | 1351 | mthca_unmap_memfree(dev, qp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | |
| 1353 | if (is_sqp(dev, qp)) { |
| 1354 | atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count)); |
| 1355 | dma_free_coherent(&dev->pdev->dev, |
| 1356 | to_msqp(qp)->header_buf_size, |
| 1357 | to_msqp(qp)->header_buf, |
| 1358 | to_msqp(qp)->header_dma); |
| 1359 | } else |
| 1360 | mthca_free(&dev->qp_table.alloc, qp->qpn); |
| 1361 | } |
| 1362 | |
| 1363 | /* Create UD header for an MLX send and build a data segment for it */ |
| 1364 | static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, |
| 1365 | int ind, struct ib_send_wr *wr, |
| 1366 | struct mthca_mlx_seg *mlx, |
| 1367 | struct mthca_data_seg *data) |
| 1368 | { |
| 1369 | int header_size; |
| 1370 | int err; |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1371 | u16 pkey; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | |
| 1373 | ib_ud_header_init(256, /* assume a MAD */ |
Michael S. Tsirkin | 9eacee2 | 2006-01-12 15:55:41 -0800 | [diff] [blame] | 1374 | mthca_ah_grh_present(to_mah(wr->wr.ud.ah)), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | &sqp->ud_header); |
| 1376 | |
| 1377 | err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header); |
| 1378 | if (err) |
| 1379 | return err; |
| 1380 | mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1); |
| 1381 | mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) | |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1382 | (sqp->ud_header.lrh.destination_lid == |
| 1383 | IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1384 | (sqp->ud_header.lrh.service_level << 8)); |
| 1385 | mlx->rlid = sqp->ud_header.lrh.destination_lid; |
| 1386 | mlx->vcrc = 0; |
| 1387 | |
| 1388 | switch (wr->opcode) { |
| 1389 | case IB_WR_SEND: |
| 1390 | sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; |
| 1391 | sqp->ud_header.immediate_present = 0; |
| 1392 | break; |
| 1393 | case IB_WR_SEND_WITH_IMM: |
| 1394 | sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; |
| 1395 | sqp->ud_header.immediate_present = 1; |
| 1396 | sqp->ud_header.immediate_data = wr->imm_data; |
| 1397 | break; |
| 1398 | default: |
| 1399 | return -EINVAL; |
| 1400 | } |
| 1401 | |
| 1402 | sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1403 | if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) |
| 1404 | sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1405 | sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); |
| 1406 | if (!sqp->qp.ibqp.qp_num) |
| 1407 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1408 | sqp->pkey_index, &pkey); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | else |
| 1410 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1411 | wr->wr.ud.pkey_index, &pkey); |
| 1412 | sqp->ud_header.bth.pkey = cpu_to_be16(pkey); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); |
| 1414 | sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); |
| 1415 | sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? |
| 1416 | sqp->qkey : wr->wr.ud.remote_qkey); |
| 1417 | sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); |
| 1418 | |
| 1419 | header_size = ib_ud_header_pack(&sqp->ud_header, |
| 1420 | sqp->header_buf + |
| 1421 | ind * MTHCA_UD_HEADER_SIZE); |
| 1422 | |
| 1423 | data->byte_count = cpu_to_be32(header_size); |
| 1424 | data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey); |
| 1425 | data->addr = cpu_to_be64(sqp->header_dma + |
| 1426 | ind * MTHCA_UD_HEADER_SIZE); |
| 1427 | |
| 1428 | return 0; |
| 1429 | } |
| 1430 | |
| 1431 | static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq, |
| 1432 | struct ib_cq *ib_cq) |
| 1433 | { |
| 1434 | unsigned cur; |
| 1435 | struct mthca_cq *cq; |
| 1436 | |
| 1437 | cur = wq->head - wq->tail; |
| 1438 | if (likely(cur + nreq < wq->max)) |
| 1439 | return 0; |
| 1440 | |
| 1441 | cq = to_mcq(ib_cq); |
| 1442 | spin_lock(&cq->lock); |
| 1443 | cur = wq->head - wq->tail; |
| 1444 | spin_unlock(&cq->lock); |
| 1445 | |
| 1446 | return cur + nreq >= wq->max; |
| 1447 | } |
| 1448 | |
| 1449 | int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
| 1450 | struct ib_send_wr **bad_wr) |
| 1451 | { |
| 1452 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 1453 | struct mthca_qp *qp = to_mqp(ibqp); |
| 1454 | void *wqe; |
| 1455 | void *prev_wqe; |
| 1456 | unsigned long flags; |
| 1457 | int err = 0; |
| 1458 | int nreq; |
| 1459 | int i; |
| 1460 | int size; |
| 1461 | int size0 = 0; |
| 1462 | u32 f0 = 0; |
| 1463 | int ind; |
| 1464 | u8 op0 = 0; |
| 1465 | |
| 1466 | spin_lock_irqsave(&qp->sq.lock, flags); |
| 1467 | |
| 1468 | /* XXX check that state is OK to post send */ |
| 1469 | |
| 1470 | ind = qp->sq.next_ind; |
| 1471 | |
| 1472 | for (nreq = 0; wr; ++nreq, wr = wr->next) { |
| 1473 | if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { |
| 1474 | mthca_err(dev, "SQ %06x full (%u head, %u tail," |
| 1475 | " %d max, %d nreq)\n", qp->qpn, |
| 1476 | qp->sq.head, qp->sq.tail, |
| 1477 | qp->sq.max, nreq); |
| 1478 | err = -ENOMEM; |
| 1479 | *bad_wr = wr; |
| 1480 | goto out; |
| 1481 | } |
| 1482 | |
| 1483 | wqe = get_send_wqe(qp, ind); |
| 1484 | prev_wqe = qp->sq.last; |
| 1485 | qp->sq.last = wqe; |
| 1486 | |
| 1487 | ((struct mthca_next_seg *) wqe)->nda_op = 0; |
| 1488 | ((struct mthca_next_seg *) wqe)->ee_nds = 0; |
| 1489 | ((struct mthca_next_seg *) wqe)->flags = |
| 1490 | ((wr->send_flags & IB_SEND_SIGNALED) ? |
| 1491 | cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | |
| 1492 | ((wr->send_flags & IB_SEND_SOLICITED) ? |
| 1493 | cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | |
| 1494 | cpu_to_be32(1); |
| 1495 | if (wr->opcode == IB_WR_SEND_WITH_IMM || |
| 1496 | wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) |
Roland Dreier | 3fba231 | 2005-04-16 15:26:16 -0700 | [diff] [blame] | 1497 | ((struct mthca_next_seg *) wqe)->imm = wr->imm_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1498 | |
| 1499 | wqe += sizeof (struct mthca_next_seg); |
| 1500 | size = sizeof (struct mthca_next_seg) / 16; |
| 1501 | |
| 1502 | switch (qp->transport) { |
| 1503 | case RC: |
| 1504 | switch (wr->opcode) { |
| 1505 | case IB_WR_ATOMIC_CMP_AND_SWP: |
| 1506 | case IB_WR_ATOMIC_FETCH_AND_ADD: |
| 1507 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1508 | cpu_to_be64(wr->wr.atomic.remote_addr); |
| 1509 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1510 | cpu_to_be32(wr->wr.atomic.rkey); |
| 1511 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1512 | |
| 1513 | wqe += sizeof (struct mthca_raddr_seg); |
| 1514 | |
| 1515 | if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { |
| 1516 | ((struct mthca_atomic_seg *) wqe)->swap_add = |
| 1517 | cpu_to_be64(wr->wr.atomic.swap); |
| 1518 | ((struct mthca_atomic_seg *) wqe)->compare = |
| 1519 | cpu_to_be64(wr->wr.atomic.compare_add); |
| 1520 | } else { |
| 1521 | ((struct mthca_atomic_seg *) wqe)->swap_add = |
| 1522 | cpu_to_be64(wr->wr.atomic.compare_add); |
| 1523 | ((struct mthca_atomic_seg *) wqe)->compare = 0; |
| 1524 | } |
| 1525 | |
| 1526 | wqe += sizeof (struct mthca_atomic_seg); |
Michael S. Tsirkin | 62abb84 | 2005-11-09 11:30:14 -0800 | [diff] [blame] | 1527 | size += (sizeof (struct mthca_raddr_seg) + |
| 1528 | sizeof (struct mthca_atomic_seg)) / 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1529 | break; |
| 1530 | |
| 1531 | case IB_WR_RDMA_WRITE: |
| 1532 | case IB_WR_RDMA_WRITE_WITH_IMM: |
| 1533 | case IB_WR_RDMA_READ: |
| 1534 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1535 | cpu_to_be64(wr->wr.rdma.remote_addr); |
| 1536 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1537 | cpu_to_be32(wr->wr.rdma.rkey); |
| 1538 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1539 | wqe += sizeof (struct mthca_raddr_seg); |
| 1540 | size += sizeof (struct mthca_raddr_seg) / 16; |
| 1541 | break; |
| 1542 | |
| 1543 | default: |
| 1544 | /* No extra segments required for sends */ |
| 1545 | break; |
| 1546 | } |
| 1547 | |
| 1548 | break; |
| 1549 | |
Roland Dreier | 9e6970b | 2005-06-27 14:36:42 -0700 | [diff] [blame] | 1550 | case UC: |
| 1551 | switch (wr->opcode) { |
| 1552 | case IB_WR_RDMA_WRITE: |
| 1553 | case IB_WR_RDMA_WRITE_WITH_IMM: |
| 1554 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1555 | cpu_to_be64(wr->wr.rdma.remote_addr); |
| 1556 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1557 | cpu_to_be32(wr->wr.rdma.rkey); |
| 1558 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1559 | wqe += sizeof (struct mthca_raddr_seg); |
| 1560 | size += sizeof (struct mthca_raddr_seg) / 16; |
| 1561 | break; |
| 1562 | |
| 1563 | default: |
| 1564 | /* No extra segments required for sends */ |
| 1565 | break; |
| 1566 | } |
| 1567 | |
| 1568 | break; |
| 1569 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1570 | case UD: |
| 1571 | ((struct mthca_tavor_ud_seg *) wqe)->lkey = |
| 1572 | cpu_to_be32(to_mah(wr->wr.ud.ah)->key); |
| 1573 | ((struct mthca_tavor_ud_seg *) wqe)->av_addr = |
| 1574 | cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma); |
| 1575 | ((struct mthca_tavor_ud_seg *) wqe)->dqpn = |
| 1576 | cpu_to_be32(wr->wr.ud.remote_qpn); |
| 1577 | ((struct mthca_tavor_ud_seg *) wqe)->qkey = |
| 1578 | cpu_to_be32(wr->wr.ud.remote_qkey); |
| 1579 | |
| 1580 | wqe += sizeof (struct mthca_tavor_ud_seg); |
| 1581 | size += sizeof (struct mthca_tavor_ud_seg) / 16; |
| 1582 | break; |
| 1583 | |
| 1584 | case MLX: |
| 1585 | err = build_mlx_header(dev, to_msqp(qp), ind, wr, |
| 1586 | wqe - sizeof (struct mthca_next_seg), |
| 1587 | wqe); |
| 1588 | if (err) { |
| 1589 | *bad_wr = wr; |
| 1590 | goto out; |
| 1591 | } |
| 1592 | wqe += sizeof (struct mthca_data_seg); |
| 1593 | size += sizeof (struct mthca_data_seg) / 16; |
| 1594 | break; |
| 1595 | } |
| 1596 | |
| 1597 | if (wr->num_sge > qp->sq.max_gs) { |
| 1598 | mthca_err(dev, "too many gathers\n"); |
| 1599 | err = -EINVAL; |
| 1600 | *bad_wr = wr; |
| 1601 | goto out; |
| 1602 | } |
| 1603 | |
| 1604 | for (i = 0; i < wr->num_sge; ++i) { |
| 1605 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 1606 | cpu_to_be32(wr->sg_list[i].length); |
| 1607 | ((struct mthca_data_seg *) wqe)->lkey = |
| 1608 | cpu_to_be32(wr->sg_list[i].lkey); |
| 1609 | ((struct mthca_data_seg *) wqe)->addr = |
| 1610 | cpu_to_be64(wr->sg_list[i].addr); |
| 1611 | wqe += sizeof (struct mthca_data_seg); |
| 1612 | size += sizeof (struct mthca_data_seg) / 16; |
| 1613 | } |
| 1614 | |
| 1615 | /* Add one more inline data segment for ICRC */ |
| 1616 | if (qp->transport == MLX) { |
| 1617 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 1618 | cpu_to_be32((1 << 31) | 4); |
| 1619 | ((u32 *) wqe)[1] = 0; |
| 1620 | wqe += sizeof (struct mthca_data_seg); |
| 1621 | size += sizeof (struct mthca_data_seg) / 16; |
| 1622 | } |
| 1623 | |
| 1624 | qp->wrid[ind + qp->rq.max] = wr->wr_id; |
| 1625 | |
| 1626 | if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { |
| 1627 | mthca_err(dev, "opcode invalid\n"); |
| 1628 | err = -EINVAL; |
| 1629 | *bad_wr = wr; |
| 1630 | goto out; |
| 1631 | } |
| 1632 | |
Roland Dreier | d6cff02 | 2005-09-13 10:41:03 -0700 | [diff] [blame] | 1633 | ((struct mthca_next_seg *) prev_wqe)->nda_op = |
| 1634 | cpu_to_be32(((ind << qp->sq.wqe_shift) + |
| 1635 | qp->send_wqe_offset) | |
| 1636 | mthca_opcode[wr->opcode]); |
| 1637 | wmb(); |
| 1638 | ((struct mthca_next_seg *) prev_wqe)->ee_nds = |
Dotan Barak | 7667abd1 | 2006-02-27 21:02:00 -0800 | [diff] [blame] | 1639 | cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size | |
| 1640 | ((wr->send_flags & IB_SEND_FENCE) ? |
| 1641 | MTHCA_NEXT_FENCE : 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1642 | |
| 1643 | if (!size0) { |
| 1644 | size0 = size; |
| 1645 | op0 = mthca_opcode[wr->opcode]; |
| 1646 | } |
| 1647 | |
| 1648 | ++ind; |
| 1649 | if (unlikely(ind >= qp->sq.max)) |
| 1650 | ind -= qp->sq.max; |
| 1651 | } |
| 1652 | |
| 1653 | out: |
| 1654 | if (likely(nreq)) { |
Sean Hefty | 97f52eb | 2005-08-13 21:05:57 -0700 | [diff] [blame] | 1655 | __be32 doorbell[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | |
| 1657 | doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) + |
| 1658 | qp->send_wqe_offset) | f0 | op0); |
| 1659 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); |
| 1660 | |
| 1661 | wmb(); |
| 1662 | |
| 1663 | mthca_write64(doorbell, |
| 1664 | dev->kar + MTHCA_SEND_DOORBELL, |
| 1665 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); |
| 1666 | } |
| 1667 | |
| 1668 | qp->sq.next_ind = ind; |
| 1669 | qp->sq.head += nreq; |
| 1670 | |
| 1671 | spin_unlock_irqrestore(&qp->sq.lock, flags); |
| 1672 | return err; |
| 1673 | } |
| 1674 | |
| 1675 | int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, |
| 1676 | struct ib_recv_wr **bad_wr) |
| 1677 | { |
| 1678 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 1679 | struct mthca_qp *qp = to_mqp(ibqp); |
Michael S. Tsirkin | ae57e24 | 2005-11-09 14:59:57 -0800 | [diff] [blame] | 1680 | __be32 doorbell[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1681 | unsigned long flags; |
| 1682 | int err = 0; |
| 1683 | int nreq; |
| 1684 | int i; |
| 1685 | int size; |
| 1686 | int size0 = 0; |
| 1687 | int ind; |
| 1688 | void *wqe; |
| 1689 | void *prev_wqe; |
| 1690 | |
| 1691 | spin_lock_irqsave(&qp->rq.lock, flags); |
| 1692 | |
| 1693 | /* XXX check that state is OK to post receive */ |
| 1694 | |
| 1695 | ind = qp->rq.next_ind; |
| 1696 | |
| 1697 | for (nreq = 0; wr; ++nreq, wr = wr->next) { |
Michael S. Tsirkin | ae57e24 | 2005-11-09 14:59:57 -0800 | [diff] [blame] | 1698 | if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { |
| 1699 | nreq = 0; |
| 1700 | |
| 1701 | doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); |
| 1702 | doorbell[1] = cpu_to_be32(qp->qpn << 8); |
| 1703 | |
| 1704 | wmb(); |
| 1705 | |
| 1706 | mthca_write64(doorbell, |
| 1707 | dev->kar + MTHCA_RECEIVE_DOORBELL, |
| 1708 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); |
| 1709 | |
| 1710 | qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB; |
| 1711 | size0 = 0; |
| 1712 | } |
| 1713 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1714 | if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { |
| 1715 | mthca_err(dev, "RQ %06x full (%u head, %u tail," |
| 1716 | " %d max, %d nreq)\n", qp->qpn, |
| 1717 | qp->rq.head, qp->rq.tail, |
| 1718 | qp->rq.max, nreq); |
| 1719 | err = -ENOMEM; |
| 1720 | *bad_wr = wr; |
| 1721 | goto out; |
| 1722 | } |
| 1723 | |
| 1724 | wqe = get_recv_wqe(qp, ind); |
| 1725 | prev_wqe = qp->rq.last; |
| 1726 | qp->rq.last = wqe; |
| 1727 | |
| 1728 | ((struct mthca_next_seg *) wqe)->nda_op = 0; |
| 1729 | ((struct mthca_next_seg *) wqe)->ee_nds = |
| 1730 | cpu_to_be32(MTHCA_NEXT_DBD); |
| 1731 | ((struct mthca_next_seg *) wqe)->flags = 0; |
| 1732 | |
| 1733 | wqe += sizeof (struct mthca_next_seg); |
| 1734 | size = sizeof (struct mthca_next_seg) / 16; |
| 1735 | |
| 1736 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { |
| 1737 | err = -EINVAL; |
| 1738 | *bad_wr = wr; |
| 1739 | goto out; |
| 1740 | } |
| 1741 | |
| 1742 | for (i = 0; i < wr->num_sge; ++i) { |
| 1743 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 1744 | cpu_to_be32(wr->sg_list[i].length); |
| 1745 | ((struct mthca_data_seg *) wqe)->lkey = |
| 1746 | cpu_to_be32(wr->sg_list[i].lkey); |
| 1747 | ((struct mthca_data_seg *) wqe)->addr = |
| 1748 | cpu_to_be64(wr->sg_list[i].addr); |
| 1749 | wqe += sizeof (struct mthca_data_seg); |
| 1750 | size += sizeof (struct mthca_data_seg) / 16; |
| 1751 | } |
| 1752 | |
| 1753 | qp->wrid[ind] = wr->wr_id; |
| 1754 | |
Roland Dreier | d6cff02 | 2005-09-13 10:41:03 -0700 | [diff] [blame] | 1755 | ((struct mthca_next_seg *) prev_wqe)->nda_op = |
| 1756 | cpu_to_be32((ind << qp->rq.wqe_shift) | 1); |
| 1757 | wmb(); |
| 1758 | ((struct mthca_next_seg *) prev_wqe)->ee_nds = |
| 1759 | cpu_to_be32(MTHCA_NEXT_DBD | size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1760 | |
| 1761 | if (!size0) |
| 1762 | size0 = size; |
| 1763 | |
| 1764 | ++ind; |
| 1765 | if (unlikely(ind >= qp->rq.max)) |
| 1766 | ind -= qp->rq.max; |
| 1767 | } |
| 1768 | |
| 1769 | out: |
| 1770 | if (likely(nreq)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1771 | doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); |
| 1772 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq); |
| 1773 | |
| 1774 | wmb(); |
| 1775 | |
| 1776 | mthca_write64(doorbell, |
| 1777 | dev->kar + MTHCA_RECEIVE_DOORBELL, |
| 1778 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); |
| 1779 | } |
| 1780 | |
| 1781 | qp->rq.next_ind = ind; |
| 1782 | qp->rq.head += nreq; |
| 1783 | |
| 1784 | spin_unlock_irqrestore(&qp->rq.lock, flags); |
| 1785 | return err; |
| 1786 | } |
| 1787 | |
| 1788 | int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
| 1789 | struct ib_send_wr **bad_wr) |
| 1790 | { |
| 1791 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 1792 | struct mthca_qp *qp = to_mqp(ibqp); |
Michael S. Tsirkin | e0ae9ec | 2005-11-29 11:33:46 -0800 | [diff] [blame] | 1793 | __be32 doorbell[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1794 | void *wqe; |
| 1795 | void *prev_wqe; |
| 1796 | unsigned long flags; |
| 1797 | int err = 0; |
| 1798 | int nreq; |
| 1799 | int i; |
| 1800 | int size; |
| 1801 | int size0 = 0; |
| 1802 | u32 f0 = 0; |
| 1803 | int ind; |
| 1804 | u8 op0 = 0; |
| 1805 | |
| 1806 | spin_lock_irqsave(&qp->sq.lock, flags); |
| 1807 | |
| 1808 | /* XXX check that state is OK to post send */ |
| 1809 | |
| 1810 | ind = qp->sq.head & (qp->sq.max - 1); |
| 1811 | |
| 1812 | for (nreq = 0; wr; ++nreq, wr = wr->next) { |
Michael S. Tsirkin | e0ae9ec | 2005-11-29 11:33:46 -0800 | [diff] [blame] | 1813 | if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) { |
| 1814 | nreq = 0; |
| 1815 | |
| 1816 | doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) | |
| 1817 | ((qp->sq.head & 0xffff) << 8) | |
| 1818 | f0 | op0); |
| 1819 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); |
| 1820 | |
| 1821 | qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB; |
| 1822 | size0 = 0; |
| 1823 | |
| 1824 | /* |
| 1825 | * Make sure that descriptors are written before |
| 1826 | * doorbell record. |
| 1827 | */ |
| 1828 | wmb(); |
| 1829 | *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); |
| 1830 | |
| 1831 | /* |
| 1832 | * Make sure doorbell record is written before we |
| 1833 | * write MMIO send doorbell. |
| 1834 | */ |
| 1835 | wmb(); |
| 1836 | mthca_write64(doorbell, |
| 1837 | dev->kar + MTHCA_SEND_DOORBELL, |
| 1838 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); |
| 1839 | } |
| 1840 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1841 | if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { |
| 1842 | mthca_err(dev, "SQ %06x full (%u head, %u tail," |
| 1843 | " %d max, %d nreq)\n", qp->qpn, |
| 1844 | qp->sq.head, qp->sq.tail, |
| 1845 | qp->sq.max, nreq); |
| 1846 | err = -ENOMEM; |
| 1847 | *bad_wr = wr; |
| 1848 | goto out; |
| 1849 | } |
| 1850 | |
| 1851 | wqe = get_send_wqe(qp, ind); |
| 1852 | prev_wqe = qp->sq.last; |
| 1853 | qp->sq.last = wqe; |
| 1854 | |
| 1855 | ((struct mthca_next_seg *) wqe)->flags = |
| 1856 | ((wr->send_flags & IB_SEND_SIGNALED) ? |
| 1857 | cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | |
| 1858 | ((wr->send_flags & IB_SEND_SOLICITED) ? |
| 1859 | cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | |
| 1860 | cpu_to_be32(1); |
| 1861 | if (wr->opcode == IB_WR_SEND_WITH_IMM || |
| 1862 | wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) |
Roland Dreier | 3fba231 | 2005-04-16 15:26:16 -0700 | [diff] [blame] | 1863 | ((struct mthca_next_seg *) wqe)->imm = wr->imm_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1864 | |
| 1865 | wqe += sizeof (struct mthca_next_seg); |
| 1866 | size = sizeof (struct mthca_next_seg) / 16; |
| 1867 | |
| 1868 | switch (qp->transport) { |
Roland Dreier | ddb934e | 2005-04-16 15:26:23 -0700 | [diff] [blame] | 1869 | case RC: |
| 1870 | switch (wr->opcode) { |
| 1871 | case IB_WR_ATOMIC_CMP_AND_SWP: |
| 1872 | case IB_WR_ATOMIC_FETCH_AND_ADD: |
| 1873 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1874 | cpu_to_be64(wr->wr.atomic.remote_addr); |
| 1875 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1876 | cpu_to_be32(wr->wr.atomic.rkey); |
| 1877 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1878 | |
| 1879 | wqe += sizeof (struct mthca_raddr_seg); |
| 1880 | |
| 1881 | if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { |
| 1882 | ((struct mthca_atomic_seg *) wqe)->swap_add = |
| 1883 | cpu_to_be64(wr->wr.atomic.swap); |
| 1884 | ((struct mthca_atomic_seg *) wqe)->compare = |
| 1885 | cpu_to_be64(wr->wr.atomic.compare_add); |
| 1886 | } else { |
| 1887 | ((struct mthca_atomic_seg *) wqe)->swap_add = |
| 1888 | cpu_to_be64(wr->wr.atomic.compare_add); |
| 1889 | ((struct mthca_atomic_seg *) wqe)->compare = 0; |
| 1890 | } |
| 1891 | |
| 1892 | wqe += sizeof (struct mthca_atomic_seg); |
Michael S. Tsirkin | 62abb84 | 2005-11-09 11:30:14 -0800 | [diff] [blame] | 1893 | size += (sizeof (struct mthca_raddr_seg) + |
| 1894 | sizeof (struct mthca_atomic_seg)) / 16; |
Roland Dreier | ddb934e | 2005-04-16 15:26:23 -0700 | [diff] [blame] | 1895 | break; |
| 1896 | |
Roland Dreier | 9e6970b | 2005-06-27 14:36:42 -0700 | [diff] [blame] | 1897 | case IB_WR_RDMA_READ: |
Roland Dreier | ddb934e | 2005-04-16 15:26:23 -0700 | [diff] [blame] | 1898 | case IB_WR_RDMA_WRITE: |
| 1899 | case IB_WR_RDMA_WRITE_WITH_IMM: |
Roland Dreier | 9e6970b | 2005-06-27 14:36:42 -0700 | [diff] [blame] | 1900 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1901 | cpu_to_be64(wr->wr.rdma.remote_addr); |
| 1902 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1903 | cpu_to_be32(wr->wr.rdma.rkey); |
| 1904 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1905 | wqe += sizeof (struct mthca_raddr_seg); |
| 1906 | size += sizeof (struct mthca_raddr_seg) / 16; |
| 1907 | break; |
| 1908 | |
| 1909 | default: |
| 1910 | /* No extra segments required for sends */ |
| 1911 | break; |
| 1912 | } |
| 1913 | |
| 1914 | break; |
| 1915 | |
| 1916 | case UC: |
| 1917 | switch (wr->opcode) { |
| 1918 | case IB_WR_RDMA_WRITE: |
| 1919 | case IB_WR_RDMA_WRITE_WITH_IMM: |
Roland Dreier | ddb934e | 2005-04-16 15:26:23 -0700 | [diff] [blame] | 1920 | ((struct mthca_raddr_seg *) wqe)->raddr = |
| 1921 | cpu_to_be64(wr->wr.rdma.remote_addr); |
| 1922 | ((struct mthca_raddr_seg *) wqe)->rkey = |
| 1923 | cpu_to_be32(wr->wr.rdma.rkey); |
| 1924 | ((struct mthca_raddr_seg *) wqe)->reserved = 0; |
| 1925 | wqe += sizeof (struct mthca_raddr_seg); |
| 1926 | size += sizeof (struct mthca_raddr_seg) / 16; |
| 1927 | break; |
| 1928 | |
| 1929 | default: |
| 1930 | /* No extra segments required for sends */ |
| 1931 | break; |
| 1932 | } |
| 1933 | |
| 1934 | break; |
| 1935 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1936 | case UD: |
| 1937 | memcpy(((struct mthca_arbel_ud_seg *) wqe)->av, |
| 1938 | to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE); |
| 1939 | ((struct mthca_arbel_ud_seg *) wqe)->dqpn = |
| 1940 | cpu_to_be32(wr->wr.ud.remote_qpn); |
| 1941 | ((struct mthca_arbel_ud_seg *) wqe)->qkey = |
| 1942 | cpu_to_be32(wr->wr.ud.remote_qkey); |
| 1943 | |
| 1944 | wqe += sizeof (struct mthca_arbel_ud_seg); |
| 1945 | size += sizeof (struct mthca_arbel_ud_seg) / 16; |
| 1946 | break; |
| 1947 | |
| 1948 | case MLX: |
| 1949 | err = build_mlx_header(dev, to_msqp(qp), ind, wr, |
| 1950 | wqe - sizeof (struct mthca_next_seg), |
| 1951 | wqe); |
| 1952 | if (err) { |
| 1953 | *bad_wr = wr; |
| 1954 | goto out; |
| 1955 | } |
| 1956 | wqe += sizeof (struct mthca_data_seg); |
| 1957 | size += sizeof (struct mthca_data_seg) / 16; |
| 1958 | break; |
| 1959 | } |
| 1960 | |
| 1961 | if (wr->num_sge > qp->sq.max_gs) { |
| 1962 | mthca_err(dev, "too many gathers\n"); |
| 1963 | err = -EINVAL; |
| 1964 | *bad_wr = wr; |
| 1965 | goto out; |
| 1966 | } |
| 1967 | |
| 1968 | for (i = 0; i < wr->num_sge; ++i) { |
| 1969 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 1970 | cpu_to_be32(wr->sg_list[i].length); |
| 1971 | ((struct mthca_data_seg *) wqe)->lkey = |
| 1972 | cpu_to_be32(wr->sg_list[i].lkey); |
| 1973 | ((struct mthca_data_seg *) wqe)->addr = |
| 1974 | cpu_to_be64(wr->sg_list[i].addr); |
| 1975 | wqe += sizeof (struct mthca_data_seg); |
| 1976 | size += sizeof (struct mthca_data_seg) / 16; |
| 1977 | } |
| 1978 | |
| 1979 | /* Add one more inline data segment for ICRC */ |
| 1980 | if (qp->transport == MLX) { |
| 1981 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 1982 | cpu_to_be32((1 << 31) | 4); |
| 1983 | ((u32 *) wqe)[1] = 0; |
| 1984 | wqe += sizeof (struct mthca_data_seg); |
| 1985 | size += sizeof (struct mthca_data_seg) / 16; |
| 1986 | } |
| 1987 | |
| 1988 | qp->wrid[ind + qp->rq.max] = wr->wr_id; |
| 1989 | |
| 1990 | if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { |
| 1991 | mthca_err(dev, "opcode invalid\n"); |
| 1992 | err = -EINVAL; |
| 1993 | *bad_wr = wr; |
| 1994 | goto out; |
| 1995 | } |
| 1996 | |
Roland Dreier | d6cff02 | 2005-09-13 10:41:03 -0700 | [diff] [blame] | 1997 | ((struct mthca_next_seg *) prev_wqe)->nda_op = |
| 1998 | cpu_to_be32(((ind << qp->sq.wqe_shift) + |
| 1999 | qp->send_wqe_offset) | |
| 2000 | mthca_opcode[wr->opcode]); |
| 2001 | wmb(); |
| 2002 | ((struct mthca_next_seg *) prev_wqe)->ee_nds = |
Dotan Barak | 7667abd1 | 2006-02-27 21:02:00 -0800 | [diff] [blame] | 2003 | cpu_to_be32(MTHCA_NEXT_DBD | size | |
Roland Dreier | b0b3a8e | 2006-03-24 15:47:29 -0800 | [diff] [blame] | 2004 | ((wr->send_flags & IB_SEND_FENCE) ? |
| 2005 | MTHCA_NEXT_FENCE : 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | |
| 2007 | if (!size0) { |
| 2008 | size0 = size; |
| 2009 | op0 = mthca_opcode[wr->opcode]; |
| 2010 | } |
| 2011 | |
| 2012 | ++ind; |
| 2013 | if (unlikely(ind >= qp->sq.max)) |
| 2014 | ind -= qp->sq.max; |
| 2015 | } |
| 2016 | |
| 2017 | out: |
| 2018 | if (likely(nreq)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2019 | doorbell[0] = cpu_to_be32((nreq << 24) | |
| 2020 | ((qp->sq.head & 0xffff) << 8) | |
| 2021 | f0 | op0); |
| 2022 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); |
| 2023 | |
| 2024 | qp->sq.head += nreq; |
| 2025 | |
| 2026 | /* |
| 2027 | * Make sure that descriptors are written before |
| 2028 | * doorbell record. |
| 2029 | */ |
| 2030 | wmb(); |
| 2031 | *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); |
| 2032 | |
| 2033 | /* |
| 2034 | * Make sure doorbell record is written before we |
| 2035 | * write MMIO send doorbell. |
| 2036 | */ |
| 2037 | wmb(); |
| 2038 | mthca_write64(doorbell, |
| 2039 | dev->kar + MTHCA_SEND_DOORBELL, |
| 2040 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); |
| 2041 | } |
| 2042 | |
| 2043 | spin_unlock_irqrestore(&qp->sq.lock, flags); |
| 2044 | return err; |
| 2045 | } |
| 2046 | |
| 2047 | int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, |
| 2048 | struct ib_recv_wr **bad_wr) |
| 2049 | { |
| 2050 | struct mthca_dev *dev = to_mdev(ibqp->device); |
| 2051 | struct mthca_qp *qp = to_mqp(ibqp); |
| 2052 | unsigned long flags; |
| 2053 | int err = 0; |
| 2054 | int nreq; |
| 2055 | int ind; |
| 2056 | int i; |
| 2057 | void *wqe; |
| 2058 | |
Roland Dreier | 2fa5e2e | 2006-02-01 13:38:24 -0800 | [diff] [blame] | 2059 | spin_lock_irqsave(&qp->rq.lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2060 | |
| 2061 | /* XXX check that state is OK to post receive */ |
| 2062 | |
| 2063 | ind = qp->rq.head & (qp->rq.max - 1); |
| 2064 | |
| 2065 | for (nreq = 0; wr; ++nreq, wr = wr->next) { |
| 2066 | if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { |
| 2067 | mthca_err(dev, "RQ %06x full (%u head, %u tail," |
| 2068 | " %d max, %d nreq)\n", qp->qpn, |
| 2069 | qp->rq.head, qp->rq.tail, |
| 2070 | qp->rq.max, nreq); |
| 2071 | err = -ENOMEM; |
| 2072 | *bad_wr = wr; |
| 2073 | goto out; |
| 2074 | } |
| 2075 | |
| 2076 | wqe = get_recv_wqe(qp, ind); |
| 2077 | |
| 2078 | ((struct mthca_next_seg *) wqe)->flags = 0; |
| 2079 | |
| 2080 | wqe += sizeof (struct mthca_next_seg); |
| 2081 | |
| 2082 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { |
| 2083 | err = -EINVAL; |
| 2084 | *bad_wr = wr; |
| 2085 | goto out; |
| 2086 | } |
| 2087 | |
| 2088 | for (i = 0; i < wr->num_sge; ++i) { |
| 2089 | ((struct mthca_data_seg *) wqe)->byte_count = |
| 2090 | cpu_to_be32(wr->sg_list[i].length); |
| 2091 | ((struct mthca_data_seg *) wqe)->lkey = |
| 2092 | cpu_to_be32(wr->sg_list[i].lkey); |
| 2093 | ((struct mthca_data_seg *) wqe)->addr = |
| 2094 | cpu_to_be64(wr->sg_list[i].addr); |
| 2095 | wqe += sizeof (struct mthca_data_seg); |
| 2096 | } |
| 2097 | |
| 2098 | if (i < qp->rq.max_gs) { |
| 2099 | ((struct mthca_data_seg *) wqe)->byte_count = 0; |
Roland Dreier | ddf841f | 2005-04-16 15:26:33 -0700 | [diff] [blame] | 2100 | ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2101 | ((struct mthca_data_seg *) wqe)->addr = 0; |
| 2102 | } |
| 2103 | |
| 2104 | qp->wrid[ind] = wr->wr_id; |
| 2105 | |
| 2106 | ++ind; |
| 2107 | if (unlikely(ind >= qp->rq.max)) |
| 2108 | ind -= qp->rq.max; |
| 2109 | } |
| 2110 | out: |
| 2111 | if (likely(nreq)) { |
| 2112 | qp->rq.head += nreq; |
| 2113 | |
| 2114 | /* |
| 2115 | * Make sure that descriptors are written before |
| 2116 | * doorbell record. |
| 2117 | */ |
| 2118 | wmb(); |
| 2119 | *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff); |
| 2120 | } |
| 2121 | |
| 2122 | spin_unlock_irqrestore(&qp->rq.lock, flags); |
| 2123 | return err; |
| 2124 | } |
| 2125 | |
Roland Dreier | d9b98b0 | 2006-01-31 20:45:51 -0800 | [diff] [blame] | 2126 | void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, |
| 2127 | int index, int *dbd, __be32 *new_wqe) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2128 | { |
| 2129 | struct mthca_next_seg *next; |
| 2130 | |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 2131 | /* |
| 2132 | * For SRQs, all WQEs generate a CQE, so we're always at the |
| 2133 | * end of the doorbell chain. |
| 2134 | */ |
| 2135 | if (qp->ibqp.srq) { |
| 2136 | *new_wqe = 0; |
Roland Dreier | d9b98b0 | 2006-01-31 20:45:51 -0800 | [diff] [blame] | 2137 | return; |
Roland Dreier | ec34a92 | 2005-08-19 10:59:31 -0700 | [diff] [blame] | 2138 | } |
| 2139 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2140 | if (is_send) |
| 2141 | next = get_send_wqe(qp, index); |
| 2142 | else |
| 2143 | next = get_recv_wqe(qp, index); |
| 2144 | |
Roland Dreier | 288bdeb | 2005-08-19 09:19:05 -0700 | [diff] [blame] | 2145 | *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2146 | if (next->ee_nds & cpu_to_be32(0x3f)) |
| 2147 | *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) | |
| 2148 | (next->ee_nds & cpu_to_be32(0x3f)); |
| 2149 | else |
| 2150 | *new_wqe = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2151 | } |
| 2152 | |
| 2153 | int __devinit mthca_init_qp_table(struct mthca_dev *dev) |
| 2154 | { |
| 2155 | int err; |
| 2156 | u8 status; |
| 2157 | int i; |
| 2158 | |
| 2159 | spin_lock_init(&dev->qp_table.lock); |
| 2160 | |
| 2161 | /* |
| 2162 | * We reserve 2 extra QPs per port for the special QPs. The |
| 2163 | * special QP for port 1 has to be even, so round up. |
| 2164 | */ |
| 2165 | dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL; |
| 2166 | err = mthca_alloc_init(&dev->qp_table.alloc, |
| 2167 | dev->limits.num_qps, |
| 2168 | (1 << 24) - 1, |
| 2169 | dev->qp_table.sqp_start + |
| 2170 | MTHCA_MAX_PORTS * 2); |
| 2171 | if (err) |
| 2172 | return err; |
| 2173 | |
| 2174 | err = mthca_array_init(&dev->qp_table.qp, |
| 2175 | dev->limits.num_qps); |
| 2176 | if (err) { |
| 2177 | mthca_alloc_cleanup(&dev->qp_table.alloc); |
| 2178 | return err; |
| 2179 | } |
| 2180 | |
| 2181 | for (i = 0; i < 2; ++i) { |
| 2182 | err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI, |
| 2183 | dev->qp_table.sqp_start + i * 2, |
| 2184 | &status); |
| 2185 | if (err) |
| 2186 | goto err_out; |
| 2187 | if (status) { |
| 2188 | mthca_warn(dev, "CONF_SPECIAL_QP returned " |
| 2189 | "status %02x, aborting.\n", |
| 2190 | status); |
| 2191 | err = -EINVAL; |
| 2192 | goto err_out; |
| 2193 | } |
| 2194 | } |
| 2195 | return 0; |
| 2196 | |
| 2197 | err_out: |
| 2198 | for (i = 0; i < 2; ++i) |
| 2199 | mthca_CONF_SPECIAL_QP(dev, i, 0, &status); |
| 2200 | |
| 2201 | mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); |
| 2202 | mthca_alloc_cleanup(&dev->qp_table.alloc); |
| 2203 | |
| 2204 | return err; |
| 2205 | } |
| 2206 | |
Roland Dreier | e1f7868 | 2006-03-29 09:36:46 -0800 | [diff] [blame] | 2207 | void mthca_cleanup_qp_table(struct mthca_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2208 | { |
| 2209 | int i; |
| 2210 | u8 status; |
| 2211 | |
| 2212 | for (i = 0; i < 2; ++i) |
| 2213 | mthca_CONF_SPECIAL_QP(dev, i, 0, &status); |
| 2214 | |
Michael S. Tsirkin | 71eea47 | 2005-09-20 10:54:48 -0700 | [diff] [blame] | 2215 | mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2216 | mthca_alloc_cleanup(&dev->qp_table.alloc); |
| 2217 | } |