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gerrit-public.fairphone.software / kernel / msm-4.9 / cd339a0ed61097d92ce03b6d1042b1e4d58535e7 / . / drivers / net / bnx2.c
blob: 015ff7906601661fdbf1dc9cc09cafc1259242fc [file] [log] [blame]
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
17#define DRV_MODULE_VERSION "1.2.19"
18#define DRV_MODULE_RELDATE "May 23, 2005"
19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44} board_t;
45
46/* indexed by board_t, above */
47static struct {
48 char *name;
49} board_info[] __devinitdata = {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]55 };
56
57static struct pci_device_id bnx2_pci_tbl[] = {
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
59 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
60 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
61 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
65 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
68 { 0, }
69};
70
71static struct flash_spec flash_table[] =
72{
73 /* Slow EEPROM */
74 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
75 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
76 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
77 "EEPROM - slow"},
78 /* Fast EEPROM */
79 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
80 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
81 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
82 "EEPROM - fast"},
83 /* ATMEL AT45DB011B (buffered flash) */
84 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
85 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
86 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
87 "Buffered flash"},
88 /* Saifun SA25F005 (non-buffered flash) */
89 /* strap, cfg1, & write1 need updates */
90 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
91 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
92 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
93 "Non-buffered flash (64kB)"},
94 /* Saifun SA25F010 (non-buffered flash) */
95 /* strap, cfg1, & write1 need updates */
96 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
97 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
98 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
99 "Non-buffered flash (128kB)"},
100 /* Saifun SA25F020 (non-buffered flash) */
101 /* strap, cfg1, & write1 need updates */
102 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
103 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
104 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
105 "Non-buffered flash (256kB)"},
106};
107
108MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
109
110static u32
111bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
112{
113 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
114 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
115}
116
117static void
118bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
119{
120 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
121 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
122}
123
124static void
125bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
126{
127 offset += cid_addr;
128 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
129 REG_WR(bp, BNX2_CTX_DATA, val);
130}
131
132static int
133bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
134{
135 u32 val1;
136 int i, ret;
137
138 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
139 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
140 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
141
142 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
143 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
144
145 udelay(40);
146 }
147
148 val1 = (bp->phy_addr << 21) | (reg << 16) |
149 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
150 BNX2_EMAC_MDIO_COMM_START_BUSY;
151 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
152
153 for (i = 0; i < 50; i++) {
154 udelay(10);
155
156 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
157 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
158 udelay(5);
159
160 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
161 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
162
163 break;
164 }
165 }
166
167 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
168 *val = 0x0;
169 ret = -EBUSY;
170 }
171 else {
172 *val = val1;
173 ret = 0;
174 }
175
176 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
177 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
178 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
179
180 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
181 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
182
183 udelay(40);
184 }
185
186 return ret;
187}
188
189static int
190bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
191{
192 u32 val1;
193 int i, ret;
194
195 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
196 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
197 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
198
199 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
200 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
201
202 udelay(40);
203 }
204
205 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
206 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
207 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
208 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
209
210 for (i = 0; i < 50; i++) {
211 udelay(10);
212
213 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
214 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
215 udelay(5);
216 break;
217 }
218 }
219
220 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
221 ret = -EBUSY;
222 else
223 ret = 0;
224
225 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
226 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
227 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
228
229 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
230 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
231
232 udelay(40);
233 }
234
235 return ret;
236}
237
238static void
239bnx2_disable_int(struct bnx2 *bp)
240{
241 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
242 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
243 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
244}
245
246static void
247bnx2_enable_int(struct bnx2 *bp)
248{
249 u32 val;
250
251 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
252 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
253
254 val = REG_RD(bp, BNX2_HC_COMMAND);
255 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
256}
257
258static void
259bnx2_disable_int_sync(struct bnx2 *bp)
260{
261 atomic_inc(&bp->intr_sem);
262 bnx2_disable_int(bp);
263 synchronize_irq(bp->pdev->irq);
264}
265
266static void
267bnx2_netif_stop(struct bnx2 *bp)
268{
269 bnx2_disable_int_sync(bp);
270 if (netif_running(bp->dev)) {
271 netif_poll_disable(bp->dev);
272 netif_tx_disable(bp->dev);
273 bp->dev->trans_start = jiffies; /* prevent tx timeout */
274 }
275}
276
277static void
278bnx2_netif_start(struct bnx2 *bp)
279{
280 if (atomic_dec_and_test(&bp->intr_sem)) {
281 if (netif_running(bp->dev)) {
282 netif_wake_queue(bp->dev);
283 netif_poll_enable(bp->dev);
284 bnx2_enable_int(bp);
285 }
286 }
287}
288
289static void
290bnx2_free_mem(struct bnx2 *bp)
291{
292 if (bp->stats_blk) {
293 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
294 bp->stats_blk, bp->stats_blk_mapping);
295 bp->stats_blk = NULL;
296 }
297 if (bp->status_blk) {
298 pci_free_consistent(bp->pdev, sizeof(struct status_block),
299 bp->status_blk, bp->status_blk_mapping);
300 bp->status_blk = NULL;
301 }
302 if (bp->tx_desc_ring) {
303 pci_free_consistent(bp->pdev,
304 sizeof(struct tx_bd) * TX_DESC_CNT,
305 bp->tx_desc_ring, bp->tx_desc_mapping);
306 bp->tx_desc_ring = NULL;
307 }
308 if (bp->tx_buf_ring) {
309 kfree(bp->tx_buf_ring);
310 bp->tx_buf_ring = NULL;
311 }
312 if (bp->rx_desc_ring) {
313 pci_free_consistent(bp->pdev,
314 sizeof(struct rx_bd) * RX_DESC_CNT,
315 bp->rx_desc_ring, bp->rx_desc_mapping);
316 bp->rx_desc_ring = NULL;
317 }
318 if (bp->rx_buf_ring) {
319 kfree(bp->rx_buf_ring);
320 bp->rx_buf_ring = NULL;
321 }
322}
323
324static int
325bnx2_alloc_mem(struct bnx2 *bp)
326{
327 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
328 GFP_KERNEL);
329 if (bp->tx_buf_ring == NULL)
330 return -ENOMEM;
331
332 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
333 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
334 sizeof(struct tx_bd) *
335 TX_DESC_CNT,
336 &bp->tx_desc_mapping);
337 if (bp->tx_desc_ring == NULL)
338 goto alloc_mem_err;
339
340 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
341 GFP_KERNEL);
342 if (bp->rx_buf_ring == NULL)
343 goto alloc_mem_err;
344
345 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
346 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
347 sizeof(struct rx_bd) *
348 RX_DESC_CNT,
349 &bp->rx_desc_mapping);
350 if (bp->rx_desc_ring == NULL)
351 goto alloc_mem_err;
352
353 bp->status_blk = pci_alloc_consistent(bp->pdev,
354 sizeof(struct status_block),
355 &bp->status_blk_mapping);
356 if (bp->status_blk == NULL)
357 goto alloc_mem_err;
358
359 memset(bp->status_blk, 0, sizeof(struct status_block));
360
361 bp->stats_blk = pci_alloc_consistent(bp->pdev,
362 sizeof(struct statistics_block),
363 &bp->stats_blk_mapping);
364 if (bp->stats_blk == NULL)
365 goto alloc_mem_err;
366
367 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
368
369 return 0;
370
371alloc_mem_err:
372 bnx2_free_mem(bp);
373 return -ENOMEM;
374}
375
376static void
377bnx2_report_link(struct bnx2 *bp)
378{
379 if (bp->link_up) {
380 netif_carrier_on(bp->dev);
381 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
382
383 printk("%d Mbps ", bp->line_speed);
384
385 if (bp->duplex == DUPLEX_FULL)
386 printk("full duplex");
387 else
388 printk("half duplex");
389
390 if (bp->flow_ctrl) {
391 if (bp->flow_ctrl & FLOW_CTRL_RX) {
392 printk(", receive ");
393 if (bp->flow_ctrl & FLOW_CTRL_TX)
394 printk("& transmit ");
395 }
396 else {
397 printk(", transmit ");
398 }
399 printk("flow control ON");
400 }
401 printk("\n");
402 }
403 else {
404 netif_carrier_off(bp->dev);
405 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
406 }
407}
408
409static void
410bnx2_resolve_flow_ctrl(struct bnx2 *bp)
411{
412 u32 local_adv, remote_adv;
413
414 bp->flow_ctrl = 0;
415 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
416 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
417
418 if (bp->duplex == DUPLEX_FULL) {
419 bp->flow_ctrl = bp->req_flow_ctrl;
420 }
421 return;
422 }
423
424 if (bp->duplex != DUPLEX_FULL) {
425 return;
426 }
427
428 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
429 bnx2_read_phy(bp, MII_LPA, &remote_adv);
430
431 if (bp->phy_flags & PHY_SERDES_FLAG) {
432 u32 new_local_adv = 0;
433 u32 new_remote_adv = 0;
434
435 if (local_adv & ADVERTISE_1000XPAUSE)
436 new_local_adv |= ADVERTISE_PAUSE_CAP;
437 if (local_adv & ADVERTISE_1000XPSE_ASYM)
438 new_local_adv |= ADVERTISE_PAUSE_ASYM;
439 if (remote_adv & ADVERTISE_1000XPAUSE)
440 new_remote_adv |= ADVERTISE_PAUSE_CAP;
441 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
442 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
443
444 local_adv = new_local_adv;
445 remote_adv = new_remote_adv;
446 }
447
448 /* See Table 28B-3 of 802.3ab-1999 spec. */
449 if (local_adv & ADVERTISE_PAUSE_CAP) {
450 if(local_adv & ADVERTISE_PAUSE_ASYM) {
451 if (remote_adv & ADVERTISE_PAUSE_CAP) {
452 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
453 }
454 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
455 bp->flow_ctrl = FLOW_CTRL_RX;
456 }
457 }
458 else {
459 if (remote_adv & ADVERTISE_PAUSE_CAP) {
460 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
461 }
462 }
463 }
464 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
465 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
466 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
467
468 bp->flow_ctrl = FLOW_CTRL_TX;
469 }
470 }
471}
472
473static int
474bnx2_serdes_linkup(struct bnx2 *bp)
475{
476 u32 bmcr, local_adv, remote_adv, common;
477
478 bp->link_up = 1;
479 bp->line_speed = SPEED_1000;
480
481 bnx2_read_phy(bp, MII_BMCR, &bmcr);
482 if (bmcr & BMCR_FULLDPLX) {
483 bp->duplex = DUPLEX_FULL;
484 }
485 else {
486 bp->duplex = DUPLEX_HALF;
487 }
488
489 if (!(bmcr & BMCR_ANENABLE)) {
490 return 0;
491 }
492
493 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
494 bnx2_read_phy(bp, MII_LPA, &remote_adv);
495
496 common = local_adv & remote_adv;
497 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
498
499 if (common & ADVERTISE_1000XFULL) {
500 bp->duplex = DUPLEX_FULL;
501 }
502 else {
503 bp->duplex = DUPLEX_HALF;
504 }
505 }
506
507 return 0;
508}
509
510static int
511bnx2_copper_linkup(struct bnx2 *bp)
512{
513 u32 bmcr;
514
515 bnx2_read_phy(bp, MII_BMCR, &bmcr);
516 if (bmcr & BMCR_ANENABLE) {
517 u32 local_adv, remote_adv, common;
518
519 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
520 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
521
522 common = local_adv & (remote_adv >> 2);
523 if (common & ADVERTISE_1000FULL) {
524 bp->line_speed = SPEED_1000;
525 bp->duplex = DUPLEX_FULL;
526 }
527 else if (common & ADVERTISE_1000HALF) {
528 bp->line_speed = SPEED_1000;
529 bp->duplex = DUPLEX_HALF;
530 }
531 else {
532 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
533 bnx2_read_phy(bp, MII_LPA, &remote_adv);
534
535 common = local_adv & remote_adv;
536 if (common & ADVERTISE_100FULL) {
537 bp->line_speed = SPEED_100;
538 bp->duplex = DUPLEX_FULL;
539 }
540 else if (common & ADVERTISE_100HALF) {
541 bp->line_speed = SPEED_100;
542 bp->duplex = DUPLEX_HALF;
543 }
544 else if (common & ADVERTISE_10FULL) {
545 bp->line_speed = SPEED_10;
546 bp->duplex = DUPLEX_FULL;
547 }
548 else if (common & ADVERTISE_10HALF) {
549 bp->line_speed = SPEED_10;
550 bp->duplex = DUPLEX_HALF;
551 }
552 else {
553 bp->line_speed = 0;
554 bp->link_up = 0;
555 }
556 }
557 }
558 else {
559 if (bmcr & BMCR_SPEED100) {
560 bp->line_speed = SPEED_100;
561 }
562 else {
563 bp->line_speed = SPEED_10;
564 }
565 if (bmcr & BMCR_FULLDPLX) {
566 bp->duplex = DUPLEX_FULL;
567 }
568 else {
569 bp->duplex = DUPLEX_HALF;
570 }
571 }
572
573 return 0;
574}
575
576static int
577bnx2_set_mac_link(struct bnx2 *bp)
578{
579 u32 val;
580
581 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
582 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
583 (bp->duplex == DUPLEX_HALF)) {
584 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
585 }
586
587 /* Configure the EMAC mode register. */
588 val = REG_RD(bp, BNX2_EMAC_MODE);
589
590 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
591 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
592
593 if (bp->link_up) {
594 if (bp->line_speed != SPEED_1000)
595 val |= BNX2_EMAC_MODE_PORT_MII;
596 else
597 val |= BNX2_EMAC_MODE_PORT_GMII;
598 }
599 else {
600 val |= BNX2_EMAC_MODE_PORT_GMII;
601 }
602
603 /* Set the MAC to operate in the appropriate duplex mode. */
604 if (bp->duplex == DUPLEX_HALF)
605 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
606 REG_WR(bp, BNX2_EMAC_MODE, val);
607
608 /* Enable/disable rx PAUSE. */
609 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
610
611 if (bp->flow_ctrl & FLOW_CTRL_RX)
612 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
613 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
614
615 /* Enable/disable tx PAUSE. */
616 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
617 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
618
619 if (bp->flow_ctrl & FLOW_CTRL_TX)
620 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
621 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
622
623 /* Acknowledge the interrupt. */
624 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
625
626 return 0;
627}
628
629static int
630bnx2_set_link(struct bnx2 *bp)
631{
632 u32 bmsr;
633 u8 link_up;
634
635 if (bp->loopback == MAC_LOOPBACK) {
636 bp->link_up = 1;
637 return 0;
638 }
639
640 link_up = bp->link_up;
641
642 bnx2_read_phy(bp, MII_BMSR, &bmsr);
643 bnx2_read_phy(bp, MII_BMSR, &bmsr);
644
645 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
646 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
647 u32 val;
648
649 val = REG_RD(bp, BNX2_EMAC_STATUS);
650 if (val & BNX2_EMAC_STATUS_LINK)
651 bmsr |= BMSR_LSTATUS;
652 else
653 bmsr &= ~BMSR_LSTATUS;
654 }
655
656 if (bmsr & BMSR_LSTATUS) {
657 bp->link_up = 1;
658
659 if (bp->phy_flags & PHY_SERDES_FLAG) {
660 bnx2_serdes_linkup(bp);
661 }
662 else {
663 bnx2_copper_linkup(bp);
664 }
665 bnx2_resolve_flow_ctrl(bp);
666 }
667 else {
668 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
669 (bp->autoneg & AUTONEG_SPEED)) {
670
671 u32 bmcr;
672
673 bnx2_read_phy(bp, MII_BMCR, &bmcr);
674 if (!(bmcr & BMCR_ANENABLE)) {
675 bnx2_write_phy(bp, MII_BMCR, bmcr |
676 BMCR_ANENABLE);
677 }
678 }
679 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
680 bp->link_up = 0;
681 }
682
683 if (bp->link_up != link_up) {
684 bnx2_report_link(bp);
685 }
686
687 bnx2_set_mac_link(bp);
688
689 return 0;
690}
691
692static int
693bnx2_reset_phy(struct bnx2 *bp)
694{
695 int i;
696 u32 reg;
697
698 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
699
700#define PHY_RESET_MAX_WAIT 100
701 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
702 udelay(10);
703
704 bnx2_read_phy(bp, MII_BMCR, &reg);
705 if (!(reg & BMCR_RESET)) {
706 udelay(20);
707 break;
708 }
709 }
710 if (i == PHY_RESET_MAX_WAIT) {
711 return -EBUSY;
712 }
713 return 0;
714}
715
716static u32
717bnx2_phy_get_pause_adv(struct bnx2 *bp)
718{
719 u32 adv = 0;
720
721 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
722 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
723
724 if (bp->phy_flags & PHY_SERDES_FLAG) {
725 adv = ADVERTISE_1000XPAUSE;
726 }
727 else {
728 adv = ADVERTISE_PAUSE_CAP;
729 }
730 }
731 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
732 if (bp->phy_flags & PHY_SERDES_FLAG) {
733 adv = ADVERTISE_1000XPSE_ASYM;
734 }
735 else {
736 adv = ADVERTISE_PAUSE_ASYM;
737 }
738 }
739 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
740 if (bp->phy_flags & PHY_SERDES_FLAG) {
741 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
742 }
743 else {
744 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
745 }
746 }
747 return adv;
748}
749
750static int
751bnx2_setup_serdes_phy(struct bnx2 *bp)
752{
753 u32 adv, bmcr;
754 u32 new_adv = 0;
755
756 if (!(bp->autoneg & AUTONEG_SPEED)) {
757 u32 new_bmcr;
758
759 bnx2_read_phy(bp, MII_BMCR, &bmcr);
760 new_bmcr = bmcr & ~BMCR_ANENABLE;
761 new_bmcr |= BMCR_SPEED1000;
762 if (bp->req_duplex == DUPLEX_FULL) {
763 new_bmcr |= BMCR_FULLDPLX;
764 }
765 else {
766 new_bmcr &= ~BMCR_FULLDPLX;
767 }
768 if (new_bmcr != bmcr) {
769 /* Force a link down visible on the other side */
770 if (bp->link_up) {
771 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
772 adv &= ~(ADVERTISE_1000XFULL |
773 ADVERTISE_1000XHALF);
774 bnx2_write_phy(bp, MII_ADVERTISE, adv);
775 bnx2_write_phy(bp, MII_BMCR, bmcr |
776 BMCR_ANRESTART | BMCR_ANENABLE);
777
778 bp->link_up = 0;
779 netif_carrier_off(bp->dev);
780 }
781 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
782 }
783 return 0;
784 }
785
786 if (bp->advertising & ADVERTISED_1000baseT_Full)
787 new_adv |= ADVERTISE_1000XFULL;
788
789 new_adv |= bnx2_phy_get_pause_adv(bp);
790
791 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
792 bnx2_read_phy(bp, MII_BMCR, &bmcr);
793
794 bp->serdes_an_pending = 0;
795 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
796 /* Force a link down visible on the other side */
797 if (bp->link_up) {
798 int i;
799
800 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
801 for (i = 0; i < 110; i++) {
802 udelay(100);
803 }
804 }
805
806 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
807 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
808 BMCR_ANENABLE);
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]809 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
810 /* Speed up link-up time when the link partner
811 * does not autonegotiate which is very common
812 * in blade servers. Some blade servers use
813 * IPMI for kerboard input and it's important
814 * to minimize link disruptions. Autoneg. involves
815 * exchanging base pages plus 3 next pages and
816 * normally completes in about 120 msec.
817 */
818 bp->current_interval = SERDES_AN_TIMEOUT;
819 bp->serdes_an_pending = 1;
820 mod_timer(&bp->timer, jiffies + bp->current_interval);
821 }
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]822 }
823
824 return 0;
825}
826
827#define ETHTOOL_ALL_FIBRE_SPEED \
828 (ADVERTISED_1000baseT_Full)
829
830#define ETHTOOL_ALL_COPPER_SPEED \
831 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
832 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
833 ADVERTISED_1000baseT_Full)
834
835#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
836 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
837
838#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
839
840static int
841bnx2_setup_copper_phy(struct bnx2 *bp)
842{
843 u32 bmcr;
844 u32 new_bmcr;
845
846 bnx2_read_phy(bp, MII_BMCR, &bmcr);
847
848 if (bp->autoneg & AUTONEG_SPEED) {
849 u32 adv_reg, adv1000_reg;
850 u32 new_adv_reg = 0;
851 u32 new_adv1000_reg = 0;
852
853 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
854 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
855 ADVERTISE_PAUSE_ASYM);
856
857 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
858 adv1000_reg &= PHY_ALL_1000_SPEED;
859
860 if (bp->advertising & ADVERTISED_10baseT_Half)
861 new_adv_reg |= ADVERTISE_10HALF;
862 if (bp->advertising & ADVERTISED_10baseT_Full)
863 new_adv_reg |= ADVERTISE_10FULL;
864 if (bp->advertising & ADVERTISED_100baseT_Half)
865 new_adv_reg |= ADVERTISE_100HALF;
866 if (bp->advertising & ADVERTISED_100baseT_Full)
867 new_adv_reg |= ADVERTISE_100FULL;
868 if (bp->advertising & ADVERTISED_1000baseT_Full)
869 new_adv1000_reg |= ADVERTISE_1000FULL;
870
871 new_adv_reg |= ADVERTISE_CSMA;
872
873 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
874
875 if ((adv1000_reg != new_adv1000_reg) ||
876 (adv_reg != new_adv_reg) ||
877 ((bmcr & BMCR_ANENABLE) == 0)) {
878
879 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
880 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
881 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
882 BMCR_ANENABLE);
883 }
884 else if (bp->link_up) {
885 /* Flow ctrl may have changed from auto to forced */
886 /* or vice-versa. */
887
888 bnx2_resolve_flow_ctrl(bp);
889 bnx2_set_mac_link(bp);
890 }
891 return 0;
892 }
893
894 new_bmcr = 0;
895 if (bp->req_line_speed == SPEED_100) {
896 new_bmcr |= BMCR_SPEED100;
897 }
898 if (bp->req_duplex == DUPLEX_FULL) {
899 new_bmcr |= BMCR_FULLDPLX;
900 }
901 if (new_bmcr != bmcr) {
902 u32 bmsr;
903 int i = 0;
904
905 bnx2_read_phy(bp, MII_BMSR, &bmsr);
906 bnx2_read_phy(bp, MII_BMSR, &bmsr);
907
908 if (bmsr & BMSR_LSTATUS) {
909 /* Force link down */
910 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
911 do {
912 udelay(100);
913 bnx2_read_phy(bp, MII_BMSR, &bmsr);
914 bnx2_read_phy(bp, MII_BMSR, &bmsr);
915 i++;
916 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
917 }
918
919 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
920
921 /* Normally, the new speed is setup after the link has
922 * gone down and up again. In some cases, link will not go
923 * down so we need to set up the new speed here.
924 */
925 if (bmsr & BMSR_LSTATUS) {
926 bp->line_speed = bp->req_line_speed;
927 bp->duplex = bp->req_duplex;
928 bnx2_resolve_flow_ctrl(bp);
929 bnx2_set_mac_link(bp);
930 }
931 }
932 return 0;
933}
934
935static int
936bnx2_setup_phy(struct bnx2 *bp)
937{
938 if (bp->loopback == MAC_LOOPBACK)
939 return 0;
940
941 if (bp->phy_flags & PHY_SERDES_FLAG) {
942 return (bnx2_setup_serdes_phy(bp));
943 }
944 else {
945 return (bnx2_setup_copper_phy(bp));
946 }
947}
948
949static int
950bnx2_init_serdes_phy(struct bnx2 *bp)
951{
952 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
953
954 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
955 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
956 }
957
958 if (bp->dev->mtu > 1500) {
959 u32 val;
960
961 /* Set extended packet length bit */
962 bnx2_write_phy(bp, 0x18, 0x7);
963 bnx2_read_phy(bp, 0x18, &val);
964 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
965
966 bnx2_write_phy(bp, 0x1c, 0x6c00);
967 bnx2_read_phy(bp, 0x1c, &val);
968 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
969 }
970 else {
971 u32 val;
972
973 bnx2_write_phy(bp, 0x18, 0x7);
974 bnx2_read_phy(bp, 0x18, &val);
975 bnx2_write_phy(bp, 0x18, val & ~0x4007);
976
977 bnx2_write_phy(bp, 0x1c, 0x6c00);
978 bnx2_read_phy(bp, 0x1c, &val);
979 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
980 }
981
982 return 0;
983}
984
985static int
986bnx2_init_copper_phy(struct bnx2 *bp)
987{
988 bp->phy_flags |= PHY_CRC_FIX_FLAG;
989
990 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
991 bnx2_write_phy(bp, 0x18, 0x0c00);
992 bnx2_write_phy(bp, 0x17, 0x000a);
993 bnx2_write_phy(bp, 0x15, 0x310b);
994 bnx2_write_phy(bp, 0x17, 0x201f);
995 bnx2_write_phy(bp, 0x15, 0x9506);
996 bnx2_write_phy(bp, 0x17, 0x401f);
997 bnx2_write_phy(bp, 0x15, 0x14e2);
998 bnx2_write_phy(bp, 0x18, 0x0400);
999 }
1000
1001 if (bp->dev->mtu > 1500) {
1002 u32 val;
1003
1004 /* Set extended packet length bit */
1005 bnx2_write_phy(bp, 0x18, 0x7);
1006 bnx2_read_phy(bp, 0x18, &val);
1007 bnx2_write_phy(bp, 0x18, val | 0x4000);
1008
1009 bnx2_read_phy(bp, 0x10, &val);
1010 bnx2_write_phy(bp, 0x10, val | 0x1);
1011 }
1012 else {
1013 u32 val;
1014
1015 bnx2_write_phy(bp, 0x18, 0x7);
1016 bnx2_read_phy(bp, 0x18, &val);
1017 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1018
1019 bnx2_read_phy(bp, 0x10, &val);
1020 bnx2_write_phy(bp, 0x10, val & ~0x1);
1021 }
1022
1023 return 0;
1024}
1025
1026
1027static int
1028bnx2_init_phy(struct bnx2 *bp)
1029{
1030 u32 val;
1031 int rc = 0;
1032
1033 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1034 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1035
1036 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1037
1038 bnx2_reset_phy(bp);
1039
1040 bnx2_read_phy(bp, MII_PHYSID1, &val);
1041 bp->phy_id = val << 16;
1042 bnx2_read_phy(bp, MII_PHYSID2, &val);
1043 bp->phy_id |= val & 0xffff;
1044
1045 if (bp->phy_flags & PHY_SERDES_FLAG) {
1046 rc = bnx2_init_serdes_phy(bp);
1047 }
1048 else {
1049 rc = bnx2_init_copper_phy(bp);
1050 }
1051
1052 bnx2_setup_phy(bp);
1053
1054 return rc;
1055}
1056
1057static int
1058bnx2_set_mac_loopback(struct bnx2 *bp)
1059{
1060 u32 mac_mode;
1061
1062 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1063 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1064 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1065 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1066 bp->link_up = 1;
1067 return 0;
1068}
1069
1070static int
1071bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1072{
1073 int i;
1074 u32 val;
1075
1076 if (bp->fw_timed_out)
1077 return -EBUSY;
1078
1079 bp->fw_wr_seq++;
1080 msg_data |= bp->fw_wr_seq;
1081
1082 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1083
1084 /* wait for an acknowledgement. */
1085 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1086 udelay(5);
1087
1088 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1089
1090 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1091 break;
1092 }
1093
1094 /* If we timed out, inform the firmware that this is the case. */
1095 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1096 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1097
1098 msg_data &= ~BNX2_DRV_MSG_CODE;
1099 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1100
1101 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1102
1103 bp->fw_timed_out = 1;
1104
1105 return -EBUSY;
1106 }
1107
1108 return 0;
1109}
1110
1111static void
1112bnx2_init_context(struct bnx2 *bp)
1113{
1114 u32 vcid;
1115
1116 vcid = 96;
1117 while (vcid) {
1118 u32 vcid_addr, pcid_addr, offset;
1119
1120 vcid--;
1121
1122 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1123 u32 new_vcid;
1124
1125 vcid_addr = GET_PCID_ADDR(vcid);
1126 if (vcid & 0x8) {
1127 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1128 }
1129 else {
1130 new_vcid = vcid;
1131 }
1132 pcid_addr = GET_PCID_ADDR(new_vcid);
1133 }
1134 else {
1135 vcid_addr = GET_CID_ADDR(vcid);
1136 pcid_addr = vcid_addr;
1137 }
1138
1139 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1140 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1141
1142 /* Zero out the context. */
1143 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1144 CTX_WR(bp, 0x00, offset, 0);
1145 }
1146
1147 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1148 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1149 }
1150}
1151
1152static int
1153bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1154{
1155 u16 *good_mbuf;
1156 u32 good_mbuf_cnt;
1157 u32 val;
1158
1159 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1160 if (good_mbuf == NULL) {
1161 printk(KERN_ERR PFX "Failed to allocate memory in "
1162 "bnx2_alloc_bad_rbuf\n");
1163 return -ENOMEM;
1164 }
1165
1166 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1167 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1168
1169 good_mbuf_cnt = 0;
1170
1171 /* Allocate a bunch of mbufs and save the good ones in an array. */
1172 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1173 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1174 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1175
1176 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1177
1178 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1179
1180 /* The addresses with Bit 9 set are bad memory blocks. */
1181 if (!(val & (1 << 9))) {
1182 good_mbuf[good_mbuf_cnt] = (u16) val;
1183 good_mbuf_cnt++;
1184 }
1185
1186 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1187 }
1188
1189 /* Free the good ones back to the mbuf pool thus discarding
1190 * all the bad ones. */
1191 while (good_mbuf_cnt) {
1192 good_mbuf_cnt--;
1193
1194 val = good_mbuf[good_mbuf_cnt];
1195 val = (val << 9) | val | 1;
1196
1197 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1198 }
1199 kfree(good_mbuf);
1200 return 0;
1201}
1202
1203static void
1204bnx2_set_mac_addr(struct bnx2 *bp)
1205{
1206 u32 val;
1207 u8 *mac_addr = bp->dev->dev_addr;
1208
1209 val = (mac_addr[0] << 8) | mac_addr[1];
1210
1211 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1212
1213 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1214 (mac_addr[4] << 8) | mac_addr[5];
1215
1216 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1217}
1218
1219static inline int
1220bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1221{
1222 struct sk_buff *skb;
1223 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1224 dma_addr_t mapping;
1225 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1226 unsigned long align;
1227
1228 skb = dev_alloc_skb(bp->rx_buf_size);
1229 if (skb == NULL) {
1230 return -ENOMEM;
1231 }
1232
1233 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1234 skb_reserve(skb, 8 - align);
1235 }
1236
1237 skb->dev = bp->dev;
1238 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1239 PCI_DMA_FROMDEVICE);
1240
1241 rx_buf->skb = skb;
1242 pci_unmap_addr_set(rx_buf, mapping, mapping);
1243
1244 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1245 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1246
1247 bp->rx_prod_bseq += bp->rx_buf_use_size;
1248
1249 return 0;
1250}
1251
1252static void
1253bnx2_phy_int(struct bnx2 *bp)
1254{
1255 u32 new_link_state, old_link_state;
1256
1257 new_link_state = bp->status_blk->status_attn_bits &
1258 STATUS_ATTN_BITS_LINK_STATE;
1259 old_link_state = bp->status_blk->status_attn_bits_ack &
1260 STATUS_ATTN_BITS_LINK_STATE;
1261 if (new_link_state != old_link_state) {
1262 if (new_link_state) {
1263 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1264 STATUS_ATTN_BITS_LINK_STATE);
1265 }
1266 else {
1267 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1268 STATUS_ATTN_BITS_LINK_STATE);
1269 }
1270 bnx2_set_link(bp);
1271 }
1272}
1273
1274static void
1275bnx2_tx_int(struct bnx2 *bp)
1276{
1277 u16 hw_cons, sw_cons, sw_ring_cons;
1278 int tx_free_bd = 0;
1279
1280 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1281 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1282 hw_cons++;
1283 }
1284 sw_cons = bp->tx_cons;
1285
1286 while (sw_cons != hw_cons) {
1287 struct sw_bd *tx_buf;
1288 struct sk_buff *skb;
1289 int i, last;
1290
1291 sw_ring_cons = TX_RING_IDX(sw_cons);
1292
1293 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1294 skb = tx_buf->skb;
1295#ifdef BCM_TSO
1296 /* partial BD completions possible with TSO packets */
1297 if (skb_shinfo(skb)->tso_size) {
1298 u16 last_idx, last_ring_idx;
1299
1300 last_idx = sw_cons +
1301 skb_shinfo(skb)->nr_frags + 1;
1302 last_ring_idx = sw_ring_cons +
1303 skb_shinfo(skb)->nr_frags + 1;
1304 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1305 last_idx++;
1306 }
1307 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1308 break;
1309 }
1310 }
1311#endif
1312 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1313 skb_headlen(skb), PCI_DMA_TODEVICE);
1314
1315 tx_buf->skb = NULL;
1316 last = skb_shinfo(skb)->nr_frags;
1317
1318 for (i = 0; i < last; i++) {
1319 sw_cons = NEXT_TX_BD(sw_cons);
1320
1321 pci_unmap_page(bp->pdev,
1322 pci_unmap_addr(
1323 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1324 mapping),
1325 skb_shinfo(skb)->frags[i].size,
1326 PCI_DMA_TODEVICE);
1327 }
1328
1329 sw_cons = NEXT_TX_BD(sw_cons);
1330
1331 tx_free_bd += last + 1;
1332
1333 dev_kfree_skb_irq(skb);
1334
1335 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1336 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1337 hw_cons++;
1338 }
1339 }
1340
1341 atomic_add(tx_free_bd, &bp->tx_avail_bd);
1342
1343 if (unlikely(netif_queue_stopped(bp->dev))) {
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&bp->tx_lock, flags);
1347 if ((netif_queue_stopped(bp->dev)) &&
1348 (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) {
1349
1350 netif_wake_queue(bp->dev);
1351 }
1352 spin_unlock_irqrestore(&bp->tx_lock, flags);
1353 }
1354
1355 bp->tx_cons = sw_cons;
1356
1357}
1358
1359static inline void
1360bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1361 u16 cons, u16 prod)
1362{
1363 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1364 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1365 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1366 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1367
1368 pci_dma_sync_single_for_device(bp->pdev,
1369 pci_unmap_addr(cons_rx_buf, mapping),
1370 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1371
1372 prod_rx_buf->skb = cons_rx_buf->skb;
1373 pci_unmap_addr_set(prod_rx_buf, mapping,
1374 pci_unmap_addr(cons_rx_buf, mapping));
1375
1376 memcpy(prod_bd, cons_bd, 8);
1377
1378 bp->rx_prod_bseq += bp->rx_buf_use_size;
1379
1380}
1381
1382static int
1383bnx2_rx_int(struct bnx2 *bp, int budget)
1384{
1385 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1386 struct l2_fhdr *rx_hdr;
1387 int rx_pkt = 0;
1388
1389 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1390 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1391 hw_cons++;
1392 }
1393 sw_cons = bp->rx_cons;
1394 sw_prod = bp->rx_prod;
1395
1396 /* Memory barrier necessary as speculative reads of the rx
1397 * buffer can be ahead of the index in the status block
1398 */
1399 rmb();
1400 while (sw_cons != hw_cons) {
1401 unsigned int len;
1402 u16 status;
1403 struct sw_bd *rx_buf;
1404 struct sk_buff *skb;
1405
1406 sw_ring_cons = RX_RING_IDX(sw_cons);
1407 sw_ring_prod = RX_RING_IDX(sw_prod);
1408
1409 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1410 skb = rx_buf->skb;
1411 pci_dma_sync_single_for_cpu(bp->pdev,
1412 pci_unmap_addr(rx_buf, mapping),
1413 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1414
1415 rx_hdr = (struct l2_fhdr *) skb->data;
1416 len = rx_hdr->l2_fhdr_pkt_len - 4;
1417
1418 if (rx_hdr->l2_fhdr_errors &
1419 (L2_FHDR_ERRORS_BAD_CRC |
1420 L2_FHDR_ERRORS_PHY_DECODE |
1421 L2_FHDR_ERRORS_ALIGNMENT |
1422 L2_FHDR_ERRORS_TOO_SHORT |
1423 L2_FHDR_ERRORS_GIANT_FRAME)) {
1424
1425 goto reuse_rx;
1426 }
1427
1428 /* Since we don't have a jumbo ring, copy small packets
1429 * if mtu > 1500
1430 */
1431 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1432 struct sk_buff *new_skb;
1433
1434 new_skb = dev_alloc_skb(len + 2);
1435 if (new_skb == NULL)
1436 goto reuse_rx;
1437
1438 /* aligned copy */
1439 memcpy(new_skb->data,
1440 skb->data + bp->rx_offset - 2,
1441 len + 2);
1442
1443 skb_reserve(new_skb, 2);
1444 skb_put(new_skb, len);
1445 new_skb->dev = bp->dev;
1446
1447 bnx2_reuse_rx_skb(bp, skb,
1448 sw_ring_cons, sw_ring_prod);
1449
1450 skb = new_skb;
1451 }
1452 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1453 pci_unmap_single(bp->pdev,
1454 pci_unmap_addr(rx_buf, mapping),
1455 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1456
1457 skb_reserve(skb, bp->rx_offset);
1458 skb_put(skb, len);
1459 }
1460 else {
1461reuse_rx:
1462 bnx2_reuse_rx_skb(bp, skb,
1463 sw_ring_cons, sw_ring_prod);
1464 goto next_rx;
1465 }
1466
1467 skb->protocol = eth_type_trans(skb, bp->dev);
1468
1469 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1470 (htons(skb->protocol) != 0x8100)) {
1471
1472 dev_kfree_skb_irq(skb);
1473 goto next_rx;
1474
1475 }
1476
1477 status = rx_hdr->l2_fhdr_status;
1478 skb->ip_summed = CHECKSUM_NONE;
1479 if (bp->rx_csum &&
1480 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1481 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1482
1483 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1484
1485 if (cksum == 0xffff)
1486 skb->ip_summed = CHECKSUM_UNNECESSARY;
1487 }
1488
1489#ifdef BCM_VLAN
1490 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1491 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1492 rx_hdr->l2_fhdr_vlan_tag);
1493 }
1494 else
1495#endif
1496 netif_receive_skb(skb);
1497
1498 bp->dev->last_rx = jiffies;
1499 rx_pkt++;
1500
1501next_rx:
1502 rx_buf->skb = NULL;
1503
1504 sw_cons = NEXT_RX_BD(sw_cons);
1505 sw_prod = NEXT_RX_BD(sw_prod);
1506
1507 if ((rx_pkt == budget))
1508 break;
1509 }
1510 bp->rx_cons = sw_cons;
1511 bp->rx_prod = sw_prod;
1512
1513 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1514
1515 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1516
1517 mmiowb();
1518
1519 return rx_pkt;
1520
1521}
1522
1523/* MSI ISR - The only difference between this and the INTx ISR
1524 * is that the MSI interrupt is always serviced.
1525 */
1526static irqreturn_t
1527bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1528{
1529 struct net_device *dev = dev_instance;
1530 struct bnx2 *bp = dev->priv;
1531
1532 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1533 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1534 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1535
1536 /* Return here if interrupt is disabled. */
1537 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1538 return IRQ_RETVAL(1);
1539 }
1540
1541 if (netif_rx_schedule_prep(dev)) {
1542 __netif_rx_schedule(dev);
1543 }
1544
1545 return IRQ_RETVAL(1);
1546}
1547
1548static irqreturn_t
1549bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1550{
1551 struct net_device *dev = dev_instance;
1552 struct bnx2 *bp = dev->priv;
1553
1554 /* When using INTx, it is possible for the interrupt to arrive
1555 * at the CPU before the status block posted prior to the
1556 * interrupt. Reading a register will flush the status block.
1557 * When using MSI, the MSI message will always complete after
1558 * the status block write.
1559 */
1560 if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1561 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1562 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1563 return IRQ_RETVAL(0);
1564
1565 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1566 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1567 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1568
1569 /* Return here if interrupt is shared and is disabled. */
1570 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1571 return IRQ_RETVAL(1);
1572 }
1573
1574 if (netif_rx_schedule_prep(dev)) {
1575 __netif_rx_schedule(dev);
1576 }
1577
1578 return IRQ_RETVAL(1);
1579}
1580
1581static int
1582bnx2_poll(struct net_device *dev, int *budget)
1583{
1584 struct bnx2 *bp = dev->priv;
1585 int rx_done = 1;
1586
1587 bp->last_status_idx = bp->status_blk->status_idx;
1588
1589 rmb();
1590 if ((bp->status_blk->status_attn_bits &
1591 STATUS_ATTN_BITS_LINK_STATE) !=
1592 (bp->status_blk->status_attn_bits_ack &
1593 STATUS_ATTN_BITS_LINK_STATE)) {
1594
1595 unsigned long flags;
1596
1597 spin_lock_irqsave(&bp->phy_lock, flags);
1598 bnx2_phy_int(bp);
1599 spin_unlock_irqrestore(&bp->phy_lock, flags);
1600 }
1601
1602 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1603 bnx2_tx_int(bp);
1604 }
1605
1606 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1607 int orig_budget = *budget;
1608 int work_done;
1609
1610 if (orig_budget > dev->quota)
1611 orig_budget = dev->quota;
1612
1613 work_done = bnx2_rx_int(bp, orig_budget);
1614 *budget -= work_done;
1615 dev->quota -= work_done;
1616
1617 if (work_done >= orig_budget) {
1618 rx_done = 0;
1619 }
1620 }
1621
1622 if (rx_done) {
1623 netif_rx_complete(dev);
1624 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1625 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1626 bp->last_status_idx);
1627 return 0;
1628 }
1629
1630 return 1;
1631}
1632
1633/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1634 * from set_multicast.
1635 */
1636static void
1637bnx2_set_rx_mode(struct net_device *dev)
1638{
1639 struct bnx2 *bp = dev->priv;
1640 u32 rx_mode, sort_mode;
1641 int i;
1642 unsigned long flags;
1643
1644 spin_lock_irqsave(&bp->phy_lock, flags);
1645
1646 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1647 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1648 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1649#ifdef BCM_VLAN
1650 if (!bp->vlgrp) {
1651 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1652 }
1653#else
1654 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1655#endif
1656 if (dev->flags & IFF_PROMISC) {
1657 /* Promiscuous mode. */
1658 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1659 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1660 }
1661 else if (dev->flags & IFF_ALLMULTI) {
1662 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1663 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1664 0xffffffff);
1665 }
1666 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1667 }
1668 else {
1669 /* Accept one or more multicast(s). */
1670 struct dev_mc_list *mclist;
1671 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1672 u32 regidx;
1673 u32 bit;
1674 u32 crc;
1675
1676 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1677
1678 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1679 i++, mclist = mclist->next) {
1680
1681 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1682 bit = crc & 0xff;
1683 regidx = (bit & 0xe0) >> 5;
1684 bit &= 0x1f;
1685 mc_filter[regidx] |= (1 << bit);
1686 }
1687
1688 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1689 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1690 mc_filter[i]);
1691 }
1692
1693 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1694 }
1695
1696 if (rx_mode != bp->rx_mode) {
1697 bp->rx_mode = rx_mode;
1698 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1699 }
1700
1701 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1702 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1703 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1704
1705 spin_unlock_irqrestore(&bp->phy_lock, flags);
1706}
1707
1708static void
1709load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1710 u32 rv2p_proc)
1711{
1712 int i;
1713 u32 val;
1714
1715
1716 for (i = 0; i < rv2p_code_len; i += 8) {
1717 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1718 rv2p_code++;
1719 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1720 rv2p_code++;
1721
1722 if (rv2p_proc == RV2P_PROC1) {
1723 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1724 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1725 }
1726 else {
1727 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1728 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1729 }
1730 }
1731
1732 /* Reset the processor, un-stall is done later. */
1733 if (rv2p_proc == RV2P_PROC1) {
1734 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1735 }
1736 else {
1737 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1738 }
1739}
1740
1741static void
1742load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1743{
1744 u32 offset;
1745 u32 val;
1746
1747 /* Halt the CPU. */
1748 val = REG_RD_IND(bp, cpu_reg->mode);
1749 val |= cpu_reg->mode_value_halt;
1750 REG_WR_IND(bp, cpu_reg->mode, val);
1751 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1752
1753 /* Load the Text area. */
1754 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1755 if (fw->text) {
1756 int j;
1757
1758 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1759 REG_WR_IND(bp, offset, fw->text[j]);
1760 }
1761 }
1762
1763 /* Load the Data area. */
1764 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1765 if (fw->data) {
1766 int j;
1767
1768 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1769 REG_WR_IND(bp, offset, fw->data[j]);
1770 }
1771 }
1772
1773 /* Load the SBSS area. */
1774 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1775 if (fw->sbss) {
1776 int j;
1777
1778 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1779 REG_WR_IND(bp, offset, fw->sbss[j]);
1780 }
1781 }
1782
1783 /* Load the BSS area. */
1784 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1785 if (fw->bss) {
1786 int j;
1787
1788 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1789 REG_WR_IND(bp, offset, fw->bss[j]);
1790 }
1791 }
1792
1793 /* Load the Read-Only area. */
1794 offset = cpu_reg->spad_base +
1795 (fw->rodata_addr - cpu_reg->mips_view_base);
1796 if (fw->rodata) {
1797 int j;
1798
1799 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1800 REG_WR_IND(bp, offset, fw->rodata[j]);
1801 }
1802 }
1803
1804 /* Clear the pre-fetch instruction. */
1805 REG_WR_IND(bp, cpu_reg->inst, 0);
1806 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1807
1808 /* Start the CPU. */
1809 val = REG_RD_IND(bp, cpu_reg->mode);
1810 val &= ~cpu_reg->mode_value_halt;
1811 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1812 REG_WR_IND(bp, cpu_reg->mode, val);
1813}
1814
1815static void
1816bnx2_init_cpus(struct bnx2 *bp)
1817{
1818 struct cpu_reg cpu_reg;
1819 struct fw_info fw;
1820
1821 /* Initialize the RV2P processor. */
1822 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1823 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1824
1825 /* Initialize the RX Processor. */
1826 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1827 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1828 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1829 cpu_reg.state = BNX2_RXP_CPU_STATE;
1830 cpu_reg.state_value_clear = 0xffffff;
1831 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1832 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1833 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1834 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1835 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1836 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1837 cpu_reg.mips_view_base = 0x8000000;
1838
1839 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1840 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1841 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1842 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1843
1844 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1845 fw.text_len = bnx2_RXP_b06FwTextLen;
1846 fw.text_index = 0;
1847 fw.text = bnx2_RXP_b06FwText;
1848
1849 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1850 fw.data_len = bnx2_RXP_b06FwDataLen;
1851 fw.data_index = 0;
1852 fw.data = bnx2_RXP_b06FwData;
1853
1854 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1855 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1856 fw.sbss_index = 0;
1857 fw.sbss = bnx2_RXP_b06FwSbss;
1858
1859 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1860 fw.bss_len = bnx2_RXP_b06FwBssLen;
1861 fw.bss_index = 0;
1862 fw.bss = bnx2_RXP_b06FwBss;
1863
1864 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1865 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1866 fw.rodata_index = 0;
1867 fw.rodata = bnx2_RXP_b06FwRodata;
1868
1869 load_cpu_fw(bp, &cpu_reg, &fw);
1870
1871 /* Initialize the TX Processor. */
1872 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1873 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1874 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1875 cpu_reg.state = BNX2_TXP_CPU_STATE;
1876 cpu_reg.state_value_clear = 0xffffff;
1877 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1878 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1879 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1880 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1881 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1882 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1883 cpu_reg.mips_view_base = 0x8000000;
1884
1885 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1886 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1887 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1888 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1889
1890 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1891 fw.text_len = bnx2_TXP_b06FwTextLen;
1892 fw.text_index = 0;
1893 fw.text = bnx2_TXP_b06FwText;
1894
1895 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1896 fw.data_len = bnx2_TXP_b06FwDataLen;
1897 fw.data_index = 0;
1898 fw.data = bnx2_TXP_b06FwData;
1899
1900 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1901 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1902 fw.sbss_index = 0;
1903 fw.sbss = bnx2_TXP_b06FwSbss;
1904
1905 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1906 fw.bss_len = bnx2_TXP_b06FwBssLen;
1907 fw.bss_index = 0;
1908 fw.bss = bnx2_TXP_b06FwBss;
1909
1910 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1911 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1912 fw.rodata_index = 0;
1913 fw.rodata = bnx2_TXP_b06FwRodata;
1914
1915 load_cpu_fw(bp, &cpu_reg, &fw);
1916
1917 /* Initialize the TX Patch-up Processor. */
1918 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1919 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1920 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1921 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1922 cpu_reg.state_value_clear = 0xffffff;
1923 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1924 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1925 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1926 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1927 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1928 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1929 cpu_reg.mips_view_base = 0x8000000;
1930
1931 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1932 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1933 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1934 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1935
1936 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1937 fw.text_len = bnx2_TPAT_b06FwTextLen;
1938 fw.text_index = 0;
1939 fw.text = bnx2_TPAT_b06FwText;
1940
1941 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1942 fw.data_len = bnx2_TPAT_b06FwDataLen;
1943 fw.data_index = 0;
1944 fw.data = bnx2_TPAT_b06FwData;
1945
1946 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1947 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1948 fw.sbss_index = 0;
1949 fw.sbss = bnx2_TPAT_b06FwSbss;
1950
1951 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1952 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1953 fw.bss_index = 0;
1954 fw.bss = bnx2_TPAT_b06FwBss;
1955
1956 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1957 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1958 fw.rodata_index = 0;
1959 fw.rodata = bnx2_TPAT_b06FwRodata;
1960
1961 load_cpu_fw(bp, &cpu_reg, &fw);
1962
1963 /* Initialize the Completion Processor. */
1964 cpu_reg.mode = BNX2_COM_CPU_MODE;
1965 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1966 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1967 cpu_reg.state = BNX2_COM_CPU_STATE;
1968 cpu_reg.state_value_clear = 0xffffff;
1969 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1970 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1971 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1972 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1973 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1974 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1975 cpu_reg.mips_view_base = 0x8000000;
1976
1977 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1978 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1979 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1980 fw.start_addr = bnx2_COM_b06FwStartAddr;
1981
1982 fw.text_addr = bnx2_COM_b06FwTextAddr;
1983 fw.text_len = bnx2_COM_b06FwTextLen;
1984 fw.text_index = 0;
1985 fw.text = bnx2_COM_b06FwText;
1986
1987 fw.data_addr = bnx2_COM_b06FwDataAddr;
1988 fw.data_len = bnx2_COM_b06FwDataLen;
1989 fw.data_index = 0;
1990 fw.data = bnx2_COM_b06FwData;
1991
1992 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1993 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1994 fw.sbss_index = 0;
1995 fw.sbss = bnx2_COM_b06FwSbss;
1996
1997 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1998 fw.bss_len = bnx2_COM_b06FwBssLen;
1999 fw.bss_index = 0;
2000 fw.bss = bnx2_COM_b06FwBss;
2001
2002 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2003 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2004 fw.rodata_index = 0;
2005 fw.rodata = bnx2_COM_b06FwRodata;
2006
2007 load_cpu_fw(bp, &cpu_reg, &fw);
2008
2009}
2010
2011static int
2012bnx2_set_power_state(struct bnx2 *bp, int state)
2013{
2014 u16 pmcsr;
2015
2016 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2017
2018 switch (state) {
2019 case 0: {
2020 u32 val;
2021
2022 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2023 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2024 PCI_PM_CTRL_PME_STATUS);
2025
2026 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2027 /* delay required during transition out of D3hot */
2028 msleep(20);
2029
2030 val = REG_RD(bp, BNX2_EMAC_MODE);
2031 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2032 val &= ~BNX2_EMAC_MODE_MPKT;
2033 REG_WR(bp, BNX2_EMAC_MODE, val);
2034
2035 val = REG_RD(bp, BNX2_RPM_CONFIG);
2036 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2037 REG_WR(bp, BNX2_RPM_CONFIG, val);
2038 break;
2039 }
2040 case 3: {
2041 int i;
2042 u32 val, wol_msg;
2043
2044 if (bp->wol) {
2045 u32 advertising;
2046 u8 autoneg;
2047
2048 autoneg = bp->autoneg;
2049 advertising = bp->advertising;
2050
2051 bp->autoneg = AUTONEG_SPEED;
2052 bp->advertising = ADVERTISED_10baseT_Half |
2053 ADVERTISED_10baseT_Full |
2054 ADVERTISED_100baseT_Half |
2055 ADVERTISED_100baseT_Full |
2056 ADVERTISED_Autoneg;
2057
2058 bnx2_setup_copper_phy(bp);
2059
2060 bp->autoneg = autoneg;
2061 bp->advertising = advertising;
2062
2063 bnx2_set_mac_addr(bp);
2064
2065 val = REG_RD(bp, BNX2_EMAC_MODE);
2066
2067 /* Enable port mode. */
2068 val &= ~BNX2_EMAC_MODE_PORT;
2069 val |= BNX2_EMAC_MODE_PORT_MII |
2070 BNX2_EMAC_MODE_MPKT_RCVD |
2071 BNX2_EMAC_MODE_ACPI_RCVD |
2072 BNX2_EMAC_MODE_FORCE_LINK |
2073 BNX2_EMAC_MODE_MPKT;
2074
2075 REG_WR(bp, BNX2_EMAC_MODE, val);
2076
2077 /* receive all multicast */
2078 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2079 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2080 0xffffffff);
2081 }
2082 REG_WR(bp, BNX2_EMAC_RX_MODE,
2083 BNX2_EMAC_RX_MODE_SORT_MODE);
2084
2085 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2086 BNX2_RPM_SORT_USER0_MC_EN;
2087 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2088 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2089 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2090 BNX2_RPM_SORT_USER0_ENA);
2091
2092 /* Need to enable EMAC and RPM for WOL. */
2093 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2094 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2095 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2096 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2097
2098 val = REG_RD(bp, BNX2_RPM_CONFIG);
2099 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2100 REG_WR(bp, BNX2_RPM_CONFIG, val);
2101
2102 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2103 }
2104 else {
2105 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2106 }
2107
2108 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2109
2110 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2111 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2112 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2113
2114 if (bp->wol)
2115 pmcsr |= 3;
2116 }
2117 else {
2118 pmcsr |= 3;
2119 }
2120 if (bp->wol) {
2121 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2122 }
2123 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2124 pmcsr);
2125
2126 /* No more memory access after this point until
2127 * device is brought back to D0.
2128 */
2129 udelay(50);
2130 break;
2131 }
2132 default:
2133 return -EINVAL;
2134 }
2135 return 0;
2136}
2137
2138static int
2139bnx2_acquire_nvram_lock(struct bnx2 *bp)
2140{
2141 u32 val;
2142 int j;
2143
2144 /* Request access to the flash interface. */
2145 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2146 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2147 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2148 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2149 break;
2150
2151 udelay(5);
2152 }
2153
2154 if (j >= NVRAM_TIMEOUT_COUNT)
2155 return -EBUSY;
2156
2157 return 0;
2158}
2159
2160static int
2161bnx2_release_nvram_lock(struct bnx2 *bp)
2162{
2163 int j;
2164 u32 val;
2165
2166 /* Relinquish nvram interface. */
2167 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2168
2169 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2170 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2171 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2172 break;
2173
2174 udelay(5);
2175 }
2176
2177 if (j >= NVRAM_TIMEOUT_COUNT)
2178 return -EBUSY;
2179
2180 return 0;
2181}
2182
2183
2184static int
2185bnx2_enable_nvram_write(struct bnx2 *bp)
2186{
2187 u32 val;
2188
2189 val = REG_RD(bp, BNX2_MISC_CFG);
2190 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2191
2192 if (!bp->flash_info->buffered) {
2193 int j;
2194
2195 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2196 REG_WR(bp, BNX2_NVM_COMMAND,
2197 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2198
2199 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2200 udelay(5);
2201
2202 val = REG_RD(bp, BNX2_NVM_COMMAND);
2203 if (val & BNX2_NVM_COMMAND_DONE)
2204 break;
2205 }
2206
2207 if (j >= NVRAM_TIMEOUT_COUNT)
2208 return -EBUSY;
2209 }
2210 return 0;
2211}
2212
2213static void
2214bnx2_disable_nvram_write(struct bnx2 *bp)
2215{
2216 u32 val;
2217
2218 val = REG_RD(bp, BNX2_MISC_CFG);
2219 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2220}
2221
2222
2223static void
2224bnx2_enable_nvram_access(struct bnx2 *bp)
2225{
2226 u32 val;
2227
2228 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2229 /* Enable both bits, even on read. */
2230 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2231 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2232}
2233
2234static void
2235bnx2_disable_nvram_access(struct bnx2 *bp)
2236{
2237 u32 val;
2238
2239 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2240 /* Disable both bits, even after read. */
2241 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2242 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2243 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2244}
2245
2246static int
2247bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2248{
2249 u32 cmd;
2250 int j;
2251
2252 if (bp->flash_info->buffered)
2253 /* Buffered flash, no erase needed */
2254 return 0;
2255
2256 /* Build an erase command */
2257 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2258 BNX2_NVM_COMMAND_DOIT;
2259
2260 /* Need to clear DONE bit separately. */
2261 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2262
2263 /* Address of the NVRAM to read from. */
2264 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2265
2266 /* Issue an erase command. */
2267 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2268
2269 /* Wait for completion. */
2270 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2271 u32 val;
2272
2273 udelay(5);
2274
2275 val = REG_RD(bp, BNX2_NVM_COMMAND);
2276 if (val & BNX2_NVM_COMMAND_DONE)
2277 break;
2278 }
2279
2280 if (j >= NVRAM_TIMEOUT_COUNT)
2281 return -EBUSY;
2282
2283 return 0;
2284}
2285
2286static int
2287bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2288{
2289 u32 cmd;
2290 int j;
2291
2292 /* Build the command word. */
2293 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2294
2295 /* Calculate an offset of a buffered flash. */
2296 if (bp->flash_info->buffered) {
2297 offset = ((offset / bp->flash_info->page_size) <<
2298 bp->flash_info->page_bits) +
2299 (offset % bp->flash_info->page_size);
2300 }
2301
2302 /* Need to clear DONE bit separately. */
2303 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2304
2305 /* Address of the NVRAM to read from. */
2306 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2307
2308 /* Issue a read command. */
2309 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2310
2311 /* Wait for completion. */
2312 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2313 u32 val;
2314
2315 udelay(5);
2316
2317 val = REG_RD(bp, BNX2_NVM_COMMAND);
2318 if (val & BNX2_NVM_COMMAND_DONE) {
2319 val = REG_RD(bp, BNX2_NVM_READ);
2320
2321 val = be32_to_cpu(val);
2322 memcpy(ret_val, &val, 4);
2323 break;
2324 }
2325 }
2326 if (j >= NVRAM_TIMEOUT_COUNT)
2327 return -EBUSY;
2328
2329 return 0;
2330}
2331
2332
2333static int
2334bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2335{
2336 u32 cmd, val32;
2337 int j;
2338
2339 /* Build the command word. */
2340 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2341
2342 /* Calculate an offset of a buffered flash. */
2343 if (bp->flash_info->buffered) {
2344 offset = ((offset / bp->flash_info->page_size) <<
2345 bp->flash_info->page_bits) +
2346 (offset % bp->flash_info->page_size);
2347 }
2348
2349 /* Need to clear DONE bit separately. */
2350 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2351
2352 memcpy(&val32, val, 4);
2353 val32 = cpu_to_be32(val32);
2354
2355 /* Write the data. */
2356 REG_WR(bp, BNX2_NVM_WRITE, val32);
2357
2358 /* Address of the NVRAM to write to. */
2359 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2360
2361 /* Issue the write command. */
2362 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2363
2364 /* Wait for completion. */
2365 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2366 udelay(5);
2367
2368 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2369 break;
2370 }
2371 if (j >= NVRAM_TIMEOUT_COUNT)
2372 return -EBUSY;
2373
2374 return 0;
2375}
2376
2377static int
2378bnx2_init_nvram(struct bnx2 *bp)
2379{
2380 u32 val;
2381 int j, entry_count, rc;
2382 struct flash_spec *flash;
2383
2384 /* Determine the selected interface. */
2385 val = REG_RD(bp, BNX2_NVM_CFG1);
2386
2387 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2388
2389 rc = 0;
2390 if (val & 0x40000000) {
2391
2392 /* Flash interface has been reconfigured */
2393 for (j = 0, flash = &flash_table[0]; j < entry_count;
2394 j++, flash++) {
2395
2396 if (val == flash->config1) {
2397 bp->flash_info = flash;
2398 break;
2399 }
2400 }
2401 }
2402 else {
2403 /* Not yet been reconfigured */
2404
2405 for (j = 0, flash = &flash_table[0]; j < entry_count;
2406 j++, flash++) {
2407
2408 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2409 bp->flash_info = flash;
2410
2411 /* Request access to the flash interface. */
2412 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2413 return rc;
2414
2415 /* Enable access to flash interface */
2416 bnx2_enable_nvram_access(bp);
2417
2418 /* Reconfigure the flash interface */
2419 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2420 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2421 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2422 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2423
2424 /* Disable access to flash interface */
2425 bnx2_disable_nvram_access(bp);
2426 bnx2_release_nvram_lock(bp);
2427
2428 break;
2429 }
2430 }
2431 } /* if (val & 0x40000000) */
2432
2433 if (j == entry_count) {
2434 bp->flash_info = NULL;
2435 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2436 rc = -ENODEV;
2437 }
2438
2439 return rc;
2440}
2441
2442static int
2443bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2444 int buf_size)
2445{
2446 int rc = 0;
2447 u32 cmd_flags, offset32, len32, extra;
2448
2449 if (buf_size == 0)
2450 return 0;
2451
2452 /* Request access to the flash interface. */
2453 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2454 return rc;
2455
2456 /* Enable access to flash interface */
2457 bnx2_enable_nvram_access(bp);
2458
2459 len32 = buf_size;
2460 offset32 = offset;
2461 extra = 0;
2462
2463 cmd_flags = 0;
2464
2465 if (offset32 & 3) {
2466 u8 buf[4];
2467 u32 pre_len;
2468
2469 offset32 &= ~3;
2470 pre_len = 4 - (offset & 3);
2471
2472 if (pre_len >= len32) {
2473 pre_len = len32;
2474 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2475 BNX2_NVM_COMMAND_LAST;
2476 }
2477 else {
2478 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2479 }
2480
2481 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2482
2483 if (rc)
2484 return rc;
2485
2486 memcpy(ret_buf, buf + (offset & 3), pre_len);
2487
2488 offset32 += 4;
2489 ret_buf += pre_len;
2490 len32 -= pre_len;
2491 }
2492 if (len32 & 3) {
2493 extra = 4 - (len32 & 3);
2494 len32 = (len32 + 4) & ~3;
2495 }
2496
2497 if (len32 == 4) {
2498 u8 buf[4];
2499
2500 if (cmd_flags)
2501 cmd_flags = BNX2_NVM_COMMAND_LAST;
2502 else
2503 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2504 BNX2_NVM_COMMAND_LAST;
2505
2506 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2507
2508 memcpy(ret_buf, buf, 4 - extra);
2509 }
2510 else if (len32 > 0) {
2511 u8 buf[4];
2512
2513 /* Read the first word. */
2514 if (cmd_flags)
2515 cmd_flags = 0;
2516 else
2517 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2518
2519 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2520
2521 /* Advance to the next dword. */
2522 offset32 += 4;
2523 ret_buf += 4;
2524 len32 -= 4;
2525
2526 while (len32 > 4 && rc == 0) {
2527 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2528
2529 /* Advance to the next dword. */
2530 offset32 += 4;
2531 ret_buf += 4;
2532 len32 -= 4;
2533 }
2534
2535 if (rc)
2536 return rc;
2537
2538 cmd_flags = BNX2_NVM_COMMAND_LAST;
2539 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2540
2541 memcpy(ret_buf, buf, 4 - extra);
2542 }
2543
2544 /* Disable access to flash interface */
2545 bnx2_disable_nvram_access(bp);
2546
2547 bnx2_release_nvram_lock(bp);
2548
2549 return rc;
2550}
2551
2552static int
2553bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2554 int buf_size)
2555{
2556 u32 written, offset32, len32;
2557 u8 *buf, start[4], end[4];
2558 int rc = 0;
2559 int align_start, align_end;
2560
2561 buf = data_buf;
2562 offset32 = offset;
2563 len32 = buf_size;
2564 align_start = align_end = 0;
2565
2566 if ((align_start = (offset32 & 3))) {
2567 offset32 &= ~3;
2568 len32 += align_start;
2569 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2570 return rc;
2571 }
2572
2573 if (len32 & 3) {
2574 if ((len32 > 4) || !align_start) {
2575 align_end = 4 - (len32 & 3);
2576 len32 += align_end;
2577 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2578 end, 4))) {
2579 return rc;
2580 }
2581 }
2582 }
2583
2584 if (align_start || align_end) {
2585 buf = kmalloc(len32, GFP_KERNEL);
2586 if (buf == 0)
2587 return -ENOMEM;
2588 if (align_start) {
2589 memcpy(buf, start, 4);
2590 }
2591 if (align_end) {
2592 memcpy(buf + len32 - 4, end, 4);
2593 }
2594 memcpy(buf + align_start, data_buf, buf_size);
2595 }
2596
2597 written = 0;
2598 while ((written < len32) && (rc == 0)) {
2599 u32 page_start, page_end, data_start, data_end;
2600 u32 addr, cmd_flags;
2601 int i;
2602 u8 flash_buffer[264];
2603
2604 /* Find the page_start addr */
2605 page_start = offset32 + written;
2606 page_start -= (page_start % bp->flash_info->page_size);
2607 /* Find the page_end addr */
2608 page_end = page_start + bp->flash_info->page_size;
2609 /* Find the data_start addr */
2610 data_start = (written == 0) ? offset32 : page_start;
2611 /* Find the data_end addr */
2612 data_end = (page_end > offset32 + len32) ?
2613 (offset32 + len32) : page_end;
2614
2615 /* Request access to the flash interface. */
2616 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2617 goto nvram_write_end;
2618
2619 /* Enable access to flash interface */
2620 bnx2_enable_nvram_access(bp);
2621
2622 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2623 if (bp->flash_info->buffered == 0) {
2624 int j;
2625
2626 /* Read the whole page into the buffer
2627 * (non-buffer flash only) */
2628 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2629 if (j == (bp->flash_info->page_size - 4)) {
2630 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2631 }
2632 rc = bnx2_nvram_read_dword(bp,
2633 page_start + j,
2634 &flash_buffer[j],
2635 cmd_flags);
2636
2637 if (rc)
2638 goto nvram_write_end;
2639
2640 cmd_flags = 0;
2641 }
2642 }
2643
2644 /* Enable writes to flash interface (unlock write-protect) */
2645 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2646 goto nvram_write_end;
2647
2648 /* Erase the page */
2649 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2650 goto nvram_write_end;
2651
2652 /* Re-enable the write again for the actual write */
2653 bnx2_enable_nvram_write(bp);
2654
2655 /* Loop to write back the buffer data from page_start to
2656 * data_start */
2657 i = 0;
2658 if (bp->flash_info->buffered == 0) {
2659 for (addr = page_start; addr < data_start;
2660 addr += 4, i += 4) {
2661
2662 rc = bnx2_nvram_write_dword(bp, addr,
2663 &flash_buffer[i], cmd_flags);
2664
2665 if (rc != 0)
2666 goto nvram_write_end;
2667
2668 cmd_flags = 0;
2669 }
2670 }
2671
2672 /* Loop to write the new data from data_start to data_end */
2673 for (addr = data_start; addr < data_end; addr += 4, i++) {
2674 if ((addr == page_end - 4) ||
2675 ((bp->flash_info->buffered) &&
2676 (addr == data_end - 4))) {
2677
2678 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2679 }
2680 rc = bnx2_nvram_write_dword(bp, addr, buf,
2681 cmd_flags);
2682
2683 if (rc != 0)
2684 goto nvram_write_end;
2685
2686 cmd_flags = 0;
2687 buf += 4;
2688 }
2689
2690 /* Loop to write back the buffer data from data_end
2691 * to page_end */
2692 if (bp->flash_info->buffered == 0) {
2693 for (addr = data_end; addr < page_end;
2694 addr += 4, i += 4) {
2695
2696 if (addr == page_end-4) {
2697 cmd_flags = BNX2_NVM_COMMAND_LAST;
2698 }
2699 rc = bnx2_nvram_write_dword(bp, addr,
2700 &flash_buffer[i], cmd_flags);
2701
2702 if (rc != 0)
2703 goto nvram_write_end;
2704
2705 cmd_flags = 0;
2706 }
2707 }
2708
2709 /* Disable writes to flash interface (lock write-protect) */
2710 bnx2_disable_nvram_write(bp);
2711
2712 /* Disable access to flash interface */
2713 bnx2_disable_nvram_access(bp);
2714 bnx2_release_nvram_lock(bp);
2715
2716 /* Increment written */
2717 written += data_end - data_start;
2718 }
2719
2720nvram_write_end:
2721 if (align_start || align_end)
2722 kfree(buf);
2723 return rc;
2724}
2725
2726static int
2727bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2728{
2729 u32 val;
2730 int i, rc = 0;
2731
2732 /* Wait for the current PCI transaction to complete before
2733 * issuing a reset. */
2734 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2735 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2736 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2737 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2738 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2739 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2740 udelay(5);
2741
2742 /* Deposit a driver reset signature so the firmware knows that
2743 * this is a soft reset. */
2744 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2745 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2746
2747 bp->fw_timed_out = 0;
2748
2749 /* Wait for the firmware to tell us it is ok to issue a reset. */
2750 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2751
2752 /* Do a dummy read to force the chip to complete all current transaction
2753 * before we issue a reset. */
2754 val = REG_RD(bp, BNX2_MISC_ID);
2755
2756 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2757 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2758 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2759
2760 /* Chip reset. */
2761 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2762
2763 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2764 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2765 msleep(15);
2766
2767 /* Reset takes approximate 30 usec */
2768 for (i = 0; i < 10; i++) {
2769 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2770 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2771 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2772 break;
2773 }
2774 udelay(10);
2775 }
2776
2777 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2778 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2779 printk(KERN_ERR PFX "Chip reset did not complete\n");
2780 return -EBUSY;
2781 }
2782
2783 /* Make sure byte swapping is properly configured. */
2784 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2785 if (val != 0x01020304) {
2786 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2787 return -ENODEV;
2788 }
2789
2790 bp->fw_timed_out = 0;
2791
2792 /* Wait for the firmware to finish its initialization. */
2793 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2794
2795 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2796 /* Adjust the voltage regular to two steps lower. The default
2797 * of this register is 0x0000000e. */
2798 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2799
2800 /* Remove bad rbuf memory from the free pool. */
2801 rc = bnx2_alloc_bad_rbuf(bp);
2802 }
2803
2804 return rc;
2805}
2806
2807static int
2808bnx2_init_chip(struct bnx2 *bp)
2809{
2810 u32 val;
2811
2812 /* Make sure the interrupt is not active. */
2813 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2814
2815 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2816 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2817#ifdef __BIG_ENDIAN
2818 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2819#endif
2820 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2821 DMA_READ_CHANS << 12 |
2822 DMA_WRITE_CHANS << 16;
2823
2824 val |= (0x2 << 20) | (1 << 11);
2825
2826 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2827 val |= (1 << 23);
2828
2829 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2830 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2831 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2832
2833 REG_WR(bp, BNX2_DMA_CONFIG, val);
2834
2835 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2836 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2837 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2838 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2839 }
2840
2841 if (bp->flags & PCIX_FLAG) {
2842 u16 val16;
2843
2844 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2845 &val16);
2846 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2847 val16 & ~PCI_X_CMD_ERO);
2848 }
2849
2850 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2851 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2852 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2853 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2854
2855 /* Initialize context mapping and zero out the quick contexts. The
2856 * context block must have already been enabled. */
2857 bnx2_init_context(bp);
2858
2859 bnx2_init_cpus(bp);
2860 bnx2_init_nvram(bp);
2861
2862 bnx2_set_mac_addr(bp);
2863
2864 val = REG_RD(bp, BNX2_MQ_CONFIG);
2865 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2866 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2867 REG_WR(bp, BNX2_MQ_CONFIG, val);
2868
2869 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2870 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2871 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2872
2873 val = (BCM_PAGE_BITS - 8) << 24;
2874 REG_WR(bp, BNX2_RV2P_CONFIG, val);
2875
2876 /* Configure page size. */
2877 val = REG_RD(bp, BNX2_TBDR_CONFIG);
2878 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2879 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2880 REG_WR(bp, BNX2_TBDR_CONFIG, val);
2881
2882 val = bp->mac_addr[0] +
2883 (bp->mac_addr[1] << 8) +
2884 (bp->mac_addr[2] << 16) +
2885 bp->mac_addr[3] +
2886 (bp->mac_addr[4] << 8) +
2887 (bp->mac_addr[5] << 16);
2888 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2889
2890 /* Program the MTU. Also include 4 bytes for CRC32. */
2891 val = bp->dev->mtu + ETH_HLEN + 4;
2892 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2893 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2894 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2895
2896 bp->last_status_idx = 0;
2897 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2898
2899 /* Set up how to generate a link change interrupt. */
2900 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2901
2902 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2903 (u64) bp->status_blk_mapping & 0xffffffff);
2904 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2905
2906 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2907 (u64) bp->stats_blk_mapping & 0xffffffff);
2908 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2909 (u64) bp->stats_blk_mapping >> 32);
2910
2911 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2912 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2913
2914 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2915 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2916
2917 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2918 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2919
2920 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2921
2922 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2923
2924 REG_WR(bp, BNX2_HC_COM_TICKS,
2925 (bp->com_ticks_int << 16) | bp->com_ticks);
2926
2927 REG_WR(bp, BNX2_HC_CMD_TICKS,
2928 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2929
2930 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2931 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2932
2933 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2934 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2935 else {
2936 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2937 BNX2_HC_CONFIG_TX_TMR_MODE |
2938 BNX2_HC_CONFIG_COLLECT_STATS);
2939 }
2940
2941 /* Clear internal stats counters. */
2942 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2943
2944 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2945
2946 /* Initialize the receive filter. */
2947 bnx2_set_rx_mode(bp->dev);
2948
2949 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2950
2951 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2952 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2953
2954 udelay(20);
2955
2956 return 0;
2957}
2958
2959
2960static void
2961bnx2_init_tx_ring(struct bnx2 *bp)
2962{
2963 struct tx_bd *txbd;
2964 u32 val;
2965
2966 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2967
2968 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2969 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2970
2971 bp->tx_prod = 0;
2972 bp->tx_cons = 0;
2973 bp->tx_prod_bseq = 0;
2974 atomic_set(&bp->tx_avail_bd, bp->tx_ring_size);
2975
2976 val = BNX2_L2CTX_TYPE_TYPE_L2;
2977 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2978 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2979
2980 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2981 val |= 8 << 16;
2982 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2983
2984 val = (u64) bp->tx_desc_mapping >> 32;
2985 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2986
2987 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2988 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2989}
2990
2991static void
2992bnx2_init_rx_ring(struct bnx2 *bp)
2993{
2994 struct rx_bd *rxbd;
2995 int i;
2996 u16 prod, ring_prod;
2997 u32 val;
2998
2999 /* 8 for CRC and VLAN */
3000 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3001 /* 8 for alignment */
3002 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3003
3004 ring_prod = prod = bp->rx_prod = 0;
3005 bp->rx_cons = 0;
3006 bp->rx_prod_bseq = 0;
3007
3008 rxbd = &bp->rx_desc_ring[0];
3009 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3010 rxbd->rx_bd_len = bp->rx_buf_use_size;
3011 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3012 }
3013
3014 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3015 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3016
3017 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3018 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3019 val |= 0x02 << 8;
3020 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3021
3022 val = (u64) bp->rx_desc_mapping >> 32;
3023 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3024
3025 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3026 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3027
3028 for ( ;ring_prod < bp->rx_ring_size; ) {
3029 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3030 break;
3031 }
3032 prod = NEXT_RX_BD(prod);
3033 ring_prod = RX_RING_IDX(prod);
3034 }
3035 bp->rx_prod = prod;
3036
3037 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3038
3039 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3040}
3041
3042static void
3043bnx2_free_tx_skbs(struct bnx2 *bp)
3044{
3045 int i;
3046
3047 if (bp->tx_buf_ring == NULL)
3048 return;
3049
3050 for (i = 0; i < TX_DESC_CNT; ) {
3051 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3052 struct sk_buff *skb = tx_buf->skb;
3053 int j, last;
3054
3055 if (skb == NULL) {
3056 i++;
3057 continue;
3058 }
3059
3060 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3061 skb_headlen(skb), PCI_DMA_TODEVICE);
3062
3063 tx_buf->skb = NULL;
3064
3065 last = skb_shinfo(skb)->nr_frags;
3066 for (j = 0; j < last; j++) {
3067 tx_buf = &bp->tx_buf_ring[i + j + 1];
3068 pci_unmap_page(bp->pdev,
3069 pci_unmap_addr(tx_buf, mapping),
3070 skb_shinfo(skb)->frags[j].size,
3071 PCI_DMA_TODEVICE);
3072 }
3073 dev_kfree_skb_any(skb);
3074 i += j + 1;
3075 }
3076
3077}
3078
3079static void
3080bnx2_free_rx_skbs(struct bnx2 *bp)
3081{
3082 int i;
3083
3084 if (bp->rx_buf_ring == NULL)
3085 return;
3086
3087 for (i = 0; i < RX_DESC_CNT; i++) {
3088 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3089 struct sk_buff *skb = rx_buf->skb;
3090
3091 if (skb == 0)
3092 continue;
3093
3094 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3095 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3096
3097 rx_buf->skb = NULL;
3098
3099 dev_kfree_skb_any(skb);
3100 }
3101}
3102
3103static void
3104bnx2_free_skbs(struct bnx2 *bp)
3105{
3106 bnx2_free_tx_skbs(bp);
3107 bnx2_free_rx_skbs(bp);
3108}
3109
3110static int
3111bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3112{
3113 int rc;
3114
3115 rc = bnx2_reset_chip(bp, reset_code);
3116 bnx2_free_skbs(bp);
3117 if (rc)
3118 return rc;
3119
3120 bnx2_init_chip(bp);
3121 bnx2_init_tx_ring(bp);
3122 bnx2_init_rx_ring(bp);
3123 return 0;
3124}
3125
3126static int
3127bnx2_init_nic(struct bnx2 *bp)
3128{
3129 int rc;
3130
3131 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3132 return rc;
3133
3134 bnx2_init_phy(bp);
3135 bnx2_set_link(bp);
3136 return 0;
3137}
3138
3139static int
3140bnx2_test_registers(struct bnx2 *bp)
3141{
3142 int ret;
3143 int i;
3144 static struct {
3145 u16 offset;
3146 u16 flags;
3147 u32 rw_mask;
3148 u32 ro_mask;
3149 } reg_tbl[] = {
3150 { 0x006c, 0, 0x00000000, 0x0000003f },
3151 { 0x0090, 0, 0xffffffff, 0x00000000 },
3152 { 0x0094, 0, 0x00000000, 0x00000000 },
3153
3154 { 0x0404, 0, 0x00003f00, 0x00000000 },
3155 { 0x0418, 0, 0x00000000, 0xffffffff },
3156 { 0x041c, 0, 0x00000000, 0xffffffff },
3157 { 0x0420, 0, 0x00000000, 0x80ffffff },
3158 { 0x0424, 0, 0x00000000, 0x00000000 },
3159 { 0x0428, 0, 0x00000000, 0x00000001 },
3160 { 0x0450, 0, 0x00000000, 0x0000ffff },
3161 { 0x0454, 0, 0x00000000, 0xffffffff },
3162 { 0x0458, 0, 0x00000000, 0xffffffff },
3163
3164 { 0x0808, 0, 0x00000000, 0xffffffff },
3165 { 0x0854, 0, 0x00000000, 0xffffffff },
3166 { 0x0868, 0, 0x00000000, 0x77777777 },
3167 { 0x086c, 0, 0x00000000, 0x77777777 },
3168 { 0x0870, 0, 0x00000000, 0x77777777 },
3169 { 0x0874, 0, 0x00000000, 0x77777777 },
3170
3171 { 0x0c00, 0, 0x00000000, 0x00000001 },
3172 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3173 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3174 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3175 { 0x0c30, 0, 0x00000000, 0xffffffff },
3176 { 0x0c34, 0, 0x00000000, 0xffffffff },
3177 { 0x0c38, 0, 0x00000000, 0xffffffff },
3178 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3179 { 0x0c40, 0, 0x00000000, 0xffffffff },
3180 { 0x0c44, 0, 0x00000000, 0xffffffff },
3181 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3182 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3183 { 0x0c50, 0, 0x00000000, 0xffffffff },
3184 { 0x0c54, 0, 0x00000000, 0xffffffff },
3185 { 0x0c58, 0, 0x00000000, 0xffffffff },
3186 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3187 { 0x0c60, 0, 0x00000000, 0xffffffff },
3188 { 0x0c64, 0, 0x00000000, 0xffffffff },
3189 { 0x0c68, 0, 0x00000000, 0xffffffff },
3190 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3191 { 0x0c70, 0, 0x00000000, 0xffffffff },
3192 { 0x0c74, 0, 0x00000000, 0xffffffff },
3193 { 0x0c78, 0, 0x00000000, 0xffffffff },
3194 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3195 { 0x0c80, 0, 0x00000000, 0xffffffff },
3196 { 0x0c84, 0, 0x00000000, 0xffffffff },
3197 { 0x0c88, 0, 0x00000000, 0xffffffff },
3198 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3199 { 0x0c90, 0, 0x00000000, 0xffffffff },
3200 { 0x0c94, 0, 0x00000000, 0xffffffff },
3201 { 0x0c98, 0, 0x00000000, 0xffffffff },
3202 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3203 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3204 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3205 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3206 { 0x0cac, 0, 0x00000000, 0xffffffff },
3207 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3208 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3209 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3210 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3211 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3212 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3213 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3214 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3215 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3216 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3217 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3218 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3219 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3220 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3221 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3222 { 0x0cec, 0, 0x00000000, 0xffffffff },
3223 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3224 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3225 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3226 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3227 { 0x0d00, 0, 0x00000000, 0xffffffff },
3228 { 0x0d04, 0, 0x00000000, 0xffffffff },
3229
3230 { 0x1000, 0, 0x00000000, 0x00000001 },
3231 { 0x1004, 0, 0x00000000, 0x000f0001 },
3232 { 0x1044, 0, 0x00000000, 0xffc003ff },
3233 { 0x1080, 0, 0x00000000, 0x0001ffff },
3234 { 0x1084, 0, 0x00000000, 0xffffffff },
3235 { 0x1088, 0, 0x00000000, 0xffffffff },
3236 { 0x108c, 0, 0x00000000, 0xffffffff },
3237 { 0x1090, 0, 0x00000000, 0xffffffff },
3238 { 0x1094, 0, 0x00000000, 0xffffffff },
3239 { 0x1098, 0, 0x00000000, 0xffffffff },
3240 { 0x109c, 0, 0x00000000, 0xffffffff },
3241 { 0x10a0, 0, 0x00000000, 0xffffffff },
3242
3243 { 0x1408, 0, 0x01c00800, 0x00000000 },
3244 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3245 { 0x14a8, 0, 0x00000000, 0x000001ff },
3246 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3247 { 0x14b0, 0, 0x00000002, 0x00000001 },
3248 { 0x14b8, 0, 0x00000000, 0x00000000 },
3249 { 0x14c0, 0, 0x00000000, 0x00000009 },
3250 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3251 { 0x14cc, 0, 0x00000000, 0x00000001 },
3252 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3253 { 0x1500, 0, 0x00000000, 0xffffffff },
3254 { 0x1504, 0, 0x00000000, 0xffffffff },
3255 { 0x1508, 0, 0x00000000, 0xffffffff },
3256 { 0x150c, 0, 0x00000000, 0xffffffff },
3257 { 0x1510, 0, 0x00000000, 0xffffffff },
3258 { 0x1514, 0, 0x00000000, 0xffffffff },
3259 { 0x1518, 0, 0x00000000, 0xffffffff },
3260 { 0x151c, 0, 0x00000000, 0xffffffff },
3261 { 0x1520, 0, 0x00000000, 0xffffffff },
3262 { 0x1524, 0, 0x00000000, 0xffffffff },
3263 { 0x1528, 0, 0x00000000, 0xffffffff },
3264 { 0x152c, 0, 0x00000000, 0xffffffff },
3265 { 0x1530, 0, 0x00000000, 0xffffffff },
3266 { 0x1534, 0, 0x00000000, 0xffffffff },
3267 { 0x1538, 0, 0x00000000, 0xffffffff },
3268 { 0x153c, 0, 0x00000000, 0xffffffff },
3269 { 0x1540, 0, 0x00000000, 0xffffffff },
3270 { 0x1544, 0, 0x00000000, 0xffffffff },
3271 { 0x1548, 0, 0x00000000, 0xffffffff },
3272 { 0x154c, 0, 0x00000000, 0xffffffff },
3273 { 0x1550, 0, 0x00000000, 0xffffffff },
3274 { 0x1554, 0, 0x00000000, 0xffffffff },
3275 { 0x1558, 0, 0x00000000, 0xffffffff },
3276 { 0x1600, 0, 0x00000000, 0xffffffff },
3277 { 0x1604, 0, 0x00000000, 0xffffffff },
3278 { 0x1608, 0, 0x00000000, 0xffffffff },
3279 { 0x160c, 0, 0x00000000, 0xffffffff },
3280 { 0x1610, 0, 0x00000000, 0xffffffff },
3281 { 0x1614, 0, 0x00000000, 0xffffffff },
3282 { 0x1618, 0, 0x00000000, 0xffffffff },
3283 { 0x161c, 0, 0x00000000, 0xffffffff },
3284 { 0x1620, 0, 0x00000000, 0xffffffff },
3285 { 0x1624, 0, 0x00000000, 0xffffffff },
3286 { 0x1628, 0, 0x00000000, 0xffffffff },
3287 { 0x162c, 0, 0x00000000, 0xffffffff },
3288 { 0x1630, 0, 0x00000000, 0xffffffff },
3289 { 0x1634, 0, 0x00000000, 0xffffffff },
3290 { 0x1638, 0, 0x00000000, 0xffffffff },
3291 { 0x163c, 0, 0x00000000, 0xffffffff },
3292 { 0x1640, 0, 0x00000000, 0xffffffff },
3293 { 0x1644, 0, 0x00000000, 0xffffffff },
3294 { 0x1648, 0, 0x00000000, 0xffffffff },
3295 { 0x164c, 0, 0x00000000, 0xffffffff },
3296 { 0x1650, 0, 0x00000000, 0xffffffff },
3297 { 0x1654, 0, 0x00000000, 0xffffffff },
3298
3299 { 0x1800, 0, 0x00000000, 0x00000001 },
3300 { 0x1804, 0, 0x00000000, 0x00000003 },
3301 { 0x1840, 0, 0x00000000, 0xffffffff },
3302 { 0x1844, 0, 0x00000000, 0xffffffff },
3303 { 0x1848, 0, 0x00000000, 0xffffffff },
3304 { 0x184c, 0, 0x00000000, 0xffffffff },
3305 { 0x1850, 0, 0x00000000, 0xffffffff },
3306 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3307 { 0x1904, 0, 0xffffffff, 0x00000000 },
3308 { 0x190c, 0, 0xffffffff, 0x00000000 },
3309 { 0x1914, 0, 0xffffffff, 0x00000000 },
3310 { 0x191c, 0, 0xffffffff, 0x00000000 },
3311 { 0x1924, 0, 0xffffffff, 0x00000000 },
3312 { 0x192c, 0, 0xffffffff, 0x00000000 },
3313 { 0x1934, 0, 0xffffffff, 0x00000000 },
3314 { 0x193c, 0, 0xffffffff, 0x00000000 },
3315 { 0x1944, 0, 0xffffffff, 0x00000000 },
3316 { 0x194c, 0, 0xffffffff, 0x00000000 },
3317 { 0x1954, 0, 0xffffffff, 0x00000000 },
3318 { 0x195c, 0, 0xffffffff, 0x00000000 },
3319 { 0x1964, 0, 0xffffffff, 0x00000000 },
3320 { 0x196c, 0, 0xffffffff, 0x00000000 },
3321 { 0x1974, 0, 0xffffffff, 0x00000000 },
3322 { 0x197c, 0, 0xffffffff, 0x00000000 },
3323 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3324
3325 { 0x1c00, 0, 0x00000000, 0x00000001 },
3326 { 0x1c04, 0, 0x00000000, 0x00000003 },
3327 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3328 { 0x1c40, 0, 0x00000000, 0xffffffff },
3329 { 0x1c44, 0, 0x00000000, 0xffffffff },
3330 { 0x1c48, 0, 0x00000000, 0xffffffff },
3331 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3332 { 0x1c50, 0, 0x00000000, 0xffffffff },
3333 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3334 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3339 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3340 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3341 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3342 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3343 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3344 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3345 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3346 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3347 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3348 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3349 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3350 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3351
3352 { 0x2004, 0, 0x00000000, 0x0337000f },
3353 { 0x2008, 0, 0xffffffff, 0x00000000 },
3354 { 0x200c, 0, 0xffffffff, 0x00000000 },
3355 { 0x2010, 0, 0xffffffff, 0x00000000 },
3356 { 0x2014, 0, 0x801fff80, 0x00000000 },
3357 { 0x2018, 0, 0x000003ff, 0x00000000 },
3358
3359 { 0x2800, 0, 0x00000000, 0x00000001 },
3360 { 0x2804, 0, 0x00000000, 0x00003f01 },
3361 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3362 { 0x2810, 0, 0xffff0000, 0x00000000 },
3363 { 0x2814, 0, 0xffff0000, 0x00000000 },
3364 { 0x2818, 0, 0xffff0000, 0x00000000 },
3365 { 0x281c, 0, 0xffff0000, 0x00000000 },
3366 { 0x2834, 0, 0xffffffff, 0x00000000 },
3367 { 0x2840, 0, 0x00000000, 0xffffffff },
3368 { 0x2844, 0, 0x00000000, 0xffffffff },
3369 { 0x2848, 0, 0xffffffff, 0x00000000 },
3370 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3371
3372 { 0x2c00, 0, 0x00000000, 0x00000011 },
3373 { 0x2c04, 0, 0x00000000, 0x00030007 },
3374
3375 { 0x3000, 0, 0x00000000, 0x00000001 },
3376 { 0x3004, 0, 0x00000000, 0x007007ff },
3377 { 0x3008, 0, 0x00000003, 0x00000000 },
3378 { 0x300c, 0, 0xffffffff, 0x00000000 },
3379 { 0x3010, 0, 0xffffffff, 0x00000000 },
3380 { 0x3014, 0, 0xffffffff, 0x00000000 },
3381 { 0x3034, 0, 0xffffffff, 0x00000000 },
3382 { 0x3038, 0, 0xffffffff, 0x00000000 },
3383 { 0x3050, 0, 0x00000001, 0x00000000 },
3384
3385 { 0x3c00, 0, 0x00000000, 0x00000001 },
3386 { 0x3c04, 0, 0x00000000, 0x00070000 },
3387 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3388 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3389 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c14, 0, 0x00000000, 0xffffffff },
3391 { 0x3c18, 0, 0x00000000, 0xffffffff },
3392 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3393 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3394 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3403 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3404 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3405 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3406 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3407 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3408 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3409 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3410 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3411 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3412 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3413 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3414 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3415 { 0x3c78, 0, 0x00000000, 0x00000000 },
3416 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3417 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3418 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3419 { 0x3c88, 0, 0x00000000, 0xffffffff },
3420 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3421
3422 { 0x4000, 0, 0x00000000, 0x00000001 },
3423 { 0x4004, 0, 0x00000000, 0x00030000 },
3424 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3425 { 0x400c, 0, 0xffffffff, 0x00000000 },
3426 { 0x4088, 0, 0x00000000, 0x00070303 },
3427
3428 { 0x4400, 0, 0x00000000, 0x00000001 },
3429 { 0x4404, 0, 0x00000000, 0x00003f01 },
3430 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3431 { 0x440c, 0, 0xffffffff, 0x00000000 },
3432 { 0x4410, 0, 0xffff, 0x0000 },
3433 { 0x4414, 0, 0xffff, 0x0000 },
3434 { 0x4418, 0, 0xffff, 0x0000 },
3435 { 0x441c, 0, 0xffff, 0x0000 },
3436 { 0x4428, 0, 0xffffffff, 0x00000000 },
3437 { 0x442c, 0, 0xffffffff, 0x00000000 },
3438 { 0x4430, 0, 0xffffffff, 0x00000000 },
3439 { 0x4434, 0, 0xffffffff, 0x00000000 },
3440 { 0x4438, 0, 0xffffffff, 0x00000000 },
3441 { 0x443c, 0, 0xffffffff, 0x00000000 },
3442 { 0x4440, 0, 0xffffffff, 0x00000000 },
3443 { 0x4444, 0, 0xffffffff, 0x00000000 },
3444
3445 { 0x4c00, 0, 0x00000000, 0x00000001 },
3446 { 0x4c04, 0, 0x00000000, 0x0000003f },
3447 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3448 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3449 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3450 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3451 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3452 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3453 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3454 { 0x4c50, 0, 0x00000000, 0xffffffff },
3455
3456 { 0x5004, 0, 0x00000000, 0x0000007f },
3457 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3458 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3459
3460 { 0x5400, 0, 0x00000008, 0x00000001 },
3461 { 0x5404, 0, 0x00000000, 0x0000003f },
3462 { 0x5408, 0, 0x0000001f, 0x00000000 },
3463 { 0x540c, 0, 0xffffffff, 0x00000000 },
3464 { 0x5410, 0, 0xffffffff, 0x00000000 },
3465 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3466 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3467 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3468 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3469 { 0x5428, 0, 0x000000ff, 0x00000000 },
3470 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3471 { 0x5430, 0, 0x001fff80, 0x00000000 },
3472 { 0x5438, 0, 0xffffffff, 0x00000000 },
3473 { 0x543c, 0, 0xffffffff, 0x00000000 },
3474 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3475
3476 { 0x5c00, 0, 0x00000000, 0x00000001 },
3477 { 0x5c04, 0, 0x00000000, 0x0003000f },
3478 { 0x5c08, 0, 0x00000003, 0x00000000 },
3479 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3480 { 0x5c10, 0, 0x00000000, 0xffffffff },
3481 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3482 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3483 { 0x5c88, 0, 0x00000000, 0x00077373 },
3484 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3485
3486 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3487 { 0x680c, 0, 0xffffffff, 0x00000000 },
3488 { 0x6810, 0, 0xffffffff, 0x00000000 },
3489 { 0x6814, 0, 0xffffffff, 0x00000000 },
3490 { 0x6818, 0, 0xffffffff, 0x00000000 },
3491 { 0x681c, 0, 0xffffffff, 0x00000000 },
3492 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3493 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3494 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3495 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3496 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3497 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3498 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3499 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3500 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3501 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3502 { 0x684c, 0, 0xffffffff, 0x00000000 },
3503 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3504 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3505 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3506 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3507 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3508 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3509
3510 { 0xffff, 0, 0x00000000, 0x00000000 },
3511 };
3512
3513 ret = 0;
3514 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3515 u32 offset, rw_mask, ro_mask, save_val, val;
3516
3517 offset = (u32) reg_tbl[i].offset;
3518 rw_mask = reg_tbl[i].rw_mask;
3519 ro_mask = reg_tbl[i].ro_mask;
3520
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3521 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3522
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3523 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3524
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3525 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3526 if ((val & rw_mask) != 0) {
3527 goto reg_test_err;
3528 }
3529
3530 if ((val & ro_mask) != (save_val & ro_mask)) {
3531 goto reg_test_err;
3532 }
3533
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3534 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3535
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3536 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3537 if ((val & rw_mask) != rw_mask) {
3538 goto reg_test_err;
3539 }
3540
3541 if ((val & ro_mask) != (save_val & ro_mask)) {
3542 goto reg_test_err;
3543 }
3544
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3545 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3546 continue;
3547
3548reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]3549 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3550 ret = -ENODEV;
3551 break;
3552 }
3553 return ret;
3554}
3555
3556static int
3557bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3558{
3559 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3560 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3561 int i;
3562
3563 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3564 u32 offset;
3565
3566 for (offset = 0; offset < size; offset += 4) {
3567
3568 REG_WR_IND(bp, start + offset, test_pattern[i]);
3569
3570 if (REG_RD_IND(bp, start + offset) !=
3571 test_pattern[i]) {
3572 return -ENODEV;
3573 }
3574 }
3575 }
3576 return 0;
3577}
3578
3579static int
3580bnx2_test_memory(struct bnx2 *bp)
3581{
3582 int ret = 0;
3583 int i;
3584 static struct {
3585 u32 offset;
3586 u32 len;
3587 } mem_tbl[] = {
3588 { 0x60000, 0x4000 },
3589 { 0xa0000, 0x4000 },
3590 { 0xe0000, 0x4000 },
3591 { 0x120000, 0x4000 },
3592 { 0x1a0000, 0x4000 },
3593 { 0x160000, 0x4000 },
3594 { 0xffffffff, 0 },
3595 };
3596
3597 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3598 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3599 mem_tbl[i].len)) != 0) {
3600 return ret;
3601 }
3602 }
3603
3604 return ret;
3605}
3606
3607static int
3608bnx2_test_loopback(struct bnx2 *bp)
3609{
3610 unsigned int pkt_size, num_pkts, i;
3611 struct sk_buff *skb, *rx_skb;
3612 unsigned char *packet;
3613 u16 rx_start_idx, rx_idx, send_idx;
3614 u32 send_bseq, val;
3615 dma_addr_t map;
3616 struct tx_bd *txbd;
3617 struct sw_bd *rx_buf;
3618 struct l2_fhdr *rx_hdr;
3619 int ret = -ENODEV;
3620
3621 if (!netif_running(bp->dev))
3622 return -ENODEV;
3623
3624 bp->loopback = MAC_LOOPBACK;
3625 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3626 bnx2_set_mac_loopback(bp);
3627
3628 pkt_size = 1514;
3629 skb = dev_alloc_skb(pkt_size);
3630 packet = skb_put(skb, pkt_size);
3631 memcpy(packet, bp->mac_addr, 6);
3632 memset(packet + 6, 0x0, 8);
3633 for (i = 14; i < pkt_size; i++)
3634 packet[i] = (unsigned char) (i & 0xff);
3635
3636 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3637 PCI_DMA_TODEVICE);
3638
3639 val = REG_RD(bp, BNX2_HC_COMMAND);
3640 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3641 REG_RD(bp, BNX2_HC_COMMAND);
3642
3643 udelay(5);
3644 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3645
3646 send_idx = 0;
3647 send_bseq = 0;
3648 num_pkts = 0;
3649
3650 txbd = &bp->tx_desc_ring[send_idx];
3651
3652 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3653 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3654 txbd->tx_bd_mss_nbytes = pkt_size;
3655 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3656
3657 num_pkts++;
3658 send_idx = NEXT_TX_BD(send_idx);
3659
3660 send_bseq += pkt_size;
3661
3662 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3663 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3664
3665
3666 udelay(100);
3667
3668 val = REG_RD(bp, BNX2_HC_COMMAND);
3669 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3670 REG_RD(bp, BNX2_HC_COMMAND);
3671
3672 udelay(5);
3673
3674 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3675 dev_kfree_skb_irq(skb);
3676
3677 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3678 goto loopback_test_done;
3679 }
3680
3681 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3682 if (rx_idx != rx_start_idx + num_pkts) {
3683 goto loopback_test_done;
3684 }
3685
3686 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3687 rx_skb = rx_buf->skb;
3688
3689 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3690 skb_reserve(rx_skb, bp->rx_offset);
3691
3692 pci_dma_sync_single_for_cpu(bp->pdev,
3693 pci_unmap_addr(rx_buf, mapping),
3694 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3695
3696 if (rx_hdr->l2_fhdr_errors &
3697 (L2_FHDR_ERRORS_BAD_CRC |
3698 L2_FHDR_ERRORS_PHY_DECODE |
3699 L2_FHDR_ERRORS_ALIGNMENT |
3700 L2_FHDR_ERRORS_TOO_SHORT |
3701 L2_FHDR_ERRORS_GIANT_FRAME)) {
3702
3703 goto loopback_test_done;
3704 }
3705
3706 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3707 goto loopback_test_done;
3708 }
3709
3710 for (i = 14; i < pkt_size; i++) {
3711 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3712 goto loopback_test_done;
3713 }
3714 }
3715
3716 ret = 0;
3717
3718loopback_test_done:
3719 bp->loopback = 0;
3720 return ret;
3721}
3722
3723#define NVRAM_SIZE 0x200
3724#define CRC32_RESIDUAL 0xdebb20e3
3725
3726static int
3727bnx2_test_nvram(struct bnx2 *bp)
3728{
3729 u32 buf[NVRAM_SIZE / 4];
3730 u8 *data = (u8 *) buf;
3731 int rc = 0;
3732 u32 magic, csum;
3733
3734 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3735 goto test_nvram_done;
3736
3737 magic = be32_to_cpu(buf[0]);
3738 if (magic != 0x669955aa) {
3739 rc = -ENODEV;
3740 goto test_nvram_done;
3741 }
3742
3743 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3744 goto test_nvram_done;
3745
3746 csum = ether_crc_le(0x100, data);
3747 if (csum != CRC32_RESIDUAL) {
3748 rc = -ENODEV;
3749 goto test_nvram_done;
3750 }
3751
3752 csum = ether_crc_le(0x100, data + 0x100);
3753 if (csum != CRC32_RESIDUAL) {
3754 rc = -ENODEV;
3755 }
3756
3757test_nvram_done:
3758 return rc;
3759}
3760
3761static int
3762bnx2_test_link(struct bnx2 *bp)
3763{
3764 u32 bmsr;
3765
3766 spin_lock_irq(&bp->phy_lock);
3767 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3768 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3769 spin_unlock_irq(&bp->phy_lock);
3770
3771 if (bmsr & BMSR_LSTATUS) {
3772 return 0;
3773 }
3774 return -ENODEV;
3775}
3776
3777static int
3778bnx2_test_intr(struct bnx2 *bp)
3779{
3780 int i;
3781 u32 val;
3782 u16 status_idx;
3783
3784 if (!netif_running(bp->dev))
3785 return -ENODEV;
3786
3787 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3788
3789 /* This register is not touched during run-time. */
3790 val = REG_RD(bp, BNX2_HC_COMMAND);
3791 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3792 REG_RD(bp, BNX2_HC_COMMAND);
3793
3794 for (i = 0; i < 10; i++) {
3795 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3796 status_idx) {
3797
3798 break;
3799 }
3800
3801 msleep_interruptible(10);
3802 }
3803 if (i < 10)
3804 return 0;
3805
3806 return -ENODEV;
3807}
3808
3809static void
3810bnx2_timer(unsigned long data)
3811{
3812 struct bnx2 *bp = (struct bnx2 *) data;
3813 u32 msg;
3814
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]3815 if (!netif_running(bp->dev))
3816 return;
3817
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3818 if (atomic_read(&bp->intr_sem) != 0)
3819 goto bnx2_restart_timer;
3820
3821 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3822 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3823
3824 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3825 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3826 unsigned long flags;
3827
3828 spin_lock_irqsave(&bp->phy_lock, flags);
3829 if (bp->serdes_an_pending) {
3830 bp->serdes_an_pending--;
3831 }
3832 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3833 u32 bmcr;
3834
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]3835 bp->current_interval = bp->timer_interval;
3836
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3837 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3838
3839 if (bmcr & BMCR_ANENABLE) {
3840 u32 phy1, phy2;
3841
3842 bnx2_write_phy(bp, 0x1c, 0x7c00);
3843 bnx2_read_phy(bp, 0x1c, &phy1);
3844
3845 bnx2_write_phy(bp, 0x17, 0x0f01);
3846 bnx2_read_phy(bp, 0x15, &phy2);
3847 bnx2_write_phy(bp, 0x17, 0x0f01);
3848 bnx2_read_phy(bp, 0x15, &phy2);
3849
3850 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3851 !(phy2 & 0x20)) { /* no CONFIG */
3852
3853 bmcr &= ~BMCR_ANENABLE;
3854 bmcr |= BMCR_SPEED1000 |
3855 BMCR_FULLDPLX;
3856 bnx2_write_phy(bp, MII_BMCR, bmcr);
3857 bp->phy_flags |=
3858 PHY_PARALLEL_DETECT_FLAG;
3859 }
3860 }
3861 }
3862 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3863 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3864 u32 phy2;
3865
3866 bnx2_write_phy(bp, 0x17, 0x0f01);
3867 bnx2_read_phy(bp, 0x15, &phy2);
3868 if (phy2 & 0x20) {
3869 u32 bmcr;
3870
3871 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3872 bmcr |= BMCR_ANENABLE;
3873 bnx2_write_phy(bp, MII_BMCR, bmcr);
3874
3875 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3876
3877 }
3878 }
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]3879 else
3880 bp->current_interval = bp->timer_interval;
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3881
3882 spin_unlock_irqrestore(&bp->phy_lock, flags);
3883 }
3884
3885bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]3886 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3887}
3888
3889/* Called with rtnl_lock */
3890static int
3891bnx2_open(struct net_device *dev)
3892{
3893 struct bnx2 *bp = dev->priv;
3894 int rc;
3895
3896 bnx2_set_power_state(bp, 0);
3897 bnx2_disable_int(bp);
3898
3899 rc = bnx2_alloc_mem(bp);
3900 if (rc)
3901 return rc;
3902
3903 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3904 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3905 !disable_msi) {
3906
3907 if (pci_enable_msi(bp->pdev) == 0) {
3908 bp->flags |= USING_MSI_FLAG;
3909 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3910 dev);
3911 }
3912 else {
3913 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3914 SA_SHIRQ, dev->name, dev);
3915 }
3916 }
3917 else {
3918 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3919 dev->name, dev);
3920 }
3921 if (rc) {
3922 bnx2_free_mem(bp);
3923 return rc;
3924 }
3925
3926 rc = bnx2_init_nic(bp);
3927
3928 if (rc) {
3929 free_irq(bp->pdev->irq, dev);
3930 if (bp->flags & USING_MSI_FLAG) {
3931 pci_disable_msi(bp->pdev);
3932 bp->flags &= ~USING_MSI_FLAG;
3933 }
3934 bnx2_free_skbs(bp);
3935 bnx2_free_mem(bp);
3936 return rc;
3937 }
3938
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]3939 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3940
3941 atomic_set(&bp->intr_sem, 0);
3942
3943 bnx2_enable_int(bp);
3944
3945 if (bp->flags & USING_MSI_FLAG) {
3946 /* Test MSI to make sure it is working
3947 * If MSI test fails, go back to INTx mode
3948 */
3949 if (bnx2_test_intr(bp) != 0) {
3950 printk(KERN_WARNING PFX "%s: No interrupt was generated"
3951 " using MSI, switching to INTx mode. Please"
3952 " report this failure to the PCI maintainer"
3953 " and include system chipset information.\n",
3954 bp->dev->name);
3955
3956 bnx2_disable_int(bp);
3957 free_irq(bp->pdev->irq, dev);
3958 pci_disable_msi(bp->pdev);
3959 bp->flags &= ~USING_MSI_FLAG;
3960
3961 rc = bnx2_init_nic(bp);
3962
3963 if (!rc) {
3964 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3965 SA_SHIRQ, dev->name, dev);
3966 }
3967 if (rc) {
3968 bnx2_free_skbs(bp);
3969 bnx2_free_mem(bp);
3970 del_timer_sync(&bp->timer);
3971 return rc;
3972 }
3973 bnx2_enable_int(bp);
3974 }
3975 }
3976 if (bp->flags & USING_MSI_FLAG) {
3977 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3978 }
3979
3980 netif_start_queue(dev);
3981
3982 return 0;
3983}
3984
3985static void
3986bnx2_reset_task(void *data)
3987{
3988 struct bnx2 *bp = data;
3989
Michael Chanafdc08b2005-08-25 15:34:29 -0700[diff] [blame]3990 if (!netif_running(bp->dev))
3991 return;
3992
3993 bp->in_reset_task = 1;
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]3994 bnx2_netif_stop(bp);
3995
3996 bnx2_init_nic(bp);
3997
3998 atomic_set(&bp->intr_sem, 1);
3999 bnx2_netif_start(bp);
Michael Chanafdc08b2005-08-25 15:34:29 -0700[diff] [blame]4000 bp->in_reset_task = 0;
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4001}
4002
4003static void
4004bnx2_tx_timeout(struct net_device *dev)
4005{
4006 struct bnx2 *bp = dev->priv;
4007
4008 /* This allows the netif to be shutdown gracefully before resetting */
4009 schedule_work(&bp->reset_task);
4010}
4011
4012#ifdef BCM_VLAN
4013/* Called with rtnl_lock */
4014static void
4015bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4016{
4017 struct bnx2 *bp = dev->priv;
4018
4019 bnx2_netif_stop(bp);
4020
4021 bp->vlgrp = vlgrp;
4022 bnx2_set_rx_mode(dev);
4023
4024 bnx2_netif_start(bp);
4025}
4026
4027/* Called with rtnl_lock */
4028static void
4029bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4030{
4031 struct bnx2 *bp = dev->priv;
4032
4033 bnx2_netif_stop(bp);
4034
4035 if (bp->vlgrp)
4036 bp->vlgrp->vlan_devices[vid] = NULL;
4037 bnx2_set_rx_mode(dev);
4038
4039 bnx2_netif_start(bp);
4040}
4041#endif
4042
4043/* Called with dev->xmit_lock.
4044 * hard_start_xmit is pseudo-lockless - a lock is only required when
4045 * the tx queue is full. This way, we get the benefit of lockless
4046 * operations most of the time without the complexities to handle
4047 * netif_stop_queue/wake_queue race conditions.
4048 */
4049static int
4050bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4051{
4052 struct bnx2 *bp = dev->priv;
4053 dma_addr_t mapping;
4054 struct tx_bd *txbd;
4055 struct sw_bd *tx_buf;
4056 u32 len, vlan_tag_flags, last_frag, mss;
4057 u16 prod, ring_prod;
4058 int i;
4059
4060 if (unlikely(atomic_read(&bp->tx_avail_bd) <
4061 (skb_shinfo(skb)->nr_frags + 1))) {
4062
4063 netif_stop_queue(dev);
4064 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4065 dev->name);
4066
4067 return NETDEV_TX_BUSY;
4068 }
4069 len = skb_headlen(skb);
4070 prod = bp->tx_prod;
4071 ring_prod = TX_RING_IDX(prod);
4072
4073 vlan_tag_flags = 0;
4074 if (skb->ip_summed == CHECKSUM_HW) {
4075 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4076 }
4077
4078 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4079 vlan_tag_flags |=
4080 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4081 }
4082#ifdef BCM_TSO
4083 if ((mss = skb_shinfo(skb)->tso_size) &&
4084 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4085 u32 tcp_opt_len, ip_tcp_len;
4086
4087 if (skb_header_cloned(skb) &&
4088 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4089 dev_kfree_skb(skb);
4090 return NETDEV_TX_OK;
4091 }
4092
4093 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4094 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4095
4096 tcp_opt_len = 0;
4097 if (skb->h.th->doff > 5) {
4098 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4099 }
4100 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4101
4102 skb->nh.iph->check = 0;
4103 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4104 skb->h.th->check =
4105 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4106 skb->nh.iph->daddr,
4107 0, IPPROTO_TCP, 0);
4108
4109 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4110 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4111 (tcp_opt_len >> 2)) << 8;
4112 }
4113 }
4114 else
4115#endif
4116 {
4117 mss = 0;
4118 }
4119
4120 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4121
4122 tx_buf = &bp->tx_buf_ring[ring_prod];
4123 tx_buf->skb = skb;
4124 pci_unmap_addr_set(tx_buf, mapping, mapping);
4125
4126 txbd = &bp->tx_desc_ring[ring_prod];
4127
4128 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4129 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4130 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4131 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4132
4133 last_frag = skb_shinfo(skb)->nr_frags;
4134
4135 for (i = 0; i < last_frag; i++) {
4136 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4137
4138 prod = NEXT_TX_BD(prod);
4139 ring_prod = TX_RING_IDX(prod);
4140 txbd = &bp->tx_desc_ring[ring_prod];
4141
4142 len = frag->size;
4143 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4144 len, PCI_DMA_TODEVICE);
4145 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4146 mapping, mapping);
4147
4148 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4149 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4150 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4151 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4152
4153 }
4154 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4155
4156 prod = NEXT_TX_BD(prod);
4157 bp->tx_prod_bseq += skb->len;
4158
4159 atomic_sub(last_frag + 1, &bp->tx_avail_bd);
4160
4161 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4162 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4163
4164 mmiowb();
4165
4166 bp->tx_prod = prod;
4167 dev->trans_start = jiffies;
4168
4169 if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) {
4170 unsigned long flags;
4171
4172 spin_lock_irqsave(&bp->tx_lock, flags);
4173 if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) {
4174 netif_stop_queue(dev);
4175
4176 if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)
4177 netif_wake_queue(dev);
4178 }
4179 spin_unlock_irqrestore(&bp->tx_lock, flags);
4180 }
4181
4182 return NETDEV_TX_OK;
4183}
4184
4185/* Called with rtnl_lock */
4186static int
4187bnx2_close(struct net_device *dev)
4188{
4189 struct bnx2 *bp = dev->priv;
4190 u32 reset_code;
4191
Michael Chanafdc08b2005-08-25 15:34:29 -0700[diff] [blame]4192 /* Calling flush_scheduled_work() may deadlock because
4193 * linkwatch_event() may be on the workqueue and it will try to get
4194 * the rtnl_lock which we are holding.
4195 */
4196 while (bp->in_reset_task)
4197 msleep(1);
4198
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4199 bnx2_netif_stop(bp);
4200 del_timer_sync(&bp->timer);
4201 if (bp->wol)
4202 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4203 else
4204 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4205 bnx2_reset_chip(bp, reset_code);
4206 free_irq(bp->pdev->irq, dev);
4207 if (bp->flags & USING_MSI_FLAG) {
4208 pci_disable_msi(bp->pdev);
4209 bp->flags &= ~USING_MSI_FLAG;
4210 }
4211 bnx2_free_skbs(bp);
4212 bnx2_free_mem(bp);
4213 bp->link_up = 0;
4214 netif_carrier_off(bp->dev);
4215 bnx2_set_power_state(bp, 3);
4216 return 0;
4217}
4218
4219#define GET_NET_STATS64(ctr) \
4220 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4221 (unsigned long) (ctr##_lo)
4222
4223#define GET_NET_STATS32(ctr) \
4224 (ctr##_lo)
4225
4226#if (BITS_PER_LONG == 64)
4227#define GET_NET_STATS GET_NET_STATS64
4228#else
4229#define GET_NET_STATS GET_NET_STATS32
4230#endif
4231
4232static struct net_device_stats *
4233bnx2_get_stats(struct net_device *dev)
4234{
4235 struct bnx2 *bp = dev->priv;
4236 struct statistics_block *stats_blk = bp->stats_blk;
4237 struct net_device_stats *net_stats = &bp->net_stats;
4238
4239 if (bp->stats_blk == NULL) {
4240 return net_stats;
4241 }
4242 net_stats->rx_packets =
4243 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4244 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4245 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4246
4247 net_stats->tx_packets =
4248 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4249 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4250 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4251
4252 net_stats->rx_bytes =
4253 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4254
4255 net_stats->tx_bytes =
4256 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4257
4258 net_stats->multicast =
4259 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4260
4261 net_stats->collisions =
4262 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4263
4264 net_stats->rx_length_errors =
4265 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4266 stats_blk->stat_EtherStatsOverrsizePkts);
4267
4268 net_stats->rx_over_errors =
4269 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4270
4271 net_stats->rx_frame_errors =
4272 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4273
4274 net_stats->rx_crc_errors =
4275 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4276
4277 net_stats->rx_errors = net_stats->rx_length_errors +
4278 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4279 net_stats->rx_crc_errors;
4280
4281 net_stats->tx_aborted_errors =
4282 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4283 stats_blk->stat_Dot3StatsLateCollisions);
4284
4285 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4286 net_stats->tx_carrier_errors = 0;
4287 else {
4288 net_stats->tx_carrier_errors =
4289 (unsigned long)
4290 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4291 }
4292
4293 net_stats->tx_errors =
4294 (unsigned long)
4295 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4296 +
4297 net_stats->tx_aborted_errors +
4298 net_stats->tx_carrier_errors;
4299
4300 return net_stats;
4301}
4302
4303/* All ethtool functions called with rtnl_lock */
4304
4305static int
4306bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4307{
4308 struct bnx2 *bp = dev->priv;
4309
4310 cmd->supported = SUPPORTED_Autoneg;
4311 if (bp->phy_flags & PHY_SERDES_FLAG) {
4312 cmd->supported |= SUPPORTED_1000baseT_Full |
4313 SUPPORTED_FIBRE;
4314
4315 cmd->port = PORT_FIBRE;
4316 }
4317 else {
4318 cmd->supported |= SUPPORTED_10baseT_Half |
4319 SUPPORTED_10baseT_Full |
4320 SUPPORTED_100baseT_Half |
4321 SUPPORTED_100baseT_Full |
4322 SUPPORTED_1000baseT_Full |
4323 SUPPORTED_TP;
4324
4325 cmd->port = PORT_TP;
4326 }
4327
4328 cmd->advertising = bp->advertising;
4329
4330 if (bp->autoneg & AUTONEG_SPEED) {
4331 cmd->autoneg = AUTONEG_ENABLE;
4332 }
4333 else {
4334 cmd->autoneg = AUTONEG_DISABLE;
4335 }
4336
4337 if (netif_carrier_ok(dev)) {
4338 cmd->speed = bp->line_speed;
4339 cmd->duplex = bp->duplex;
4340 }
4341 else {
4342 cmd->speed = -1;
4343 cmd->duplex = -1;
4344 }
4345
4346 cmd->transceiver = XCVR_INTERNAL;
4347 cmd->phy_address = bp->phy_addr;
4348
4349 return 0;
4350}
4351
4352static int
4353bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4354{
4355 struct bnx2 *bp = dev->priv;
4356 u8 autoneg = bp->autoneg;
4357 u8 req_duplex = bp->req_duplex;
4358 u16 req_line_speed = bp->req_line_speed;
4359 u32 advertising = bp->advertising;
4360
4361 if (cmd->autoneg == AUTONEG_ENABLE) {
4362 autoneg |= AUTONEG_SPEED;
4363
4364 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4365
4366 /* allow advertising 1 speed */
4367 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4368 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4369 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4370 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4371
4372 if (bp->phy_flags & PHY_SERDES_FLAG)
4373 return -EINVAL;
4374
4375 advertising = cmd->advertising;
4376
4377 }
4378 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4379 advertising = cmd->advertising;
4380 }
4381 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4382 return -EINVAL;
4383 }
4384 else {
4385 if (bp->phy_flags & PHY_SERDES_FLAG) {
4386 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4387 }
4388 else {
4389 advertising = ETHTOOL_ALL_COPPER_SPEED;
4390 }
4391 }
4392 advertising |= ADVERTISED_Autoneg;
4393 }
4394 else {
4395 if (bp->phy_flags & PHY_SERDES_FLAG) {
4396 if ((cmd->speed != SPEED_1000) ||
4397 (cmd->duplex != DUPLEX_FULL)) {
4398 return -EINVAL;
4399 }
4400 }
4401 else if (cmd->speed == SPEED_1000) {
4402 return -EINVAL;
4403 }
4404 autoneg &= ~AUTONEG_SPEED;
4405 req_line_speed = cmd->speed;
4406 req_duplex = cmd->duplex;
4407 advertising = 0;
4408 }
4409
4410 bp->autoneg = autoneg;
4411 bp->advertising = advertising;
4412 bp->req_line_speed = req_line_speed;
4413 bp->req_duplex = req_duplex;
4414
4415 spin_lock_irq(&bp->phy_lock);
4416
4417 bnx2_setup_phy(bp);
4418
4419 spin_unlock_irq(&bp->phy_lock);
4420
4421 return 0;
4422}
4423
4424static void
4425bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4426{
4427 struct bnx2 *bp = dev->priv;
4428
4429 strcpy(info->driver, DRV_MODULE_NAME);
4430 strcpy(info->version, DRV_MODULE_VERSION);
4431 strcpy(info->bus_info, pci_name(bp->pdev));
4432 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4433 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4434 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4435 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4436 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4437 info->fw_version[7] = 0;
4438}
4439
4440static void
4441bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4442{
4443 struct bnx2 *bp = dev->priv;
4444
4445 if (bp->flags & NO_WOL_FLAG) {
4446 wol->supported = 0;
4447 wol->wolopts = 0;
4448 }
4449 else {
4450 wol->supported = WAKE_MAGIC;
4451 if (bp->wol)
4452 wol->wolopts = WAKE_MAGIC;
4453 else
4454 wol->wolopts = 0;
4455 }
4456 memset(&wol->sopass, 0, sizeof(wol->sopass));
4457}
4458
4459static int
4460bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4461{
4462 struct bnx2 *bp = dev->priv;
4463
4464 if (wol->wolopts & ~WAKE_MAGIC)
4465 return -EINVAL;
4466
4467 if (wol->wolopts & WAKE_MAGIC) {
4468 if (bp->flags & NO_WOL_FLAG)
4469 return -EINVAL;
4470
4471 bp->wol = 1;
4472 }
4473 else {
4474 bp->wol = 0;
4475 }
4476 return 0;
4477}
4478
4479static int
4480bnx2_nway_reset(struct net_device *dev)
4481{
4482 struct bnx2 *bp = dev->priv;
4483 u32 bmcr;
4484
4485 if (!(bp->autoneg & AUTONEG_SPEED)) {
4486 return -EINVAL;
4487 }
4488
4489 spin_lock_irq(&bp->phy_lock);
4490
4491 /* Force a link down visible on the other side */
4492 if (bp->phy_flags & PHY_SERDES_FLAG) {
4493 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4494 spin_unlock_irq(&bp->phy_lock);
4495
4496 msleep(20);
4497
4498 spin_lock_irq(&bp->phy_lock);
4499 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]4500 bp->current_interval = SERDES_AN_TIMEOUT;
4501 bp->serdes_an_pending = 1;
4502 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4503 }
4504 }
4505
4506 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4507 bmcr &= ~BMCR_LOOPBACK;
4508 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4509
4510 spin_unlock_irq(&bp->phy_lock);
4511
4512 return 0;
4513}
4514
4515static int
4516bnx2_get_eeprom_len(struct net_device *dev)
4517{
4518 struct bnx2 *bp = dev->priv;
4519
4520 if (bp->flash_info == 0)
4521 return 0;
4522
4523 return (int) bp->flash_info->total_size;
4524}
4525
4526static int
4527bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4528 u8 *eebuf)
4529{
4530 struct bnx2 *bp = dev->priv;
4531 int rc;
4532
4533 if (eeprom->offset > bp->flash_info->total_size)
4534 return -EINVAL;
4535
4536 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4537 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4538
4539 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4540
4541 return rc;
4542}
4543
4544static int
4545bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4546 u8 *eebuf)
4547{
4548 struct bnx2 *bp = dev->priv;
4549 int rc;
4550
4551 if (eeprom->offset > bp->flash_info->total_size)
4552 return -EINVAL;
4553
4554 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4555 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4556
4557 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4558
4559 return rc;
4560}
4561
4562static int
4563bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4564{
4565 struct bnx2 *bp = dev->priv;
4566
4567 memset(coal, 0, sizeof(struct ethtool_coalesce));
4568
4569 coal->rx_coalesce_usecs = bp->rx_ticks;
4570 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4571 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4572 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4573
4574 coal->tx_coalesce_usecs = bp->tx_ticks;
4575 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4576 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4577 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4578
4579 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4580
4581 return 0;
4582}
4583
4584static int
4585bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4586{
4587 struct bnx2 *bp = dev->priv;
4588
4589 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4590 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4591
4592 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4593 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4594
4595 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4596 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4597
4598 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4599 if (bp->rx_quick_cons_trip_int > 0xff)
4600 bp->rx_quick_cons_trip_int = 0xff;
4601
4602 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4603 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4604
4605 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4606 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4607
4608 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4609 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4610
4611 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4612 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4613 0xff;
4614
4615 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4616 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4617 bp->stats_ticks &= 0xffff00;
4618
4619 if (netif_running(bp->dev)) {
4620 bnx2_netif_stop(bp);
4621 bnx2_init_nic(bp);
4622 bnx2_netif_start(bp);
4623 }
4624
4625 return 0;
4626}
4627
4628static void
4629bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4630{
4631 struct bnx2 *bp = dev->priv;
4632
4633 ering->rx_max_pending = MAX_RX_DESC_CNT;
4634 ering->rx_mini_max_pending = 0;
4635 ering->rx_jumbo_max_pending = 0;
4636
4637 ering->rx_pending = bp->rx_ring_size;
4638 ering->rx_mini_pending = 0;
4639 ering->rx_jumbo_pending = 0;
4640
4641 ering->tx_max_pending = MAX_TX_DESC_CNT;
4642 ering->tx_pending = bp->tx_ring_size;
4643}
4644
4645static int
4646bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4647{
4648 struct bnx2 *bp = dev->priv;
4649
4650 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4651 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4652 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4653
4654 return -EINVAL;
4655 }
4656 bp->rx_ring_size = ering->rx_pending;
4657 bp->tx_ring_size = ering->tx_pending;
4658
4659 if (netif_running(bp->dev)) {
4660 bnx2_netif_stop(bp);
4661 bnx2_init_nic(bp);
4662 bnx2_netif_start(bp);
4663 }
4664
4665 return 0;
4666}
4667
4668static void
4669bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4670{
4671 struct bnx2 *bp = dev->priv;
4672
4673 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4674 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4675 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4676}
4677
4678static int
4679bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4680{
4681 struct bnx2 *bp = dev->priv;
4682
4683 bp->req_flow_ctrl = 0;
4684 if (epause->rx_pause)
4685 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4686 if (epause->tx_pause)
4687 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4688
4689 if (epause->autoneg) {
4690 bp->autoneg |= AUTONEG_FLOW_CTRL;
4691 }
4692 else {
4693 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4694 }
4695
4696 spin_lock_irq(&bp->phy_lock);
4697
4698 bnx2_setup_phy(bp);
4699
4700 spin_unlock_irq(&bp->phy_lock);
4701
4702 return 0;
4703}
4704
4705static u32
4706bnx2_get_rx_csum(struct net_device *dev)
4707{
4708 struct bnx2 *bp = dev->priv;
4709
4710 return bp->rx_csum;
4711}
4712
4713static int
4714bnx2_set_rx_csum(struct net_device *dev, u32 data)
4715{
4716 struct bnx2 *bp = dev->priv;
4717
4718 bp->rx_csum = data;
4719 return 0;
4720}
4721
4722#define BNX2_NUM_STATS 45
4723
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]4724static struct {
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4725 char string[ETH_GSTRING_LEN];
4726} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4727 { "rx_bytes" },
4728 { "rx_error_bytes" },
4729 { "tx_bytes" },
4730 { "tx_error_bytes" },
4731 { "rx_ucast_packets" },
4732 { "rx_mcast_packets" },
4733 { "rx_bcast_packets" },
4734 { "tx_ucast_packets" },
4735 { "tx_mcast_packets" },
4736 { "tx_bcast_packets" },
4737 { "tx_mac_errors" },
4738 { "tx_carrier_errors" },
4739 { "rx_crc_errors" },
4740 { "rx_align_errors" },
4741 { "tx_single_collisions" },
4742 { "tx_multi_collisions" },
4743 { "tx_deferred" },
4744 { "tx_excess_collisions" },
4745 { "tx_late_collisions" },
4746 { "tx_total_collisions" },
4747 { "rx_fragments" },
4748 { "rx_jabbers" },
4749 { "rx_undersize_packets" },
4750 { "rx_oversize_packets" },
4751 { "rx_64_byte_packets" },
4752 { "rx_65_to_127_byte_packets" },
4753 { "rx_128_to_255_byte_packets" },
4754 { "rx_256_to_511_byte_packets" },
4755 { "rx_512_to_1023_byte_packets" },
4756 { "rx_1024_to_1522_byte_packets" },
4757 { "rx_1523_to_9022_byte_packets" },
4758 { "tx_64_byte_packets" },
4759 { "tx_65_to_127_byte_packets" },
4760 { "tx_128_to_255_byte_packets" },
4761 { "tx_256_to_511_byte_packets" },
4762 { "tx_512_to_1023_byte_packets" },
4763 { "tx_1024_to_1522_byte_packets" },
4764 { "tx_1523_to_9022_byte_packets" },
4765 { "rx_xon_frames" },
4766 { "rx_xoff_frames" },
4767 { "tx_xon_frames" },
4768 { "tx_xoff_frames" },
4769 { "rx_mac_ctrl_frames" },
4770 { "rx_filtered_packets" },
4771 { "rx_discards" },
4772};
4773
4774#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4775
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]4776static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4777 STATS_OFFSET32(stat_IfHCInOctets_hi),
4778 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4779 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4780 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4781 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4782 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4783 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4784 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4785 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4786 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4787 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4788 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4789 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4790 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4791 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4792 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4793 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4794 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4795 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4796 STATS_OFFSET32(stat_EtherStatsCollisions),
4797 STATS_OFFSET32(stat_EtherStatsFragments),
4798 STATS_OFFSET32(stat_EtherStatsJabbers),
4799 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4800 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4801 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4802 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4803 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4804 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4805 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4806 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4807 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4808 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4809 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4810 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4811 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4812 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4813 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4814 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4815 STATS_OFFSET32(stat_XonPauseFramesReceived),
4816 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4817 STATS_OFFSET32(stat_OutXonSent),
4818 STATS_OFFSET32(stat_OutXoffSent),
4819 STATS_OFFSET32(stat_MacControlFramesReceived),
4820 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4821 STATS_OFFSET32(stat_IfInMBUFDiscards),
4822};
4823
4824/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4825 * skipped because of errata.
4826 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]4827static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4828 8,0,8,8,8,8,8,8,8,8,
4829 4,0,4,4,4,4,4,4,4,4,
4830 4,4,4,4,4,4,4,4,4,4,
4831 4,4,4,4,4,4,4,4,4,4,
4832 4,4,4,4,4,
4833};
4834
4835#define BNX2_NUM_TESTS 6
4836
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]4837static struct {
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4838 char string[ETH_GSTRING_LEN];
4839} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4840 { "register_test (offline)" },
4841 { "memory_test (offline)" },
4842 { "loopback_test (offline)" },
4843 { "nvram_test (online)" },
4844 { "interrupt_test (online)" },
4845 { "link_test (online)" },
4846};
4847
4848static int
4849bnx2_self_test_count(struct net_device *dev)
4850{
4851 return BNX2_NUM_TESTS;
4852}
4853
4854static void
4855bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4856{
4857 struct bnx2 *bp = dev->priv;
4858
4859 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4860 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4861 bnx2_netif_stop(bp);
4862 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4863 bnx2_free_skbs(bp);
4864
4865 if (bnx2_test_registers(bp) != 0) {
4866 buf[0] = 1;
4867 etest->flags |= ETH_TEST_FL_FAILED;
4868 }
4869 if (bnx2_test_memory(bp) != 0) {
4870 buf[1] = 1;
4871 etest->flags |= ETH_TEST_FL_FAILED;
4872 }
4873 if (bnx2_test_loopback(bp) != 0) {
4874 buf[2] = 1;
4875 etest->flags |= ETH_TEST_FL_FAILED;
4876 }
4877
4878 if (!netif_running(bp->dev)) {
4879 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4880 }
4881 else {
4882 bnx2_init_nic(bp);
4883 bnx2_netif_start(bp);
4884 }
4885
4886 /* wait for link up */
4887 msleep_interruptible(3000);
4888 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4889 msleep_interruptible(4000);
4890 }
4891
4892 if (bnx2_test_nvram(bp) != 0) {
4893 buf[3] = 1;
4894 etest->flags |= ETH_TEST_FL_FAILED;
4895 }
4896 if (bnx2_test_intr(bp) != 0) {
4897 buf[4] = 1;
4898 etest->flags |= ETH_TEST_FL_FAILED;
4899 }
4900
4901 if (bnx2_test_link(bp) != 0) {
4902 buf[5] = 1;
4903 etest->flags |= ETH_TEST_FL_FAILED;
4904
4905 }
4906}
4907
4908static void
4909bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4910{
4911 switch (stringset) {
4912 case ETH_SS_STATS:
4913 memcpy(buf, bnx2_stats_str_arr,
4914 sizeof(bnx2_stats_str_arr));
4915 break;
4916 case ETH_SS_TEST:
4917 memcpy(buf, bnx2_tests_str_arr,
4918 sizeof(bnx2_tests_str_arr));
4919 break;
4920 }
4921}
4922
4923static int
4924bnx2_get_stats_count(struct net_device *dev)
4925{
4926 return BNX2_NUM_STATS;
4927}
4928
4929static void
4930bnx2_get_ethtool_stats(struct net_device *dev,
4931 struct ethtool_stats *stats, u64 *buf)
4932{
4933 struct bnx2 *bp = dev->priv;
4934 int i;
4935 u32 *hw_stats = (u32 *) bp->stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]4936 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]4937
4938 if (hw_stats == NULL) {
4939 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4940 return;
4941 }
4942
4943 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4944 stats_len_arr = bnx2_5706_stats_len_arr;
4945
4946 for (i = 0; i < BNX2_NUM_STATS; i++) {
4947 if (stats_len_arr[i] == 0) {
4948 /* skip this counter */
4949 buf[i] = 0;
4950 continue;
4951 }
4952 if (stats_len_arr[i] == 4) {
4953 /* 4-byte counter */
4954 buf[i] = (u64)
4955 *(hw_stats + bnx2_stats_offset_arr[i]);
4956 continue;
4957 }
4958 /* 8-byte counter */
4959 buf[i] = (((u64) *(hw_stats +
4960 bnx2_stats_offset_arr[i])) << 32) +
4961 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4962 }
4963}
4964
4965static int
4966bnx2_phys_id(struct net_device *dev, u32 data)
4967{
4968 struct bnx2 *bp = dev->priv;
4969 int i;
4970 u32 save;
4971
4972 if (data == 0)
4973 data = 2;
4974
4975 save = REG_RD(bp, BNX2_MISC_CFG);
4976 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4977
4978 for (i = 0; i < (data * 2); i++) {
4979 if ((i % 2) == 0) {
4980 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4981 }
4982 else {
4983 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4984 BNX2_EMAC_LED_1000MB_OVERRIDE |
4985 BNX2_EMAC_LED_100MB_OVERRIDE |
4986 BNX2_EMAC_LED_10MB_OVERRIDE |
4987 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4988 BNX2_EMAC_LED_TRAFFIC);
4989 }
4990 msleep_interruptible(500);
4991 if (signal_pending(current))
4992 break;
4993 }
4994 REG_WR(bp, BNX2_EMAC_LED, 0);
4995 REG_WR(bp, BNX2_MISC_CFG, save);
4996 return 0;
4997}
4998
4999static struct ethtool_ops bnx2_ethtool_ops = {
5000 .get_settings = bnx2_get_settings,
5001 .set_settings = bnx2_set_settings,
5002 .get_drvinfo = bnx2_get_drvinfo,
5003 .get_wol = bnx2_get_wol,
5004 .set_wol = bnx2_set_wol,
5005 .nway_reset = bnx2_nway_reset,
5006 .get_link = ethtool_op_get_link,
5007 .get_eeprom_len = bnx2_get_eeprom_len,
5008 .get_eeprom = bnx2_get_eeprom,
5009 .set_eeprom = bnx2_set_eeprom,
5010 .get_coalesce = bnx2_get_coalesce,
5011 .set_coalesce = bnx2_set_coalesce,
5012 .get_ringparam = bnx2_get_ringparam,
5013 .set_ringparam = bnx2_set_ringparam,
5014 .get_pauseparam = bnx2_get_pauseparam,
5015 .set_pauseparam = bnx2_set_pauseparam,
5016 .get_rx_csum = bnx2_get_rx_csum,
5017 .set_rx_csum = bnx2_set_rx_csum,
5018 .get_tx_csum = ethtool_op_get_tx_csum,
5019 .set_tx_csum = ethtool_op_set_tx_csum,
5020 .get_sg = ethtool_op_get_sg,
5021 .set_sg = ethtool_op_set_sg,
5022#ifdef BCM_TSO
5023 .get_tso = ethtool_op_get_tso,
5024 .set_tso = ethtool_op_set_tso,
5025#endif
5026 .self_test_count = bnx2_self_test_count,
5027 .self_test = bnx2_self_test,
5028 .get_strings = bnx2_get_strings,
5029 .phys_id = bnx2_phys_id,
5030 .get_stats_count = bnx2_get_stats_count,
5031 .get_ethtool_stats = bnx2_get_ethtool_stats,
5032};
5033
5034/* Called with rtnl_lock */
5035static int
5036bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5037{
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]5038 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5039 struct bnx2 *bp = dev->priv;
5040 int err;
5041
5042 switch(cmd) {
5043 case SIOCGMIIPHY:
5044 data->phy_id = bp->phy_addr;
5045
5046 /* fallthru */
5047 case SIOCGMIIREG: {
5048 u32 mii_regval;
5049
5050 spin_lock_irq(&bp->phy_lock);
5051 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5052 spin_unlock_irq(&bp->phy_lock);
5053
5054 data->val_out = mii_regval;
5055
5056 return err;
5057 }
5058
5059 case SIOCSMIIREG:
5060 if (!capable(CAP_NET_ADMIN))
5061 return -EPERM;
5062
5063 spin_lock_irq(&bp->phy_lock);
5064 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5065 spin_unlock_irq(&bp->phy_lock);
5066
5067 return err;
5068
5069 default:
5070 /* do nothing */
5071 break;
5072 }
5073 return -EOPNOTSUPP;
5074}
5075
5076/* Called with rtnl_lock */
5077static int
5078bnx2_change_mac_addr(struct net_device *dev, void *p)
5079{
5080 struct sockaddr *addr = p;
5081 struct bnx2 *bp = dev->priv;
5082
5083 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5084 if (netif_running(dev))
5085 bnx2_set_mac_addr(bp);
5086
5087 return 0;
5088}
5089
5090/* Called with rtnl_lock */
5091static int
5092bnx2_change_mtu(struct net_device *dev, int new_mtu)
5093{
5094 struct bnx2 *bp = dev->priv;
5095
5096 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5097 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5098 return -EINVAL;
5099
5100 dev->mtu = new_mtu;
5101 if (netif_running(dev)) {
5102 bnx2_netif_stop(bp);
5103
5104 bnx2_init_nic(bp);
5105
5106 bnx2_netif_start(bp);
5107 }
5108 return 0;
5109}
5110
5111#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5112static void
5113poll_bnx2(struct net_device *dev)
5114{
5115 struct bnx2 *bp = dev->priv;
5116
5117 disable_irq(bp->pdev->irq);
5118 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5119 enable_irq(bp->pdev->irq);
5120}
5121#endif
5122
5123static int __devinit
5124bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5125{
5126 struct bnx2 *bp;
5127 unsigned long mem_len;
5128 int rc;
5129 u32 reg;
5130
5131 SET_MODULE_OWNER(dev);
5132 SET_NETDEV_DEV(dev, &pdev->dev);
5133 bp = dev->priv;
5134
5135 bp->flags = 0;
5136 bp->phy_flags = 0;
5137
5138 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5139 rc = pci_enable_device(pdev);
5140 if (rc) {
5141 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5142 goto err_out;
5143 }
5144
5145 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5146 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5147 "aborting.\n");
5148 rc = -ENODEV;
5149 goto err_out_disable;
5150 }
5151
5152 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5153 if (rc) {
5154 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5155 goto err_out_disable;
5156 }
5157
5158 pci_set_master(pdev);
5159
5160 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5161 if (bp->pm_cap == 0) {
5162 printk(KERN_ERR PFX "Cannot find power management capability, "
5163 "aborting.\n");
5164 rc = -EIO;
5165 goto err_out_release;
5166 }
5167
5168 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5169 if (bp->pcix_cap == 0) {
5170 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5171 rc = -EIO;
5172 goto err_out_release;
5173 }
5174
5175 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5176 bp->flags |= USING_DAC_FLAG;
5177 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5178 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5179 "failed, aborting.\n");
5180 rc = -EIO;
5181 goto err_out_release;
5182 }
5183 }
5184 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5185 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5186 rc = -EIO;
5187 goto err_out_release;
5188 }
5189
5190 bp->dev = dev;
5191 bp->pdev = pdev;
5192
5193 spin_lock_init(&bp->phy_lock);
5194 spin_lock_init(&bp->tx_lock);
5195 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5196
5197 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5198 mem_len = MB_GET_CID_ADDR(17);
5199 dev->mem_end = dev->mem_start + mem_len;
5200 dev->irq = pdev->irq;
5201
5202 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5203
5204 if (!bp->regview) {
5205 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5206 rc = -ENOMEM;
5207 goto err_out_release;
5208 }
5209
5210 /* Configure byte swap and enable write to the reg_window registers.
5211 * Rely on CPU to do target byte swapping on big endian systems
5212 * The chip's target access swapping will not swap all accesses
5213 */
5214 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5215 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5216 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5217
5218 bnx2_set_power_state(bp, 0);
5219
5220 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5221
5222 bp->phy_addr = 1;
5223
5224 /* Get bus information. */
5225 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5226 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5227 u32 clkreg;
5228
5229 bp->flags |= PCIX_FLAG;
5230
5231 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5232
5233 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5234 switch (clkreg) {
5235 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5236 bp->bus_speed_mhz = 133;
5237 break;
5238
5239 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5240 bp->bus_speed_mhz = 100;
5241 break;
5242
5243 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5244 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5245 bp->bus_speed_mhz = 66;
5246 break;
5247
5248 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5249 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5250 bp->bus_speed_mhz = 50;
5251 break;
5252
5253 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5254 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5255 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5256 bp->bus_speed_mhz = 33;
5257 break;
5258 }
5259 }
5260 else {
5261 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5262 bp->bus_speed_mhz = 66;
5263 else
5264 bp->bus_speed_mhz = 33;
5265 }
5266
5267 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5268 bp->flags |= PCI_32BIT_FLAG;
5269
5270 /* 5706A0 may falsely detect SERR and PERR. */
5271 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5272 reg = REG_RD(bp, PCI_COMMAND);
5273 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5274 REG_WR(bp, PCI_COMMAND, reg);
5275 }
5276 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5277 !(bp->flags & PCIX_FLAG)) {
5278
5279 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5280 "aborting.\n");
5281 goto err_out_unmap;
5282 }
5283
5284 bnx2_init_nvram(bp);
5285
5286 /* Get the permanent MAC address. First we need to make sure the
5287 * firmware is actually running.
5288 */
5289 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5290
5291 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5292 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5293 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5294 rc = -ENODEV;
5295 goto err_out_unmap;
5296 }
5297
5298 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5299 BNX2_DEV_INFO_BC_REV);
5300
5301 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5302 bp->mac_addr[0] = (u8) (reg >> 8);
5303 bp->mac_addr[1] = (u8) reg;
5304
5305 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5306 bp->mac_addr[2] = (u8) (reg >> 24);
5307 bp->mac_addr[3] = (u8) (reg >> 16);
5308 bp->mac_addr[4] = (u8) (reg >> 8);
5309 bp->mac_addr[5] = (u8) reg;
5310
5311 bp->tx_ring_size = MAX_TX_DESC_CNT;
5312 bp->rx_ring_size = 100;
5313
5314 bp->rx_csum = 1;
5315
5316 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5317
5318 bp->tx_quick_cons_trip_int = 20;
5319 bp->tx_quick_cons_trip = 20;
5320 bp->tx_ticks_int = 80;
5321 bp->tx_ticks = 80;
5322
5323 bp->rx_quick_cons_trip_int = 6;
5324 bp->rx_quick_cons_trip = 6;
5325 bp->rx_ticks_int = 18;
5326 bp->rx_ticks = 18;
5327
5328 bp->stats_ticks = 1000000 & 0xffff00;
5329
5330 bp->timer_interval = HZ;
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]5331 bp->current_interval = HZ;
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5332
5333 /* Disable WOL support if we are running on a SERDES chip. */
5334 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5335 bp->phy_flags |= PHY_SERDES_FLAG;
5336 bp->flags |= NO_WOL_FLAG;
5337 }
5338
5339 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5340 bp->tx_quick_cons_trip_int =
5341 bp->tx_quick_cons_trip;
5342 bp->tx_ticks_int = bp->tx_ticks;
5343 bp->rx_quick_cons_trip_int =
5344 bp->rx_quick_cons_trip;
5345 bp->rx_ticks_int = bp->rx_ticks;
5346 bp->comp_prod_trip_int = bp->comp_prod_trip;
5347 bp->com_ticks_int = bp->com_ticks;
5348 bp->cmd_ticks_int = bp->cmd_ticks;
5349 }
5350
5351 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5352 bp->req_line_speed = 0;
5353 if (bp->phy_flags & PHY_SERDES_FLAG) {
5354 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]5355
5356 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5357 BNX2_PORT_HW_CFG_CONFIG);
5358 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5359 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5360 bp->autoneg = 0;
5361 bp->req_line_speed = bp->line_speed = SPEED_1000;
5362 bp->req_duplex = DUPLEX_FULL;
5363 }
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5364 }
5365 else {
5366 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5367 }
5368
5369 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5370
Michael Chancd339a02005-08-25 15:35:24 -0700[diff] [blame^]5371 init_timer(&bp->timer);
5372 bp->timer.expires = RUN_AT(bp->timer_interval);
5373 bp->timer.data = (unsigned long) bp;
5374 bp->timer.function = bnx2_timer;
5375
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5376 return 0;
5377
5378err_out_unmap:
5379 if (bp->regview) {
5380 iounmap(bp->regview);
5381 }
5382
5383err_out_release:
5384 pci_release_regions(pdev);
5385
5386err_out_disable:
5387 pci_disable_device(pdev);
5388 pci_set_drvdata(pdev, NULL);
5389
5390err_out:
5391 return rc;
5392}
5393
5394static int __devinit
5395bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5396{
5397 static int version_printed = 0;
5398 struct net_device *dev = NULL;
5399 struct bnx2 *bp;
5400 int rc, i;
5401
5402 if (version_printed++ == 0)
5403 printk(KERN_INFO "%s", version);
5404
5405 /* dev zeroed in init_etherdev */
5406 dev = alloc_etherdev(sizeof(*bp));
5407
5408 if (!dev)
5409 return -ENOMEM;
5410
5411 rc = bnx2_init_board(pdev, dev);
5412 if (rc < 0) {
5413 free_netdev(dev);
5414 return rc;
5415 }
5416
5417 dev->open = bnx2_open;
5418 dev->hard_start_xmit = bnx2_start_xmit;
5419 dev->stop = bnx2_close;
5420 dev->get_stats = bnx2_get_stats;
5421 dev->set_multicast_list = bnx2_set_rx_mode;
5422 dev->do_ioctl = bnx2_ioctl;
5423 dev->set_mac_address = bnx2_change_mac_addr;
5424 dev->change_mtu = bnx2_change_mtu;
5425 dev->tx_timeout = bnx2_tx_timeout;
5426 dev->watchdog_timeo = TX_TIMEOUT;
5427#ifdef BCM_VLAN
5428 dev->vlan_rx_register = bnx2_vlan_rx_register;
5429 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5430#endif
5431 dev->poll = bnx2_poll;
5432 dev->ethtool_ops = &bnx2_ethtool_ops;
5433 dev->weight = 64;
5434
5435 bp = dev->priv;
5436
5437#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5438 dev->poll_controller = poll_bnx2;
5439#endif
5440
5441 if ((rc = register_netdev(dev))) {
5442 printk(KERN_ERR PFX "Cannot register net device\n");
5443 if (bp->regview)
5444 iounmap(bp->regview);
5445 pci_release_regions(pdev);
5446 pci_disable_device(pdev);
5447 pci_set_drvdata(pdev, NULL);
5448 free_netdev(dev);
5449 return rc;
5450 }
5451
5452 pci_set_drvdata(pdev, dev);
5453
5454 memcpy(dev->dev_addr, bp->mac_addr, 6);
5455 bp->name = board_info[ent->driver_data].name,
5456 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5457 "IRQ %d, ",
5458 dev->name,
5459 bp->name,
5460 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5461 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5462 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5463 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5464 bp->bus_speed_mhz,
5465 dev->base_addr,
5466 bp->pdev->irq);
5467
5468 printk("node addr ");
5469 for (i = 0; i < 6; i++)
5470 printk("%2.2x", dev->dev_addr[i]);
5471 printk("\n");
5472
5473 dev->features |= NETIF_F_SG;
5474 if (bp->flags & USING_DAC_FLAG)
5475 dev->features |= NETIF_F_HIGHDMA;
5476 dev->features |= NETIF_F_IP_CSUM;
5477#ifdef BCM_VLAN
5478 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5479#endif
5480#ifdef BCM_TSO
5481 dev->features |= NETIF_F_TSO;
5482#endif
5483
5484 netif_carrier_off(bp->dev);
5485
5486 return 0;
5487}
5488
5489static void __devexit
5490bnx2_remove_one(struct pci_dev *pdev)
5491{
5492 struct net_device *dev = pci_get_drvdata(pdev);
5493 struct bnx2 *bp = dev->priv;
5494
Michael Chanafdc08b2005-08-25 15:34:29 -0700[diff] [blame]5495 flush_scheduled_work();
5496
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5497 unregister_netdev(dev);
5498
5499 if (bp->regview)
5500 iounmap(bp->regview);
5501
5502 free_netdev(dev);
5503 pci_release_regions(pdev);
5504 pci_disable_device(pdev);
5505 pci_set_drvdata(pdev, NULL);
5506}
5507
5508static int
5509bnx2_suspend(struct pci_dev *pdev, u32 state)
5510{
5511 struct net_device *dev = pci_get_drvdata(pdev);
5512 struct bnx2 *bp = dev->priv;
5513 u32 reset_code;
5514
5515 if (!netif_running(dev))
5516 return 0;
5517
5518 bnx2_netif_stop(bp);
5519 netif_device_detach(dev);
5520 del_timer_sync(&bp->timer);
5521 if (bp->wol)
5522 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5523 else
5524 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5525 bnx2_reset_chip(bp, reset_code);
5526 bnx2_free_skbs(bp);
5527 bnx2_set_power_state(bp, state);
5528 return 0;
5529}
5530
5531static int
5532bnx2_resume(struct pci_dev *pdev)
5533{
5534 struct net_device *dev = pci_get_drvdata(pdev);
5535 struct bnx2 *bp = dev->priv;
5536
5537 if (!netif_running(dev))
5538 return 0;
5539
5540 bnx2_set_power_state(bp, 0);
5541 netif_device_attach(dev);
5542 bnx2_init_nic(bp);
5543 bnx2_netif_start(bp);
5544 return 0;
5545}
5546
5547static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -0700[diff] [blame]5548 .name = DRV_MODULE_NAME,
5549 .id_table = bnx2_pci_tbl,
5550 .probe = bnx2_init_one,
5551 .remove = __devexit_p(bnx2_remove_one),
5552 .suspend = bnx2_suspend,
5553 .resume = bnx2_resume,
Michael Chanb6016b72005-05-26 13:03:09 -0700[diff] [blame]5554};
5555
5556static int __init bnx2_init(void)
5557{
5558 return pci_module_init(&bnx2_pci_driver);
5559}
5560
5561static void __exit bnx2_cleanup(void)
5562{
5563 pci_unregister_driver(&bnx2_pci_driver);
5564}
5565
5566module_init(bnx2_init);
5567module_exit(bnx2_cleanup);
5568
5569
5570